implemented GS/FS BASE access instructions published in _319433-007.pdf document
This commit is contained in:
Stanislav Shwartsman
parent
7f7c249934
commit
91ac0df65c
@ -179,6 +179,10 @@ cpu: count=1, ips=50000000, reset_on_triple_fault=1, ignore_bad_msrs=1, msrs="ms
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# Enable Process-Context Identifiers (PCID) support in long mode.
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# This option exists only if Bochs compiled with x86-64 support.
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#
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# FSGSBASE:
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# Enable GS/GS BASE access instructions support in long mode.
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# This option exists only if Bochs compiled with x86-64 support.
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#
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# MWAIT_IS_NOP:
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# When this option is enabled MWAIT will not put the CPU into a sleep state.
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# This option exists only if Bochs compiled with --enable-monitor-mwait.
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@ -1,4 +1,4 @@
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$Id: PARAM_TREE.txt,v 1.31 2010-07-03 05:34:27 vruppert Exp $
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$Id: PARAM_TREE.txt,v 1.32 2010-07-22 16:41:57 sshwarts Exp $
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Starting from Bochs 2.3 the parameters are organized in a tree structure
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instead of a huge flat list. The parameter tree was required for implementing
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@ -27,6 +27,7 @@ cpu
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cpuid
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cpuid_limit_winnt
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stepping
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vendor_string
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brand_string
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mmx
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@ -38,6 +39,7 @@ cpuid
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xapic
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1g_pages
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pcid
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fsgsbase
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mwait_is_nop
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memory
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: dbg_main.cc,v 1.237 2010-05-04 20:17:26 sshwarts Exp $
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// $Id: dbg_main.cc,v 1.238 2010-07-22 16:41:58 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2009 The Bochs Project
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@ -850,9 +850,10 @@ void bx_dbg_info_control_regs_command(void)
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dbg_printf(" PWT=page-level write-through=%d\n", (cr3>>3) & 1);
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#if BX_CPU_LEVEL >= 4
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Bit32u cr4 = SIM->get_param_num("CR4", dbg_cpu_list)->get();
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dbg_printf("CR4=0x%08x: %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s\n", cr4,
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dbg_printf("CR4=0x%08x: %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s\n", cr4,
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(cr4 & (1<<18)) ? "OSXSAVE" : "osxsave",
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(cr4 & (1<<17)) ? "PCID" : "pcid",
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(cr4 & (1<<16)) ? "FSGSBASE" : "fsgsbase",
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(cr4 & (1<<14)) ? "SMX" : "smx",
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(cr4 & (1<<13)) ? "VMX" : "vmx",
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(cr4 & (1<<10)) ? "OSXMMEXCPT" : "osxmmexcpt",
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: config.cc,v 1.209 2010-07-16 21:10:48 sshwarts Exp $
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// $Id: config.cc,v 1.210 2010-07-22 16:41:58 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002-2009 The Bochs Project
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@ -366,7 +366,7 @@ void bx_init_options()
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cpu_param->set_options(menu->SHOW_PARENT);
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// cpuid subtree
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bx_list_c *cpuid_param = new bx_list_c(root_param, "cpuid", "CPUID Options", 15);
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bx_list_c *cpuid_param = new bx_list_c(root_param, "cpuid", "CPUID Options", 16);
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new bx_param_bool_c(cpuid_param,
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"cpuid_limit_winnt", "Limit max CPUID function to 3",
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@ -446,6 +446,10 @@ void bx_init_options()
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"pcid", "PCID support in long mode",
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"Support for process context ID (PCID) in long mode",
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0);
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new bx_param_bool_c(cpuid_param,
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"fsgsbase", "FS/GS BASE access instructions support",
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"FS/GS BASE access instructions support in long mode",
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0);
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#endif
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#if BX_SUPPORT_MONITOR_MWAIT
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new bx_param_bool_c(cpuid_param,
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@ -2717,6 +2721,10 @@ static int parse_line_formatted(const char *context, int num_params, char *param
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if (parse_param_bool(params[i], 5, BXPN_CPUID_PCID) < 0) {
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PARSE_ERR(("%s: cpuid directive malformed.", context));
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}
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} else if (!strncmp(params[i], "fsgsbase=", 9)) {
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if (parse_param_bool(params[i], 9, BXPN_CPUID_FSGSBASE) < 0) {
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PARSE_ERR(("%s: cpuid directive malformed.", context));
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}
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#endif
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#if BX_SUPPORT_MONITOR_MWAIT
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} else if (!strncmp(params[i], "mwait_is_nop=", 13)) {
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@ -3893,9 +3901,10 @@ int bx_write_configuration(const char *rc, int overwrite)
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SIM->get_param_bool(BXPN_CPUID_XSAVE)->get(),
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SIM->get_param_bool(BXPN_CPUID_MOVBE)->get());
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#if BX_SUPPORT_X86_64
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fprintf(fp, ", 1g_pages=%d, pcid=%d",
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fprintf(fp, ", 1g_pages=%d, pcid=%d fsgsbase=%d",
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SIM->get_param_bool(BXPN_CPUID_1G_PAGES)->get(),
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SIM->get_param_bool(BXPN_CPUID_PCID)->get());
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SIM->get_param_bool(BXPN_CPUID_PCID)->get(),
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SIM->get_param_bool(BXPN_CPUID_FSGSBASE)->get());
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#endif
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#if BX_SUPPORT_MONITOR_MWAIT
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fprintf(fp, ", mwait_is_nop=%d", SIM->get_param_bool(BXPN_CPUID_MWAIT_IS_NOP)->get());
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.681 2010-07-22 15:12:08 sshwarts Exp $
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// $Id: cpu.h,v 1.682 2010-07-22 16:41:58 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2010 The Bochs Project
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@ -2735,10 +2735,15 @@ public: // for now...
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BX_SMF void SYSCALL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SYSRET(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SWAPGS(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void RDTSCP(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void CMPXCHG16B(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void SWAPGS(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void RDFSBASE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void RDGSBASE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void WRFSBASE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void WRGSBASE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOOPNE64_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOOPE64_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOOP64_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -3270,6 +3275,7 @@ public: // for now...
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BX_SMF BX_CPP_INLINE int bx_cpuid_support_pse(void);
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BX_SMF BX_CPP_INLINE int bx_cpuid_support_pse36(void);
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BX_SMF BX_CPP_INLINE int bx_cpuid_support_pcid(void);
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BX_SMF BX_CPP_INLINE int bx_cpuid_support_fsgsbase(void);
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BX_SMF BX_CPP_INLINE unsigned which_cpu(void) { return BX_CPU_THIS_PTR bx_cpuid; }
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BX_SMF BX_CPP_INLINE const bx_gen_reg_t *get_gen_regfile() { return BX_CPU_THIS_PTR gen_reg; }
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@ -3693,6 +3699,15 @@ BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_pcid(void)
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#endif
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}
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BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_fsgsbase(void)
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{
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#if BX_SUPPORT_X86_64
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return BX_CPU_THIS_PTR cpuid_std_function[7].ecx & 0x1;
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#else
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return 0;
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#endif
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}
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BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_vme(void)
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{
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return (BX_CPU_THIS_PTR cpuid_std_function[1].edx >> 1) & 0x1;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpuid.cc,v 1.121 2010-07-22 15:12:08 sshwarts Exp $
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// $Id: cpuid.cc,v 1.122 2010-07-22 16:41:59 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2007-2010 Stanislav Shwartsman
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@ -218,9 +218,14 @@ Bit32u BX_CPU_C::get_extended_cpuid_features(void)
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Bit32u BX_CPU_C::get_ext2_cpuid_features(void)
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{
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// [0:0] FS/GS BASE access instructions
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Bit32u features = 0;
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return 0;
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// [0:0] FS/GS BASE access instructions
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// [31:1] Reserved
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if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_FSGSBASE))
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features |= 1;
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return features;
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}
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/* Get CPU feature flags. Returned by CPUID functions 1 and 80000001. */
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@ -561,6 +566,7 @@ void BX_CPU_C::set_cpuid_defaults(void)
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else
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cpuid->eax = 0; /* leaf 7 not supported */
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BX_INFO(("CPUID[0x00000007]: %08x %08x %08x %08x", cpuid->eax, cpuid->ebx, cpuid->ecx, cpuid->edx));
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// ------------------------------------------------------
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// CPUID function 0x0000000d
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@ -932,6 +938,9 @@ void BX_CPU_C::init_isa_features_bitmask(void)
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xapic_enabled = SIM->get_param_bool(BXPN_CPUID_XAPIC)->get();
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sse_enabled = SIM->get_param_enum(BXPN_CPUID_SSE)->get();
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#endif
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#if BX_SUPPORT_X86_64
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bx_bool fsgsbase_enabled = SIM->get_param_bool(BXPN_CPUID_FSGSBASE)->get();
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#endif
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// sanity checks
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#if BX_SUPPORT_3DNOW
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@ -1074,6 +1083,9 @@ void BX_CPU_C::init_isa_features_bitmask(void)
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#if BX_SUPPORT_X86_64
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features_bitmask |= BX_CPU_X86_64;
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if (fsgsbase_enabled)
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features_bitmask |= BX_CPU_FSGSBASE;
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#endif
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BX_CPU_THIS_PTR isa_extensions_bitmask = features_bitmask;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: crregs.cc,v 1.18 2010-05-12 21:33:04 sshwarts Exp $
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// $Id: crregs.cc,v 1.19 2010-07-22 16:41:59 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2010 Stanislav Shwartsman
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@ -909,7 +909,8 @@ Bit32u BX_CPU_C::get_cr4_allow_mask(void)
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// [31-19] Reserved, Must be Zero
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// [18] OSXSAVE: Operating System XSAVE Support R/W
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// [17] PCIDE: PCID Support R/W
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// [16-15] Reserved, Must be Zero
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// [16] FSGSBASE: FS/GS BASE access R/W
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// [15] Reserved, Must be Zero
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// [14] SMXE: SMX Extensions R/W
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// [13] VMXE: VMX Extensions R/W
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// [12-11] Reserved, Must be Zero
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@ -975,6 +976,9 @@ Bit32u BX_CPU_C::get_cr4_allow_mask(void)
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#if BX_SUPPORT_X86_64
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if (bx_cpuid_support_pcid())
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allowMask |= BX_CR4_PCIDE_MASK;
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if (bx_cpuid_support_fsgsbase())
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allowMask |= BX_CR4_FSGSBASE_MASK;
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#endif
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#if BX_CPU_LEVEL >= 6
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.h,v 1.103 2010-05-18 07:28:04 sshwarts Exp $
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// $Id: fetchdecode.h,v 1.104 2010-07-22 16:41:59 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2005-2010 Stanislav Shwartsman
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@ -971,4 +971,17 @@ static const BxOpcodeInfo_t BxOpcodeInfoG15R[8] = {
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/* 7 */ { BxPrefixSSE, BX_IA_SFENCE, BxOpcodeGroupSSE_ERR }
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};
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#if BX_SUPPORT_X86_64
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static const BxOpcodeInfo_t BxOpcodeInfoG15R64[8] = {
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/* 0 */ { BxPrefixSSEF3, BX_IA_RDFSBASE },
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/* 1 */ { BxPrefixSSEF3, BX_IA_RDGSBASE },
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/* 2 */ { BxPrefixSSEF3, BX_IA_WRFSBASE },
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/* 3 */ { BxPrefixSSEF3, BX_IA_WRGSBASE },
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/* 4 */ { 0, BX_IA_ERROR },
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/* 5 */ { BxPrefixSSE, BX_IA_LFENCE, BxOpcodeGroupSSE_ERR },
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/* 6 */ { BxPrefixSSE, BX_IA_MFENCE, BxOpcodeGroupSSE_ERR },
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/* 7 */ { BxPrefixSSE, BX_IA_SFENCE, BxOpcodeGroupSSE_ERR }
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};
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#endif
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#endif // BX_COMMON_FETCHDECODE_TABLES_H
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode64.cc,v 1.269 2010-05-26 18:37:54 sshwarts Exp $
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// $Id: fetchdecode64.cc,v 1.270 2010-07-22 16:41:59 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2010 The Bochs Project
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@ -1017,7 +1017,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3*2] = {
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/* 0F AC /wm */ { BxImmediate_Ib, BX_IA_SHRD_EwGwM },
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/* 0F AD /wr */ { 0, BX_IA_SHRD_EwGwR },
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/* 0F AD /wm */ { 0, BX_IA_SHRD_EwGwM },
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/* 0F AE /wr */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15R },
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/* 0F AE /wr */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15R64 },
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/* 0F AE /wm */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15M },
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/* 0F AF /wr */ { 0, BX_IA_IMUL_GwEwR },
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/* 0F AF /wm */ { 0, BX_IA_IMUL_GwEwM },
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@ -2044,7 +2044,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3*2] = {
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/* 0F AC /dm */ { BxImmediate_Ib, BX_IA_SHRD_EdGdM },
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/* 0F AD /dr */ { 0, BX_IA_SHRD_EdGdR },
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/* 0F AD /dm */ { 0, BX_IA_SHRD_EdGdM },
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/* 0F AE /dr */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15R },
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/* 0F AE /dr */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15R64 },
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/* 0F AE /dm */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15M },
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/* 0F AF /dr */ { 0, BX_IA_IMUL_GdEdR },
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/* 0F AF /dm */ { 0, BX_IA_IMUL_GdEdM },
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@ -3071,7 +3071,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3*2] = {
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/* 0F AC /qm */ { BxImmediate_Ib, BX_IA_SHRD_EqGqM },
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/* 0F AD /qr */ { 0, BX_IA_SHRD_EqGqR },
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/* 0F AD /qm */ { 0, BX_IA_SHRD_EqGqM },
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/* 0F AE /qr */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15R },
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/* 0F AE /qr */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15R64 },
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/* 0F AE /qm */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15M },
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/* 0F AF /qr */ { 0, BX_IA_IMUL_GqEqR },
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/* 0F AF /qm */ { 0, BX_IA_IMUL_GqEqM },
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: ia_opcodes.h,v 1.49 2010-05-18 07:28:04 sshwarts Exp $
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// $Id: ia_opcodes.h,v 1.50 2010-07-22 16:41:59 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2008-2010 Stanislav Shwartsman
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@ -1620,7 +1620,6 @@ bx_define_opcode(BX_IA_SGDT64_Ms, &BX_CPU_C::SGDT64_Ms, NULL, BX_CPU_X86_64)
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bx_define_opcode(BX_IA_SIDT64_Ms, &BX_CPU_C::SIDT64_Ms, NULL, BX_CPU_X86_64)
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bx_define_opcode(BX_IA_LGDT64_Ms, &BX_CPU_C::LGDT64_Ms, NULL, BX_CPU_X86_64)
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bx_define_opcode(BX_IA_LIDT64_Ms, &BX_CPU_C::LIDT64_Ms, NULL, BX_CPU_X86_64)
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bx_define_opcode(BX_IA_SWAPGS, &BX_CPU_C::SWAPGS, NULL, BX_CPU_X86_64)
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bx_define_opcode(BX_IA_RDTSCP, &BX_CPU_C::RDTSCP, NULL, BX_CPU_X86_64)
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bx_define_opcode(BX_IA_CMPXCHG16B, &BX_CPU_C::CMPXCHG16B, NULL, BX_CPU_X86_64)
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bx_define_opcode(BX_IA_LOOPNE64_Jb, &BX_CPU_C::LOOPNE64_Jb, NULL, BX_CPU_X86_64)
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@ -1636,6 +1635,11 @@ bx_define_opcode(BX_IA_MOVQ_VdqEqM, &BX_CPU_C::MOVQ_VqWqM, NULL, BX_CPU_X86_64)
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bx_define_opcode(BX_IA_MOVNTI_MqGq, &BX_CPU_C::MOVNTI_MqGq, NULL, BX_CPU_X86_64)
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bx_define_opcode(BX_IA_SYSCALL, &BX_CPU_C::SYSCALL, NULL, BX_CPU_X86_64)
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bx_define_opcode(BX_IA_SYSRET, &BX_CPU_C::SYSRET, NULL, BX_CPU_X86_64)
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bx_define_opcode(BX_IA_SWAPGS, &BX_CPU_C::SWAPGS, NULL, BX_CPU_X86_64)
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bx_define_opcode(BX_IA_RDFSBASE, &BX_CPU_C::RDFSBASE, NULL, BX_CPU_X86_64 | BX_CPU_FSGSBASE)
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bx_define_opcode(BX_IA_RDGSBASE, &BX_CPU_C::RDGSBASE, NULL, BX_CPU_X86_64 | BX_CPU_FSGSBASE)
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bx_define_opcode(BX_IA_WRFSBASE, &BX_CPU_C::WRFSBASE, NULL, BX_CPU_X86_64 | BX_CPU_FSGSBASE)
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bx_define_opcode(BX_IA_WRGSBASE, &BX_CPU_C::WRGSBASE, NULL, BX_CPU_X86_64 | BX_CPU_FSGSBASE)
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||||
#endif
|
||||
|
||||
// VMX
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: proc_ctrl.cc,v 1.334 2010-07-15 20:18:03 sshwarts Exp $
|
||||
// $Id: proc_ctrl.cc,v 1.335 2010-07-22 16:41:59 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001-2010 The Bochs Project
|
||||
@ -1274,4 +1274,72 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SWAPGS(bxInstruction_c *i)
|
||||
MSR_GSBASE = MSR_KERNELGSBASE;
|
||||
MSR_KERNELGSBASE = temp_GS_base;
|
||||
}
|
||||
|
||||
/* F3 0F AE /0 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::RDFSBASE(bxInstruction_c *i)
|
||||
{
|
||||
if (! BX_CPU_THIS_PTR cr4.get_FSGSBASE())
|
||||
exception(BX_UD_EXCEPTION, 0);
|
||||
|
||||
if (i->os64L()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), MSR_FSBASE);
|
||||
}
|
||||
else {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), (Bit32u) MSR_FSBASE);
|
||||
}
|
||||
}
|
||||
|
||||
/* F3 0F AE /1 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::RDGSBASE(bxInstruction_c *i)
|
||||
{
|
||||
if (! BX_CPU_THIS_PTR cr4.get_FSGSBASE())
|
||||
exception(BX_UD_EXCEPTION, 0);
|
||||
|
||||
if (i->os64L()) {
|
||||
BX_WRITE_64BIT_REG(i->rm(), MSR_GSBASE);
|
||||
}
|
||||
else {
|
||||
BX_WRITE_32BIT_REGZ(i->rm(), (Bit32u) MSR_GSBASE);
|
||||
}
|
||||
}
|
||||
|
||||
/* F3 0F AE /2 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::WRFSBASE(bxInstruction_c *i)
|
||||
{
|
||||
if (! BX_CPU_THIS_PTR cr4.get_FSGSBASE())
|
||||
exception(BX_UD_EXCEPTION, 0);
|
||||
|
||||
if (i->os64L()) {
|
||||
Bit64u fsbase = BX_READ_64BIT_REG(i->rm());
|
||||
if (!IsCanonical(fsbase)) {
|
||||
BX_ERROR(("WRFSBASE: canonical failure !"));
|
||||
exception(BX_GP_EXCEPTION, 0);
|
||||
}
|
||||
MSR_FSBASE = fsbase;
|
||||
}
|
||||
else {
|
||||
// 32-bit value is always canonical
|
||||
MSR_FSBASE = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
}
|
||||
|
||||
/* F3 0F AE /3 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::WRGSBASE(bxInstruction_c *i)
|
||||
{
|
||||
if (! BX_CPU_THIS_PTR cr4.get_FSGSBASE())
|
||||
exception(BX_UD_EXCEPTION, 0);
|
||||
|
||||
if (i->os64L()) {
|
||||
Bit64u gsbase = BX_READ_64BIT_REG(i->rm());
|
||||
if (!IsCanonical(gsbase)) {
|
||||
BX_ERROR(("WRGSBASE: canonical failure !"));
|
||||
exception(BX_GP_EXCEPTION, 0);
|
||||
}
|
||||
MSR_GSBASE = gsbase;
|
||||
}
|
||||
else {
|
||||
// 32-bit value is always canonical
|
||||
MSR_GSBASE = BX_READ_32BIT_REG(i->rm());
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: param_names.h,v 1.10 2010-07-16 21:03:52 sshwarts Exp $
|
||||
// $Id: param_names.h,v 1.11 2010-07-22 16:41:58 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2009 The Bochs Project
|
||||
@ -54,6 +54,7 @@
|
||||
#define BXPN_CPUID_MWAIT_IS_NOP "cpuid.mwait_is_nop"
|
||||
#define BXPN_CPUID_1G_PAGES "cpuid.1g_pages"
|
||||
#define BXPN_CPUID_PCID "cpuid.pcid"
|
||||
#define BXPN_CPUID_FSGSBASE "cpuid.fsgsbase"
|
||||
#define BXPN_MEM_SIZE "memory.standard.ram.size"
|
||||
#define BXPN_HOST_MEM_SIZE "memory.standard.ram.host_size"
|
||||
#define BXPN_ROM_PATH "memory.standard.rom.path"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user