disasm and some cpuid code according to recently published AVX_319433-007.pdf document
This commit is contained in:
Stanislav Shwartsman
parent
21e39a66c9
commit
7f7c249934
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.680 2010-05-23 19:17:40 sshwarts Exp $
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// $Id: cpu.h,v 1.681 2010-07-22 15:12:08 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2010 The Bochs Project
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@ -625,11 +625,13 @@ typedef struct
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#define BX_CPU_SMX 0x00040000 /* SMX instruction */
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#define BX_CPU_SVM 0x00080000 /* SVM instruction */
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#define BX_CPU_XSAVE 0x00100000 /* XSAVE/XRSTOR extensions instruction */
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#define BX_CPU_AES_PCLMULQDQ 0x00200000 /* AES+PCLMULQDQ instructions */
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#define BX_CPU_MOVBE 0x00400000 /* MOVBE Intel Atom(R) instruction */
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#define BX_CPU_AVX 0x00800000 /* AVX instruction */
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#define BX_CPU_AVX_FMA 0x01000000 /* AVX FMA instruction */
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#define BX_CPU_X86_64 0x02000000 /* x86-64 instruction */
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#define BX_CPU_XSAVEOPT 0x00200000 /* XSAVEOPT instruction */
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#define BX_CPU_AES_PCLMULQDQ 0x00400000 /* AES+PCLMULQDQ instructions */
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#define BX_CPU_MOVBE 0x00800000 /* MOVBE Intel Atom(R) instruction */
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#define BX_CPU_FSGSBASE 0x01000000 /* FS/GS BASE access instructions */
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#define BX_CPU_AVX 0x02000000 /* AVX instruction */
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#define BX_CPU_AVX_FMA 0x04000000 /* AVX FMA instruction */
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#define BX_CPU_X86_64 0x08000000 /* x86-64 instruction */
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struct cpuid_function_t {
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Bit32u eax;
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@ -3246,6 +3248,7 @@ public: // for now...
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BX_SMF Bit32u get_cpu_version_information(void);
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BX_SMF Bit32u get_extended_cpuid_features(void);
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BX_SMF Bit32u get_ext2_cpuid_features(void);
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BX_SMF Bit32u get_std_cpuid_features(void);
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BX_SMF void set_cpuid_defaults(void);
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@ -3256,6 +3259,7 @@ public: // for now...
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#endif
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#if BX_CPU_LEVEL >= 6
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BX_SMF void bx_cpuid_xsave_leaf(Bit32u subfunction);
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BX_SMF void bx_cpuid_extended_cpuid_leaf(Bit32u subfunction);
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#endif
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BX_SMF BX_CPP_INLINE int bx_cpuid_support_debug_extensions(void);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpuid.cc,v 1.120 2010-07-16 21:03:52 sshwarts Exp $
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// $Id: cpuid.cc,v 1.121 2010-07-22 15:12:08 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2007-2010 Stanislav Shwartsman
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@ -142,7 +142,8 @@ Bit32u BX_CPU_C::get_extended_cpuid_features(void)
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// [12:12] FMA Instructions support
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// [13:13] CMPXCHG16B: CMPXCHG16B instruction support
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// [14:14] xTPR update control
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// [16:15] reserved
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// [15:15] PDCM - Perfon and Debug Capability MSR
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// [16:16] reserved
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// [17:17] PCID: Process Context Identifiers
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// [18:18] DCA - Direct Cache Access
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// [19:19] SSE4.1 Instructions
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@ -155,7 +156,9 @@ Bit32u BX_CPU_C::get_extended_cpuid_features(void)
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// [26:26] XSAVE extensions support
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// [27:27] OSXSAVE support
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// [28:28] AVX extensions support
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// [31:29] reserved
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// [29:29] F16C - Float16 conversion support
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// [30:30] RDRAND instruction
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// [31:31] reserved
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Bit32u features = 0;
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@ -213,6 +216,13 @@ Bit32u BX_CPU_C::get_extended_cpuid_features(void)
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return features;
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}
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Bit32u BX_CPU_C::get_ext2_cpuid_features(void)
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{
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// [0:0] FS/GS BASE access instructions
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return 0;
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}
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/* Get CPU feature flags. Returned by CPUID functions 1 and 80000001. */
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Bit32u BX_CPU_C::get_std_cpuid_features(void)
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{
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@ -340,6 +350,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CPUID(bxInstruction_c *i)
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}
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#endif
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#if BX_CPU_LEVEL >= 6
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if (function == 0x7) {
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bx_cpuid_extended_cpuid_leaf(subfunction);
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return;
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}
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if (function == 0xd) {
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bx_cpuid_xsave_leaf(subfunction);
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return;
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@ -462,71 +476,10 @@ void BX_CPU_C::set_cpuid_defaults(void)
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cpuid->ebx |= ((BX_CPU_THIS_PTR lapic.get_id() & 0xff) << 24);
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#endif
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// ECX: Extended Feature Flags
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// [0:0] SSE3: SSE3 Instructions
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// [1:1] PCLMULQDQ Instruction support
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// [2:2] DTES64: 64-bit DS area
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// [3:3] MONITOR/MWAIT support
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// [4:4] DS-CPL: CPL qualified debug store
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// [5:5] VMX: Virtual Machine Technology
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// [6:6] SMX: Secure Virtual Machine Technology
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// [7:7] EST: Enhanced Intel SpeedStep Technology
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// [8:8] TM2: Thermal Monitor 2
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// [9:9] SSSE3: SSSE3 Instructions
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// [10:10] CNXT-ID: L1 context ID
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// [11:11] reserved
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// [12:12] FMA Instructions support
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// [13:13] CMPXCHG16B: CMPXCHG16B instruction support
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// [14:14] xTPR update control
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// [16:15] reserved
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// [17:17] PCID: Process Context Identifiers
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// [18:18] DCA - Direct Cache Access
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// [19:19] SSE4.1 Instructions
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// [20:20] SSE4.2 Instructions
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// [21:21] X2APIC
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// [22:22] MOVBE instruction
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// [23:23] POPCNT instruction
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// [24:24] TSC Deadline
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// [25:25] AES Instructions
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// [26:26] XSAVE extensions support
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// [27:27] OSXSAVE support
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// [28:28] AVX extensions support
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// [31:29] reserved
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// ECX: Extended Feature Flags
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cpuid->ecx = get_extended_cpuid_features();
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// EDX: Standard Feature Flags
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// [0:0] FPU on chip
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// [1:1] VME: Virtual-8086 Mode enhancements
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// [2:2] DE: Debug Extensions (I/O breakpoints)
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// [3:3] PSE: Page Size Extensions
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// [4:4] TSC: Time Stamp Counter
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// [5:5] MSR: RDMSR and WRMSR support
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// [6:6] PAE: Physical Address Extensions
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// [7:7] MCE: Machine Check Exception
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// [8:8] CXS: CMPXCHG8B instruction
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// [9:9] APIC: APIC on Chip
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// [10:10] Reserved
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// [11:11] SYSENTER/SYSEXIT support
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// [12:12] MTRR: Memory Type Range Reg
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// [13:13] PGE/PTE Global Bit
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// [14:14] MCA: Machine Check Architecture
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// [15:15] CMOV: Cond Mov/Cmp Instructions
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// [16:16] PAT: Page Attribute Table
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// [17:17] PSE-36: Physical Address Extensions
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// [18:18] PSN: Processor Serial Number
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// [19:19] CLFLUSH: CLFLUSH Instruction support
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// [20:20] Reserved
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// [21:21] DS: Debug Store
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// [22:22] ACPI: Thermal Monitor and Software Controlled Clock Facilities
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// [23:23] MMX Technology
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// [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
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// [25:25] SSE: SSE Extensions
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// [26:26] SSE2: SSE2 Extensions
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// [27:27] Self Snoop
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// [28:28] Hyper Threading Technology
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// [29:29] TM: Thermal Monitor
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// [30:30] Reserved
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// [31:31] PBE: Pending Break Enable
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// EDX: Standard Feature Flags
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cpuid->edx = get_std_cpuid_features();
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BX_INFO(("CPUID[0x00000001]: %08x %08x %08x %08x", cpuid->eax, cpuid->ebx, cpuid->ecx, cpuid->edx));
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@ -596,6 +549,19 @@ void BX_CPU_C::set_cpuid_defaults(void)
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BX_INFO(("CPUID[0x00000005]: %08x %08x %08x %08x", cpuid->eax, cpuid->ebx, cpuid->ecx, cpuid->edx));
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#endif
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// ------------------------------------------------------
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// CPUID function 0x00000007
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cpuid = &(BX_CPU_THIS_PTR cpuid_std_function[7]);
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cpuid->ebx = get_ext2_cpuid_features();
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cpuid->ecx = 0;
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cpuid->edx = 0;
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if (cpuid->ebx)
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cpuid->eax = 1; /* report max sub-leaves that are supported in leaf 7 */
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else
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cpuid->eax = 0; /* leaf 7 not supported */
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// ------------------------------------------------------
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// CPUID function 0x0000000d
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if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_XSAVE))
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@ -912,6 +878,22 @@ void BX_CPU_C::bx_cpuid_extended_topology_leaf(Bit32u subfunction)
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#endif
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#if BX_CPU_LEVEL >= 6
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void BX_CPU_C::bx_cpuid_extended_cpuid_leaf(Bit32u subfunction)
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{
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if (subfunction == 0) {
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RAX = BX_CPU_THIS_PTR cpuid_std_function[0x7].eax;
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RBX = BX_CPU_THIS_PTR cpuid_std_function[0x7].ebx;
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RCX = BX_CPU_THIS_PTR cpuid_std_function[0x7].ecx;
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RDX = BX_CPU_THIS_PTR cpuid_std_function[0x7].edx;
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}
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else {
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RAX = 0; // reserved
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RBX = 0; // reserved
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RCX = 0; // reserved
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RDX = 0; // reserved
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}
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}
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void BX_CPU_C::bx_cpuid_xsave_leaf(Bit32u subfunction)
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{
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BX_ASSERT(BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_XSAVE));
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: crregs.h,v 1.29 2010-05-12 21:33:04 sshwarts Exp $
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// $Id: crregs.h,v 1.30 2010-07-22 15:12:08 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2007-2009 Stanislav Shwartsman
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@ -89,6 +89,7 @@ struct bx_cr0_t {
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#define BX_CR4_OSXMMEXCPT_MASK (1 << 10)
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#define BX_CR4_VMXE_MASK (1 << 13)
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#define BX_CR4_SMXE_MASK (1 << 14)
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#define BX_CR4_FSGSBASE_MASK (1 << 16)
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#define BX_CR4_PCIDE_MASK (1 << 17)
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#define BX_CR4_OSXSAVE_MASK (1 << 18)
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@ -110,6 +111,7 @@ struct bx_cr4_t {
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IMPLEMENT_CRREG_ACCESSORS(VMXE, 13);
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#endif
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#if BX_SUPPORT_X86_64
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IMPLEMENT_CRREG_ACCESSORS(FSGSBASE, 16);
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IMPLEMENT_CRREG_ACCESSORS(PCIDE, 17);
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#endif
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IMPLEMENT_CRREG_ACCESSORS(OSXSAVE, 18);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: dis_groups.cc,v 1.52 2010-04-02 19:01:16 sshwarts Exp $
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// $Id: dis_groups.cc,v 1.53 2010-07-22 15:12:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2005-2009 Stanislav Shwartsman
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@ -353,6 +353,12 @@ void disassembler::Rq(const x86_insn *insn)
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dis_sprintf("%s", general_64bit_regname[insn->rm]);
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}
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void disassembler::Ry(const x86_insn *insn)
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{
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if (insn->os_64) Rq(insn);
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else Rd(insn);
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}
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// mmx register
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void disassembler::Pq(const x86_insn *insn)
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{
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: dis_tables.h,v 1.45 2010-04-02 19:01:16 sshwarts Exp $
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// $Id: dis_tables.h,v 1.46 2010-07-22 15:12:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2005-2010 Stanislav Shwartsman
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@ -119,6 +119,7 @@
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#define Rw &disassembler::Rw
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#define Rd &disassembler::Rd
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#define Rq &disassembler::Rq
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#define Ry &disassembler::Ry
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#define Pq &disassembler::Pq
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#define Qd &disassembler::Qd
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: dis_tables.inc,v 1.35 2010-05-23 20:05:14 sshwarts Exp $
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// $Id: dis_tables.inc,v 1.36 2010-07-22 15:12:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2005-2010 Stanislav Shwartsman
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@ -495,7 +495,7 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_G9VMX7[4] = {
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static BxDisasmOpcodeTable_t BxDisasmGroupG9[8] = {
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/* 0 */ { 0, &Ia_Invalid },
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/* 1 */ { 0, &Ia_cmpxchg8b },
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/* 1 */ { 0, &Ia_cmpxchg8b_Mq },
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/* 2 */ { 0, &Ia_Invalid },
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/* 3 */ { 0, &Ia_Invalid },
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/* 4 */ { 0, &Ia_Invalid },
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@ -506,7 +506,7 @@ static BxDisasmOpcodeTable_t BxDisasmGroupG9[8] = {
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static BxDisasmOpcodeTable_t BxDisasmGroupG9q[8] = {
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/* 0 */ { 0, &Ia_Invalid },
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/* 1 */ { 0, &Ia_cmpxchg16b },
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/* 1 */ { 0, &Ia_cmpxchg16b_Mdq },
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/* 2 */ { 0, &Ia_Invalid },
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/* 3 */ { 0, &Ia_Invalid },
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/* 4 */ { 0, &Ia_Invalid },
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@ -598,21 +598,21 @@ static BxDisasmOpcodeTable_t BxDisasmGroupG14[8] = {
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/* Group15 */
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static BxDisasmOpcodeTable_t BxDisasmGroupG15M[8] = {
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/* 0 */ { 0, &Ia_fxsave },
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/* 1 */ { 0, &Ia_fxrstor },
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/* 2 */ { 0, &Ia_ldmxcsr },
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/* 3 */ { 0, &Ia_stmxcsr },
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/* 4 */ { 0, &Ia_xsave },
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/* 5 */ { 0, &Ia_xrstor },
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/* 6 */ { 0, &Ia_Invalid },
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/* 7 */ { 0, &Ia_cflush }
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/* 0 */ { 0, &Ia_fxsave },
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/* 1 */ { 0, &Ia_fxrstor },
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/* 2 */ { 0, &Ia_ldmxcsr },
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/* 3 */ { 0, &Ia_stmxcsr },
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/* 4 */ { 0, &Ia_xsave },
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/* 5 */ { 0, &Ia_xrstor },
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/* 6 */ { 0, &Ia_xsaveopt },
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/* 7 */ { 0, &Ia_cflush }
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};
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static BxDisasmOpcodeTable_t BxDisasmGroupG15R[8] = {
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/* 0 */ { 0, &Ia_Invalid },
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/* 1 */ { 0, &Ia_Invalid },
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/* 2 */ { 0, &Ia_Invalid },
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/* 3 */ { 0, &Ia_Invalid },
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/* 0 */ { GRPSSEF3(Ia_rdfsbase_Ry) },
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/* 1 */ { GRPSSEF3(Ia_rdgsbase_Ry) },
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/* 2 */ { GRPSSEF3(Ia_wrfsbase_Ry) },
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/* 3 */ { GRPSSEF3(Ia_wrgsbase_Ry) },
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/* 4 */ { 0, &Ia_Invalid },
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/* 5 */ { 0, &Ia_lfence },
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/* 6 */ { 0, &Ia_mfence },
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: disasm.h,v 1.62 2010-04-08 15:50:39 sshwarts Exp $
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// $Id: disasm.h,v 1.63 2010-07-22 15:12:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2005-2009 Stanislav Shwartsman
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@ -60,11 +60,13 @@
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#define IA_SMX 0x00040000 /* SMX instruction */
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#define IA_SVM 0x00080000 /* SVM instruction */
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#define IA_XSAVE 0x00100000 /* XSAVE/XRSTOR extensions instruction */
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#define IA_AES_PCLMULQDQ 0x00200000 /* AES+PCLMULQDQ instructions */
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#define IA_MOVBE 0x00400000 /* MOVBE Intel Atom(R) instruction */
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#define IA_AVX 0x00800000 /* AVX instruction */
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#define IA_AVX_FMA 0x01000000 /* AVX FMA instruction */
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#define IA_X86_64 0x02000000 /* x86-64 instruction */
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#define IA_XSAVEOPT 0x00200000 /* XSAVEOPT instruction */
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#define IA_AES_PCLMULQDQ 0x00400000 /* AES+PCLMULQDQ instructions */
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#define IA_MOVBE 0x00800000 /* MOVBE Intel Atom(R) instruction */
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#define IA_FSGSBASE 0x01000000 /* FS/GS BASE access instructions */
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#define IA_AVX 0x02000000 /* AVX instruction */
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#define IA_AVX_FMA 0x04000000 /* AVX FMA instruction */
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#define IA_X86_64 0x08000000 /* x86-64 instruction */
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/* general purpose bit register */
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enum {
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@ -480,6 +482,7 @@ public:
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void Rw(const x86_insn *insn);
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void Rd(const x86_insn *insn);
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void Rq(const x86_insn *insn);
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void Ry(const x86_insn *insn);
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// mmx register
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void Pq(const x86_insn *insn);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: opcodes.inc,v 1.39 2010-05-23 20:05:14 sshwarts Exp $
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// $Id: opcodes.inc,v 1.40 2010-07-22 15:12:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2005-2009 Stanislav Shwartsman
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@ -226,8 +226,8 @@ Ia_cmpw_Ew_Gw = { "cmp", "cmpw", Ew, Gw, XX, XX, 0 },
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Ia_cmpw_Ew_Iw = { "cmp", "cmpw", Ew, Iw, XX, XX, 0 },
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Ia_cmpw_Ew_sIb = { "cmp", "cmpw", Ew, sIbw, XX, XX, 0 },
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Ia_cmpw_Gw_Ew = { "cmp", "cmpw", Gw, Ew, XX, XX, 0 },
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Ia_cmpxchg16b = { "cmpxchg16b", "cmpxchg16b", Mdq, XX, XX, XX, IA_X86_64 },
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Ia_cmpxchg8b = { "cmpxchg8b", "cmpxchg8b", Mq, XX, XX, XX, IA_PENTIUM },
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Ia_cmpxchg16b_Mdq = { "cmpxchg16b", "cmpxchg16b", Mdq, XX, XX, XX, IA_X86_64 },
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Ia_cmpxchg8b_Mq = { "cmpxchg8b", "cmpxchg8b", Mq, XX, XX, XX, IA_PENTIUM },
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Ia_cmpxchgb_Eb_Gb = { "cmpxchg", "cmpxchgb", Eb, Gb, XX, XX, IA_486 },
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||||
Ia_cmpxchgl_Ed_Gd = { "cmpxchg", "cmpxchgl", Ed, Gd, XX, XX, IA_486 },
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||||
Ia_cmpxchgq_Eq_Gq = { "cmpxchg", "cmpxchgq", Eq, Gq, XX, XX, IA_X86_64 },
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||||
@ -1098,6 +1098,8 @@ Ia_rcrq_Eq_Ib = { "rcr", "rcrq", Eq, Ib, XX, XX, IA_X86_64 },
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||||
Ia_rcrw_Ew_CL = { "rcr", "rcrw", Ew, CL_Reg, XX, XX, 0 },
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Ia_rcrw_Ew_I1 = { "rcr", "rcrw", Ew, I1, XX, XX, 0 },
|
||||
Ia_rcrw_Ew_Ib = { "rcr", "rcrw", Ew, Ib, XX, XX, 0 },
|
||||
Ia_rdfsbase_Ry = { "rdfsbase", "rdfsbase", Ry, XX, XX, XX, IA_FSGSBASE },
|
||||
Ia_rdgsbase_Ry = { "rdgsbase", "rdgsbase", Ry, XX, XX, XX, IA_FSGSBASE },
|
||||
Ia_rdmsr = { "rdmsr", "rdmsr", XX, XX, XX, XX, IA_PENTIUM },
|
||||
Ia_rdpmc = { "rdpmc", "rdpmc", XX, XX, XX, XX, IA_P6 },
|
||||
Ia_rdtsc = { "rdtsc", "rdtsc", XX, XX, XX, XX, IA_PENTIUM },
|
||||
@ -1307,6 +1309,8 @@ Ia_vmwrite_Gq_Eq = { "vmwrite", "vmwrite", Gq, Eq, XX, XX, IA_VMX },
|
||||
Ia_vmxoff = { "vmxoff", "vmxoff", XX, XX, XX, XX, IA_VMX },
|
||||
Ia_vmxon_Mq = { "vmxon", "vmxon", Mq, XX, XX, XX, IA_VMX },
|
||||
Ia_wbinvd = { "wbinvd", "wbinvd", XX, XX, XX, XX, IA_486 },
|
||||
Ia_wrfsbase_Ry = { "wrfsbase", "wrfsbase", Ry, XX, XX, XX, IA_FSGSBASE },
|
||||
Ia_wrgsbase_Ry = { "wrgsbase", "wrgsbase", Ry, XX, XX, XX, IA_FSGSBASE },
|
||||
Ia_wrmsr = { "wrmsr", "wrmsr", XX, XX, XX, XX, IA_PENTIUM },
|
||||
Ia_xaddb_Eb_Gb = { "xadd", "xaddb", Eb, Gb, XX, XX, IA_486 },
|
||||
Ia_xaddl_Ed_Gd = { "xadd", "xaddl", Ed, Gd, XX, XX, IA_486 },
|
||||
@ -1344,4 +1348,5 @@ Ia_xorw_Ew_sIb = { "xor", "xorw", Ew, sIbw, XX, XX, 0 },
|
||||
Ia_xorw_Gw_Ew = { "xor", "xorw", Gw, Ew, XX, XX, 0 },
|
||||
Ia_xrstor = { "xrstor", "xrstor", Mx, XX, XX, XX, IA_XSAVE },
|
||||
Ia_xsave = { "xsave", "xsave", Mx, XX, XX, XX, IA_XSAVE },
|
||||
Ia_xsaveopt = { "xsaveopt", "xsaveopt", Mx, XX, XX, XX, IA_XSAVEOPT },
|
||||
Ia_xsetbv = { "xsetbv", "xsetbv", XX, XX, XX, XX, IA_XSAVE };
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user