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1st step of moving CPU options to runtime

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This commit is contained in:
Stanislav Shwartsman 2010-02-24 19:27:51 +00:00
parent 5a81abb795
commit 70dc124b3a
13 changed files with 1706 additions and 1660 deletions
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34
bochs/cpu/cpu.h
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.638 2010-02-10 17:21:14 sshwarts Exp $
// $Id: cpu.h,v 1.639 2010-02-24 19:27:50 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2009 The Bochs Project
@ -596,6 +596,34 @@ typedef struct
#define MAX_STD_CPUID_FUNCTION 14
#define MAX_EXT_CPUID_FUNCTION 9
// cpuid features (duplicated in disasm.h)
#define BX_CPU_X87 0x00000001 /* FPU (X87) instruction */
#define BX_CPU_486 0x00000002 /* 486 new instruction */
#define BX_CPU_PENTIUM 0x00000004 /* Pentium new instruction */
#define BX_CPU_P6 0x00000008 /* P6 new instruction */
#define BX_CPU_MMX 0x00000010 /* MMX instruction */
#define BX_CPU_3DNOW 0x00000020 /* 3DNow! instruction */
#define BX_CPU_MONITOR_MWAIT 0x00000040 /* MONITOR/MWAIT instruction */
#define BX_CPU_CLFLUSH 0x00000080 /* CLFLUSH instruction */
#define BX_CPU_SSE 0x00000100 /* SSE instruction */
#define BX_CPU_SSE2 0x00000200 /* SSE2 instruction */
#define BX_CPU_SSE3 0x00000400 /* SSE3 instruction */
#define BX_CPU_SSSE3 0x00000800 /* SSSE3 instruction */
#define BX_CPU_SSE4_1 0x00001000 /* SSE4_1 instruction */
#define BX_CPU_SSE4_2 0x00002000 /* SSE4_2 instruction */
#define BX_CPU_SSE4A 0x00004000 /* SSE4A instruction */
#define BX_CPU_SYSENTER_SYSEXIT 0x00008000 /* SYSENTER/SYSEXIT instruction */
#define BX_CPU_VMX 0x00010000 /* VMX instruction */
#define BX_CPU_SMX 0x00020000 /* SMX instruction */
#define BX_CPU_SVM 0x00040000 /* SVM instruction */
#define BX_CPU_XSAVE 0x00080000 /* XSAVE/XRSTOR extensions instruction */
#define BX_CPU_AES 0x00100000 /* AES instruction */
#define BX_CPU_PCLMULQDQ 0x00200000 /* PCLMULQDQ instruction */
#define BX_CPU_MOVBE 0x00400000 /* MOVBE Intel Atom(R) instruction */
#define BX_CPU_AVX 0x00800000 /* AVX instruction */
#define BX_CPU_AVX_FMA 0x01000000 /* AVX FMA instruction */
#define BX_CPU_X86_64 0x02000000 /* x86-64 instruction */
struct cpuid_function_t {
Bit32u eax;
Bit32u ebx;
@ -2142,7 +2170,7 @@ public: // for now...
// 3-byte opcodes
#if (BX_SUPPORT_SSE >= 4) || (BX_SUPPORT_SSE >= 3 && BX_SUPPORT_SSE_EXTENSION > 0)
/* SSE3E */
/* SSSE3 */
BX_SMF void PSHUFB_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void PHADDW_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void PHADDD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -2176,7 +2204,7 @@ public: // for now...
BX_SMF void PABSW_VdqWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void PABSD_VdqWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void PALIGNR_VdqWdqIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
/* SSE3E */
/* SSSE3 */
/* SSE4.1 */
BX_SMF void PBLENDVB_VdqWdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);

10
bochs/cpu/crc32.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: crc32.cc,v 1.3 2009-10-14 20:45:29 sshwarts Exp $
// $Id: crc32.cc,v 1.4 2010-02-24 19:27:50 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2009 Stanislav Shwartsman
@ -98,7 +98,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEb(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), BitReflect32(op2));
#else
BX_INFO(("CRC32_GdEb: required SSE4_2 support, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("CRC32_GdEb: required SSE4_2 support, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -127,7 +127,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEw(bxInstruction_c *i)
BX_WRITE_32BIT_REGZ(i->nnn(), BitReflect32(op2));
#else
BX_INFO(("CRC32_GdEw: required SSE4_2 support, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("CRC32_GdEw: required SSE4_2 support, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -156,7 +156,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEd(bxInstruction_c *i)
BX_WRITE_32BIT_REGZ(i->nnn(), BitReflect32(op2));
#else
BX_INFO(("CRC32_GdEd: required SSE4_2 support, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("CRC32_GdEd: required SSE4_2 support, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -191,7 +191,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CRC32_GdEq(bxInstruction_c *i)
BX_WRITE_32BIT_REGZ(i->nnn(), BitReflect32(op2));
#else
BX_INFO(("CRC32_GdEq: required SSE4_2 support, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("CRC32_GdEq: required SSE4_2 support, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

14
bochs/cpu/fetchdecode.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode.cc,v 1.251 2010-02-10 17:21:14 sshwarts Exp $
// $Id: fetchdecode.cc,v 1.252 2010-02-24 19:27:50 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2009 The Bochs Project
@ -168,7 +168,7 @@ static unsigned sreg_mod1or2_base32[8] = {
// table of all Bochs opcodes
bxIAOpcodeTable BxOpcodesTable[] = {
#define bx_define_opcode(a, b, c) { b, c },
#define bx_define_opcode(a, b, c, d) { b, c },
#include "ia_opcodes.h"
};
#undef bx_define_opcode
@ -472,7 +472,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F 0B /wr */ { BxTraceEnd, BX_IA_UD2A },
/* 0F 0C /wr */ { 0, BX_IA_ERROR },
#if BX_SUPPORT_X86_64 || BX_SUPPORT_3DNOW
/* 0F 0D /wr */ { 0, BX_IA_NOP }, // 3DNow! PREFETCH on AMD, NOP on Intel
/* 0F 0D /wr */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel
#else
/* 0F 0D /wr */ { 0, BX_IA_ERROR },
#endif
@ -1035,7 +1035,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32R[512*2] = {
/* 0F 0B /dr */ { BxTraceEnd, BX_IA_UD2A },
/* 0F 0C /dr */ { 0, BX_IA_ERROR },
#if BX_SUPPORT_X86_64 || BX_SUPPORT_3DNOW
/* 0F 0D /dr */ { 0, BX_IA_NOP }, // 3DNow! PREFETCH on AMD, NOP on Intel
/* 0F 0D /dr */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel
#else
/* 0F 0D /dr */ { 0, BX_IA_ERROR },
#endif
@ -1605,7 +1605,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F 0B /wm */ { BxTraceEnd, BX_IA_UD2A },
/* 0F 0C /wm */ { 0, BX_IA_ERROR },
#if BX_SUPPORT_X86_64 || BX_SUPPORT_3DNOW
/* 0F 0D /wm */ { 0, BX_IA_NOP }, // 3DNow! PREFETCH on AMD, NOP on Intel
/* 0F 0D /wm */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel
#else
/* 0F 0D /wm */ { 0, BX_IA_ERROR },
#endif
@ -2168,7 +2168,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo32M[512*2] = {
/* 0F 0B /dm */ { BxTraceEnd, BX_IA_UD2A },
/* 0F 0C /dm */ { 0, BX_IA_ERROR },
#if BX_SUPPORT_X86_64 || BX_SUPPORT_3DNOW
/* 0F 0D /dm */ { 0, BX_IA_NOP }, // 3DNow! PREFETCH on AMD, NOP on Intel
/* 0F 0D /dm */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel
#else
/* 0F 0D /dm */ { 0, BX_IA_ERROR },
#endif
@ -2961,7 +2961,7 @@ const char *get_bx_opcode_name(Bit16u ia_opcode)
{
static const char* BxOpcodeNamesTable[BX_IA_LAST] =
{
#define bx_define_opcode(a, b, c) #a,
#define bx_define_opcode(a, b, c, d) #a,
#include "ia_opcodes.h"
};
#undef bx_define_opcode

14
bochs/cpu/fetchdecode64.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode64.cc,v 1.253 2010-02-10 17:21:14 sshwarts Exp $
// $Id: fetchdecode64.cc,v 1.254 2010-02-24 19:27:51 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2009 The Bochs Project
@ -426,7 +426,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 0F 0A /wr */ { 0, BX_IA_ERROR },
/* 0F 0B /wr */ { BxTraceEnd, BX_IA_UD2A },
/* 0F 0C /wr */ { 0, BX_IA_ERROR },
/* 0F 0D /wr */ { 0, BX_IA_NOP }, // 3DNow! PREFETCH on AMD, NOP on Intel
/* 0F 0D /wr */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel
/* 0F 0E /wr */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS
#if BX_SUPPORT_3DNOW
/* 0F 0F /wr */ { BxImmediate_Ib, BX_IA_ERROR, Bx3DNowOpcodeInfo },
@ -953,7 +953,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 0F 0A /dr */ { 0, BX_IA_ERROR },
/* 0F 0B /dr */ { BxTraceEnd, BX_IA_UD2A },
/* 0F 0C /dr */ { 0, BX_IA_ERROR },
/* 0F 0D /dr */ { 0, BX_IA_NOP }, // 3DNow! PREFETCH on AMD, NOP on Intel
/* 0F 0D /dr */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel
/* 0F 0E /dr */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS
#if BX_SUPPORT_3DNOW
/* 0F 0F /dr */ { BxImmediate_Ib, BX_IA_ERROR, Bx3DNowOpcodeInfo },
@ -1480,7 +1480,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64R[512*3] = {
/* 0F 0A /qr */ { 0, BX_IA_ERROR },
/* 0F 0B /qr */ { BxTraceEnd, BX_IA_UD2A },
/* 0F 0C /qr */ { 0, BX_IA_ERROR },
/* 0F 0D /qr */ { 0, BX_IA_NOP }, // 3DNow! PREFETCH on AMD, NOP on Intel
/* 0F 0D /qr */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel
/* 0F 0E /qr */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS
#if BX_SUPPORT_3DNOW
/* 0F 0F /qr */ { BxImmediate_Ib, BX_IA_ERROR, Bx3DNowOpcodeInfo },
@ -2013,7 +2013,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 0F 0A /wm */ { 0, BX_IA_ERROR },
/* 0F 0B /wm */ { BxTraceEnd, BX_IA_UD2A },
/* 0F 0C /wm */ { 0, BX_IA_ERROR },
/* 0F 0D /wm */ { 0, BX_IA_NOP }, // 3DNow! PREFETCH on AMD, NOP on Intel
/* 0F 0D /wm */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel
/* 0F 0E /wm */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS
#if BX_SUPPORT_3DNOW
/* 0F 0F /wm */ { BxImmediate_Ib, BX_IA_ERROR, Bx3DNowOpcodeInfo },
@ -2540,7 +2540,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 0F 0A /dm */ { 0, BX_IA_ERROR },
/* 0F 0B /dm */ { BxTraceEnd, BX_IA_UD2A },
/* 0F 0C /dm */ { 0, BX_IA_ERROR },
/* 0F 0D /dm */ { 0, BX_IA_NOP }, // 3DNow! PREFETCH on AMD, NOP on Intel
/* 0F 0D /dm */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel
/* 0F 0E /dm */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS
#if BX_SUPPORT_3DNOW
/* 0F 0F /dm */ { BxImmediate_Ib, BX_IA_ERROR, Bx3DNowOpcodeInfo },
@ -3067,7 +3067,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64M[512*3] = {
/* 0F 0A /qm */ { 0, BX_IA_ERROR },
/* 0F 0B /qm */ { BxTraceEnd, BX_IA_UD2A },
/* 0F 0C /qm */ { 0, BX_IA_ERROR },
/* 0F 0D /qm */ { 0, BX_IA_NOP }, // 3DNow! PREFETCH on AMD, NOP on Intel
/* 0F 0D /qm */ { 0, BX_IA_PREFETCHW }, // 3DNow! PREFETCH on AMD, NOP on Intel
/* 0F 0E /qm */ { 0, BX_IA_FEMMS }, // 3DNow! FEMMS
#if BX_SUPPORT_3DNOW
/* 0F 0F /qm */ { BxImmediate_Ib, BX_IA_ERROR, Bx3DNowOpcodeInfo },

3078
bochs/cpu/ia_opcodes.h
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File diff suppressed because it is too large Load Diff

4
bochs/cpu/instr.h
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: instr.h,v 1.25 2010-01-09 15:11:32 sshwarts Exp $
// $Id: instr.h,v 1.26 2010-02-24 19:27:51 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2009 Stanislav Shwartsman
@ -278,7 +278,7 @@ public:
const char *get_bx_opcode_name(Bit16u ia_opcode);
enum {
#define bx_define_opcode(a, b, c) a,
#define bx_define_opcode(a, b, c, d) a,
#include "ia_opcodes.h"
BX_IA_LAST
};

34
bochs/cpu/mmx.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: mmx.cc,v 1.90 2010-02-10 17:21:15 sshwarts Exp $
// $Id: mmx.cc,v 1.91 2010-02-24 19:27:51 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002-2009 Stanislav Shwartsman
@ -77,7 +77,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PSHUFB_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PSHUFB_PqQq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -109,7 +109,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PHADDW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PHADDW_PqQq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -139,7 +139,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDD_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PHADDD_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PHADDD_PqQq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -172,7 +172,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDSW_PqQq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PHADDSW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PHADDSW_PqQq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -208,7 +208,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMADDUBSW_PqQq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PMADDUBSW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PMADDUBSW_PqQq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -241,7 +241,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBSW_PqQq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PHSUBSW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PHSUBSW_PqQq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -273,7 +273,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PHSUBW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PHSUBW_PqQq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -303,7 +303,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBD_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PHSUBD_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PHSUBD_PqQq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -335,7 +335,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGNB_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSIGNB_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PSIGNB_PqQq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -367,7 +367,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGNW_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSIGNW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PSIGNW_PqQq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -401,7 +401,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGND_PqQq(bxInstruction_c *i)
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSIGND_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PSIGND_PqQq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -439,7 +439,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHRSW_PqQq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PMULHRSW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PMULHRSW_PqQq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -475,7 +475,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSB_PqQq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), op);
#else
BX_INFO(("PABSB_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PABSB_PqQq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -507,7 +507,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSW_PqQq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), op);
#else
BX_INFO(("PABSW_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PABSW_PqQq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -537,7 +537,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSD_PqQq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), op);
#else
BX_INFO(("PABSD_PqQq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PABSD_PqQq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -576,7 +576,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PALIGNR_PqQqIb(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), result);
#else
BX_INFO(("PALIGNR_PqQqIb: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PALIGNR_PqQqIb: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

7
bochs/cpu/mult64.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: mult64.cc,v 1.37 2009-12-04 16:53:12 sshwarts Exp $
// $Id: mult64.cc,v 1.38 2010-02-24 19:27:51 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2009 The Bochs Project
@ -86,8 +86,7 @@ void long_imul(Bit128s *product, Bit64s op1, Bit64s op2)
void long_shl(Bit128u *a)
{
Bit64u c;
c = a->lo >> 63;
Bit64u c = a->lo >> 63;
a->lo <<= 1;
a->hi <<= 1;
a->hi |= c;
@ -121,7 +120,7 @@ int long_le(Bit128u *a,Bit128u *b)
}
}
void long_div(Bit128u *quotient,Bit64u *remainder,Bit128u *dividend,Bit64u divisor)
void long_div(Bit128u *quotient,Bit64u *remainder,const Bit128u *dividend,Bit64u divisor)
{
/*
n := 0;

34
bochs/cpu/sse.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: sse.cc,v 1.66 2009-10-14 20:45:29 sshwarts Exp $
// $Id: sse.cc,v 1.67 2010-02-24 19:27:51 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003-2009 Stanislav Shwartsman
@ -62,7 +62,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PSHUFB_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PSHUFB_VdqWdq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -97,7 +97,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PHADDW_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PHADDW_VdqWdq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -127,7 +127,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PHADDD_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PHADDD_VdqWdq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -163,7 +163,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDSW_VdqWdq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PHADDSW_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PHADDSW_VdqWdq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -197,7 +197,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMADDUBSW_VdqWdq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PMADDUBSW_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PMADDUBSW_VdqWdq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -233,7 +233,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBSW_VdqWdq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PHSUBSW_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PHSUBSW_VdqWdq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -268,7 +268,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PHSUBW_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PHSUBW_VdqWdq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -298,7 +298,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBD_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PHSUBD_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PHSUBD_VdqWdq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -328,7 +328,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGNB_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSIGNB_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PSIGNB_VdqWdq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -358,7 +358,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGNW_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSIGNW_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PSIGNW_VdqWdq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -388,7 +388,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGND_VdqWdq(bxInstruction_c *i)
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSIGND_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PSIGND_VdqWdq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -423,7 +423,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHRSW_VdqWdq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PMULHRSW_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PMULHRSW_VdqWdq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -465,7 +465,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSB_VdqWdq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("PABSB_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PABSB_VdqWdq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -499,7 +499,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSW_VdqWdq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("PABSW_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PABSW_VdqWdq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -529,7 +529,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSD_VdqWdq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), op);
#else
BX_INFO(("PABSD_VdqWdq: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PABSD_VdqWdq: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -781,7 +781,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPGTQ_VdqWdq(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PCMPGTQ_VdqWdq: required SSE4.2, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PCMPGTQ_VdqWdq: required SSE4.2, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

4
bochs/cpu/sse_move.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: sse_move.cc,v 1.106 2009-11-29 21:01:26 sshwarts Exp $
// $Id: sse_move.cc,v 1.107 2010-02-24 19:27:51 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003-2009 Stanislav Shwartsman
@ -1550,7 +1550,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PALIGNR_VdqWdqIb(bxInstruction_c *i)
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PALIGNR_VdqWdqIb: required SSE3E, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PALIGNR_VdqWdqIb: required SSSE3, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

10
bochs/cpu/sse_string.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: sse_string.cc,v 1.13 2009-10-14 20:45:29 sshwarts Exp $
// $Id: sse_string.cc,v 1.14 2010-02-24 19:27:51 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2007-2009 Stanislav Shwartsman
@ -356,7 +356,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRM_VdqWdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(0, result); /* store result XMM0 */
#else
BX_INFO(("PCMPESTRM_VdqWdqIb: required SSE4.2, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PCMPESTRM_VdqWdqIb: required SSE4.2, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -423,7 +423,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRI_VdqWdqIb(bxInstruction_c *i)
setEFlagsOSZAPC(flags);
#else
BX_INFO(("PCMPESTRI_VdqWdqIb: required SSE4.2, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PCMPESTRI_VdqWdqIb: required SSE4.2, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -484,7 +484,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRM_VdqWdqIb(bxInstruction_c *i)
BX_WRITE_XMM_REG(0, result); /* store result XMM0 */
#else
BX_INFO(("PCMPISTRM_VdqWdqIb: required SSE4.2, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PCMPISTRM_VdqWdqIb: required SSE4.2, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}
@ -542,7 +542,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRI_VdqWdqIb(bxInstruction_c *i)
setEFlagsOSZAPC(flags);
#else
BX_INFO(("PCMPISTRI_VdqWdqIb: required SSE4.2, use --enable-sse and --enable-sse-extension options"));
BX_INFO(("PCMPISTRI_VdqWdqIb: required SSE4.2, use --enable-sse option"));
exception(BX_UD_EXCEPTION, 0, 0);
#endif
}

53
bochs/disasm/disasm.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: disasm.h,v 1.55 2010-02-01 07:59:21 sshwarts Exp $
// $Id: disasm.h,v 1.56 2010-02-24 19:27:50 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2009 Stanislav Shwartsman
@ -38,34 +38,33 @@
base = sib_byte & 0x07; \
}
/* Instruction set attributes */
#define IA_486 0x00000001 /* 486 new instruction */
#define IA_PENTIUM 0x00000002 /* Pentium new instruction */
#define IA_P6 0x00000004 /* P6 new instruction */
#define IA_X87 0x00000008 /* FPU (X87) instruction */
/* Instruction set attributes (duplicated in cpu.h) */
#define IA_X87 0x00000001 /* FPU (X87) instruction */
#define IA_486 0x00000002 /* 486 new instruction */
#define IA_PENTIUM 0x00000004 /* Pentium new instruction */
#define IA_P6 0x00000008 /* P6 new instruction */
#define IA_MMX 0x00000010 /* MMX instruction */
#define IA_3DNOW 0x00000020 /* 3DNow! instruction */
#define IA_3DNOW_EXT 0x00000040 /* 3DNow! extensions */
#define IA_MONITOR_MWAIT 0x00000080 /* MONITOR/MWAIT instruction */
#define IA_CLFLUSH 0x00000100 /* CLFLUSH instruction */
#define IA_SSE 0x00000200 /* SSE instruction */
#define IA_SSE2 0x00000400 /* SSE2 instruction */
#define IA_SSE3 0x00000800 /* SSE3 instruction */
#define IA_SSE3E 0x00001000 /* SSE3E instruction */
#define IA_SSE4_1 0x00002000 /* SSE4_1 instruction */
#define IA_SSE4_2 0x00004000 /* SSE4_2 instruction */
#define IA_SSE4A 0x00008000 /* SSE4A instruction */
#define IA_X86_64 0x00010000 /* x86-64 instruction */
#define IA_SYSCALL_SYSRET 0x00020000 /* SYSCALL/SYSRET instruction */
#define IA_SYSENTER_SYSEXIT 0x00040000 /* SYSENTER/SYSEXIT instruction */
#define IA_VMX 0x00080000 /* VMX instruction */
#define IA_SMX 0x00100000 /* SMX instruction */
#define IA_SVM 0x00200000 /* SVM instruction */
#define IA_XSAVE 0x00400000 /* XSAVE/XRSTOR extensions instruction */
#define IA_AES 0x00800000 /* AES instruction */
#define IA_PCLMULQDQ 0x01000000 /* PCLMULQDQ instruction */
#define IA_MOVBE 0x02000000 /* MOVBE Intel Atom(R) instruction */
#define IA_AVX 0x04000000 /* AVX instruction */
#define IA_MONITOR_MWAIT 0x00000040 /* MONITOR/MWAIT instruction */
#define IA_CLFLUSH 0x00000080 /* CLFLUSH instruction */
#define IA_SSE 0x00000100 /* SSE instruction */
#define IA_SSE2 0x00000200 /* SSE2 instruction */
#define IA_SSE3 0x00000400 /* SSE3 instruction */
#define IA_SSSE3 0x00000800 /* SSSE3 instruction */
#define IA_SSE4_1 0x00001000 /* SSE4_1 instruction */
#define IA_SSE4_2 0x00002000 /* SSE4_2 instruction */
#define IA_SSE4A 0x00004000 /* SSE4A instruction */
#define IA_SYSENTER_SYSEXIT 0x00008000 /* SYSENTER/SYSEXIT instruction */
#define IA_VMX 0x00010000 /* VMX instruction */
#define IA_SMX 0x00020000 /* SMX instruction */
#define IA_SVM 0x00040000 /* SVM instruction */
#define IA_XSAVE 0x00080000 /* XSAVE/XRSTOR extensions instruction */
#define IA_AES 0x00100000 /* AES instruction */
#define IA_PCLMULQDQ 0x00200000 /* PCLMULQDQ instruction */
#define IA_MOVBE 0x00400000 /* MOVBE Intel Atom(R) instruction */
#define IA_AVX 0x00800000 /* AVX instruction */
#define IA_AVX_FMA 0x01000000 /* AVX FMA instruction */
#define IA_X86_64 0x02000000 /* x86-64 instruction */
/* general purpose bit register */
enum {

70
bochs/disasm/opcodes.inc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: opcodes.inc,v 1.32 2010-02-09 20:28:12 sshwarts Exp $
// $Id: opcodes.inc,v 1.33 2010-02-24 19:27:50 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2009 Stanislav Shwartsman
@ -764,12 +764,12 @@ Ia_outsl_DX_Xd = { "outsd", "outsl", DX_Reg, Xd, XX, XX, 0 },
Ia_outsw_DX_Xw = { "outsw", "outsw", DX_Reg, Xw, XX, XX, 0 },
Ia_outw_DX_AX = { "out", "outw", DX_Reg, AX_Reg, XX, XX, 0 },
Ia_outw_Ib_AX = { "out", "outw", Ib, AX_Reg, XX, XX, 0 },
Ia_pabsb_Pq_Qq = { "pabsb", "pabsb", Pq, Qq, XX, XX, IA_SSE3E },
Ia_pabsb_Vdq_Wdq = { "pabsb", "pabsb", Vdq, Wdq, XX, XX, IA_SSE3E },
Ia_pabsd_Pq_Qq = { "pabsd", "pabsd", Pq, Qq, XX, XX, IA_SSE3E },
Ia_pabsd_Vdq_Wdq = { "pabsd", "pabsd", Vdq, Wdq, XX, XX, IA_SSE3E },
Ia_pabsw_Pq_Qq = { "pabsw", "pabsw", Pq, Qq, XX, XX, IA_SSE3E },
Ia_pabsw_Vdq_Wdq = { "pabsw", "pabsw", Vdq, Wdq, XX, XX, IA_SSE3E },
Ia_pabsb_Pq_Qq = { "pabsb", "pabsb", Pq, Qq, XX, XX, IA_SSSE3 },
Ia_pabsb_Vdq_Wdq = { "pabsb", "pabsb", Vdq, Wdq, XX, XX, IA_SSSE3 },
Ia_pabsd_Pq_Qq = { "pabsd", "pabsd", Pq, Qq, XX, XX, IA_SSSE3 },
Ia_pabsd_Vdq_Wdq = { "pabsd", "pabsd", Vdq, Wdq, XX, XX, IA_SSSE3 },
Ia_pabsw_Pq_Qq = { "pabsw", "pabsw", Pq, Qq, XX, XX, IA_SSSE3 },
Ia_pabsw_Vdq_Wdq = { "pabsw", "pabsw", Vdq, Wdq, XX, XX, IA_SSSE3 },
Ia_packssdw_Pq_Qq = { "packssdw", "packssdw", Pq, Qq, XX, XX, IA_MMX },
Ia_packssdw_Vdq_Wdq = { "packssdw", "packssdw", Vdq, Wdq, XX, XX, IA_SSE2 },
Ia_packsswb_Pq_Qq = { "packsswb", "packsswb", Pq, Qq, XX, XX, IA_MMX },
@ -793,8 +793,8 @@ Ia_paddusw_Pq_Qq = { "paddusw", "paddusw", Pq, Qq, XX, XX, IA_MMX },
Ia_paddusw_Vdq_Wdq = { "paddusw", "paddusw", Vdq, Wdq, XX, XX, IA_SSE2 },
Ia_paddw_Pq_Qq = { "paddw", "paddw", Pq, Qq, XX, XX, IA_MMX },
Ia_paddw_Vdq_Wdq = { "paddw", "paddw", Vdq, Wdq, XX, XX, IA_SSE2 },
Ia_palignr_Pq_Qq_Ib = { "palignr", "palignr", Pq, Qq, Ib, XX, IA_SSE3E },
Ia_palignr_Vdq_Wdq_Ib = { "palignr", "palignr", Vdq, Wdq, Ib, XX, IA_SSE3E },
Ia_palignr_Pq_Qq_Ib = { "palignr", "palignr", Pq, Qq, Ib, XX, IA_SSSE3 },
Ia_palignr_Vdq_Wdq_Ib = { "palignr", "palignr", Vdq, Wdq, Ib, XX, IA_SSSE3 },
Ia_pand_Pq_Qq = { "pand", "pand", Pq, Qq, XX, XX, IA_MMX },
Ia_pand_Vdq_Wdq = { "pand", "pand", Vdq, Wdq, XX, XX, IA_SSE2 },
Ia_pandn_Pq_Qq = { "pandn", "pandn", Pq, Qq, XX, XX, IA_MMX },
@ -850,19 +850,19 @@ Ia_pfrsqit1_Pq_Qq = { "pfrsqit1", "pfrsqit1", Pq, Qq, XX, XX, IA_3DNOW },
Ia_pfrsqrt_Pq_Qq = { "pfrsqrt", "pfrsqrt", Pq, Qq, XX, XX, IA_3DNOW },
Ia_pfsub_Pq_Qq = { "pfsub", "pfsub", Pq, Qq, XX, XX, IA_3DNOW },
Ia_pfsubr_Pq_Qq = { "pfsubr", "pfsubr", Pq, Qq, XX, XX, IA_3DNOW },
Ia_phaddd_Pq_Qq = { "phaddd", "phaddd", Pq, Qq, XX, XX, IA_SSE3E },
Ia_phaddd_Vdq_Wdq = { "phaddd", "phaddd", Vdq, Wdq, XX, XX, IA_SSE3E },
Ia_phaddsw_Pq_Qq = { "phaddsw", "phaddsw", Pq, Qq, XX, XX, IA_SSE3E },
Ia_phaddsw_Vdq_Wdq = { "phaddsw", "phaddsw", Vdq, Wdq, XX, XX, IA_SSE3E },
Ia_phaddw_Pq_Qq = { "phaddw", "phaddw", Pq, Qq, XX, XX, IA_SSE3E },
Ia_phaddw_Vdq_Wdq = { "phaddw", "phaddw", Vdq, Wdq, XX, XX, IA_SSE3E },
Ia_phaddd_Pq_Qq = { "phaddd", "phaddd", Pq, Qq, XX, XX, IA_SSSE3 },
Ia_phaddd_Vdq_Wdq = { "phaddd", "phaddd", Vdq, Wdq, XX, XX, IA_SSSE3 },
Ia_phaddsw_Pq_Qq = { "phaddsw", "phaddsw", Pq, Qq, XX, XX, IA_SSSE3 },
Ia_phaddsw_Vdq_Wdq = { "phaddsw", "phaddsw", Vdq, Wdq, XX, XX, IA_SSSE3 },
Ia_phaddw_Pq_Qq = { "phaddw", "phaddw", Pq, Qq, XX, XX, IA_SSSE3 },
Ia_phaddw_Vdq_Wdq = { "phaddw", "phaddw", Vdq, Wdq, XX, XX, IA_SSSE3 },
Ia_phminposuw_Vdq_Wdq = { "phminposuw", "phminposuw", Vdq, Wdq, XX, XX, IA_SSE4_1 },
Ia_phsubd_Pq_Qq = { "phsubd", "phsubd", Pq, Qq, XX, XX, IA_SSE3E },
Ia_phsubd_Vdq_Wdq = { "phsubd", "phsubd", Vdq, Wdq, XX, XX, IA_SSE3E },
Ia_phsubsw_Pq_Qq = { "phsubsw", "phsubsw", Pq, Qq, XX, XX, IA_SSE3E },
Ia_phsubsw_Vdq_Wdq = { "phsubsw", "phsubsw", Vdq, Wdq, XX, XX, IA_SSE3E },
Ia_phsubw_Pq_Qq = { "phsubw", "phsubw", Pq, Qq, XX, XX, IA_SSE3E },
Ia_phsubw_Vdq_Wdq = { "phsubw", "phsubw", Vdq, Wdq, XX, XX, IA_SSE3E },
Ia_phsubd_Pq_Qq = { "phsubd", "phsubd", Pq, Qq, XX, XX, IA_SSSE3 },
Ia_phsubd_Vdq_Wdq = { "phsubd", "phsubd", Vdq, Wdq, XX, XX, IA_SSSE3 },
Ia_phsubsw_Pq_Qq = { "phsubsw", "phsubsw", Pq, Qq, XX, XX, IA_SSSE3 },
Ia_phsubsw_Vdq_Wdq = { "phsubsw", "phsubsw", Vdq, Wdq, XX, XX, IA_SSSE3 },
Ia_phsubw_Pq_Qq = { "phsubw", "phsubw", Pq, Qq, XX, XX, IA_SSSE3 },
Ia_phsubw_Vdq_Wdq = { "phsubw", "phsubw", Vdq, Wdq, XX, XX, IA_SSSE3 },
Ia_pi2fd_Pq_Qq = { "pi2fd", "pi2fd", Pq, Qq, XX, XX, IA_3DNOW },
Ia_pi2fw_Pq_Qq = { "pi2fw", "pi2fw", Pq, Qq, XX, XX, IA_3DNOW },
Ia_pinsrb_Vdq_Ed_Ib = { "pinsrb", "pinsrb", Vdq, Ed, Ib, XX, IA_SSE4_1 },
@ -870,8 +870,8 @@ Ia_pinsrd_Vdq_Ed_Ib = { "pinsrd", "pinsrd", Vdq, Ed, Ib, XX, IA_SSE4_1 },
Ia_pinsrq_Vdq_Eq_Ib = { "pinsrq", "pinsrq", Vdq, Eq, Ib, XX, IA_SSE4_1 },
Ia_pinsrw_Pq_Ew_Ib = { "pinsrw", "pinsrw", Pq, Ew, Ib, XX, IA_3DNOW | IA_SSE },
Ia_pinsrw_Vdq_Ew_Ib = { "pinsrw", "pinsrw", Vdq, Ew, Ib, XX, IA_SSE2 },
Ia_pmaddubsw_Pq_Qq = { "pmaddubsw", "pmaddubsw", Pq, Qq, XX, XX, IA_SSE3E },
Ia_pmaddubsw_Vdq_Wdq = { "pmaddubsw", "pmaddubsw", Vdq, Wdq, XX, XX, IA_SSE3E },
Ia_pmaddubsw_Pq_Qq = { "pmaddubsw", "pmaddubsw", Pq, Qq, XX, XX, IA_SSSE3 },
Ia_pmaddubsw_Vdq_Wdq = { "pmaddubsw", "pmaddubsw", Vdq, Wdq, XX, XX, IA_SSSE3 },
Ia_pmaddwd_Pq_Qq = { "pmaddwd", "pmaddwd", Pq, Qq, XX, XX, IA_MMX },
Ia_pmaddwd_Vdq_Wdq = { "pmaddwd", "pmaddwd", Vdq, Wdq, XX, XX, IA_SSE2 },
Ia_pmaxsb_Vdq_Wdq = { "pmaxsb", "pmaxsb", Vdq, Wdq, XX, XX, IA_SSE4_1 },
@ -905,8 +905,8 @@ Ia_pmovzxdq_Vdq_Wq = { "pmovzxdq", "pmovzxdq", Vdq, Wq, XX, XX, IA_SSE4_1 },
Ia_pmovzxwd_Vdq_Wq = { "pmovzxwd", "pmovzxwd", Vdq, Wq, XX, XX, IA_SSE4_1 },
Ia_pmovzxwq_Vdq_Wd = { "pmovzxwq", "pmovzxwq", Vdq, Wd, XX, XX, IA_SSE4_1 },
Ia_pmuldq_Vdq_Wdq = { "pmuldq", "pmuldq", Vdq, Wdq, XX, XX, IA_SSE4_1 },
Ia_pmulhrsw_Pq_Qq = { "pmulhrsw", "pmulhrsw", Pq, Qq, XX, XX, IA_SSE3E },
Ia_pmulhrsw_Vdq_Wdq = { "pmulhrsw", "pmulhrsw", Vdq, Wdq, XX, XX, IA_SSE3E },
Ia_pmulhrsw_Pq_Qq = { "pmulhrsw", "pmulhrsw", Pq, Qq, XX, XX, IA_SSSE3 },
Ia_pmulhrsw_Vdq_Wdq = { "pmulhrsw", "pmulhrsw", Vdq, Wdq, XX, XX, IA_SSSE3 },
Ia_pmulhrw_Pq_Qq = { "pmulhrw", "pmulhrw", Pq, Qq, XX, XX, IA_3DNOW },
Ia_pmulhuw_Pq_Qq = { "pmulhuw", "pmulhuw", Pq, Qq, XX, XX, IA_3DNOW | IA_MMX },
Ia_pmulhuw_Vdq_Wdq = { "pmulhuw", "pmulhuw", Vdq, Wdq, XX, XX, IA_SSE },
@ -965,18 +965,18 @@ Ia_prefix_rex = { "rex", "rex", XX, XX, XX, XX, IA_X86_64 },
Ia_prefix_ss = { "ss", "ss", XX, XX, XX, XX, 0 },
Ia_psadbw_Pq_Qq = { "psadbw", "psadbw", Pq, Qq, XX, XX, IA_3DNOW | IA_SSE },
Ia_psadbw_Vdq_Wdq = { "psadbw", "psadbw", Vdq, Wdq, XX, XX, IA_SSE2 },
Ia_pshufb_Pq_Qq = { "pshufb", "pshufb", Pq, Qq, XX, XX, IA_SSE3E },
Ia_pshufb_Vdq_Wdq = { "pshufb", "pshufb", Vdq, Wdq, XX, XX, IA_SSE3E },
Ia_pshufb_Pq_Qq = { "pshufb", "pshufb", Pq, Qq, XX, XX, IA_SSSE3 },
Ia_pshufb_Vdq_Wdq = { "pshufb", "pshufb", Vdq, Wdq, XX, XX, IA_SSSE3 },
Ia_pshufd_Vdq_Wdq_Ib = { "pshufd", "pshufd", Vdq, Wdq, Ib, XX, IA_SSE2 },
Ia_pshufhw_Vdq_Wdq_Ib = { "pshufhw", "pshufhw", Vdq, Wdq, Ib, XX, IA_SSE2 },
Ia_pshuflw_Vdq_Wdq_Ib = { "pshuflw", "pshuflw", Vdq, Wdq, Ib, XX, IA_SSE2 },
Ia_pshufw_Pq_Qq_Ib = { "pshufw", "pshufw", Pq, Qq, Ib, XX, IA_3DNOW | IA_SSE },
Ia_psignb_Pq_Qq = { "psignb", "psignb", Pq, Qq, XX, XX, IA_SSE3E },
Ia_psignb_Vdq_Wdq = { "psignb", "psignb", Vdq, Wdq, XX, XX, IA_SSE3E },
Ia_psignd_Pq_Qq = { "psignd", "psignd", Pq, Qq, XX, XX, IA_SSE3E },
Ia_psignd_Vdq_Wdq = { "psignd", "psignd", Vdq, Wdq, XX, XX, IA_SSE3E },
Ia_psignw_Pq_Qq = { "psignw", "psignw", Pq, Qq, XX, XX, IA_SSE3E },
Ia_psignw_Vdq_Wdq = { "psignw", "psignw", Vdq, Wdq, XX, XX, IA_SSE3E },
Ia_psignb_Pq_Qq = { "psignb", "psignb", Pq, Qq, XX, XX, IA_SSSE3 },
Ia_psignb_Vdq_Wdq = { "psignb", "psignb", Vdq, Wdq, XX, XX, IA_SSSE3 },
Ia_psignd_Pq_Qq = { "psignd", "psignd", Pq, Qq, XX, XX, IA_SSSE3 },
Ia_psignd_Vdq_Wdq = { "psignd", "psignd", Vdq, Wdq, XX, XX, IA_SSSE3 },
Ia_psignw_Pq_Qq = { "psignw", "psignw", Pq, Qq, XX, XX, IA_SSSE3 },
Ia_psignw_Vdq_Wdq = { "psignw", "psignw", Vdq, Wdq, XX, XX, IA_SSSE3 },
Ia_pslld_Nq_Ib = { "pslld", "pslld", Nq, Ib, XX, XX, IA_MMX },
Ia_pslld_Pq_Qq = { "pslld", "pslld", Pq, Qq, XX, XX, IA_MMX },
Ia_pslld_Udq_Ib = { "pslld", "pslld", Udq, Ib, XX, XX, IA_SSE2 },
@ -1272,10 +1272,10 @@ Ia_subw_Ew_Iw = { "sub", "subw", Ew, Iw, XX, XX, 0 },
Ia_subw_Ew_sIb = { "sub", "subw", Ew, sIbw, XX, XX, 0 },
Ia_subw_Gw_Ew = { "sub", "subw", Gw, Ew, XX, XX, 0 },
Ia_swapgs = { "swapgs", "swapgs", XX, XX, XX, XX, IA_X86_64 },
Ia_syscall = { "syscall", "syscall", XX, XX, XX, XX, IA_SYSCALL_SYSRET },
Ia_syscall = { "syscall", "syscall", XX, XX, XX, XX, IA_X86_64 },
Ia_sysenter = { "sysenter", "sysenter", XX, XX, XX, XX, IA_SYSENTER_SYSEXIT },
Ia_sysexit = { "sysexit", "sysexit", XX, XX, XX, XX, IA_SYSENTER_SYSEXIT },
Ia_sysret = { "sysret", "sysret", XX, XX, XX, XX, IA_SYSCALL_SYSRET },
Ia_sysret = { "sysret", "sysret", XX, XX, XX, XX, IA_X86_64 },
Ia_testb_AL_Ib = { "test", "testb", AL_Reg, Ib, XX, XX, 0 },
Ia_testb_Eb_Gb = { "test", "testb", Eb, Gb, XX, XX, 0 },
Ia_testb_Eb_Ib = { "test", "testb", Eb, Ib, XX, XX, 0 },