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779 Commits

Author SHA1 Message Date
Stanislav Shwartsman
cc61e5d5d5 Leave aligment in floatx80 reg to compiler. 
CPU code no longer assume that floatx80 register is 16-byte aligned
 2004-07-02 20:24:47 +00:00
Stanislav Shwartsman
2a0a361298 Implemented precision lost up indication in floating point status word 2004-06-25 18:51:28 +00:00
Stanislav Shwartsman
dfd17222b0 Changed MMX regs access macros to avoid code duplication in MMX register declaration 2004-06-23 21:59:24 +00:00
Christophe Bothamy
ba13a484b5 - replace ResetCpu and ResetSystem by Reset(BX_RESET_SOFTWARE) and Reset(BX_RESET_HARDWARE) 2004-06-21 10:39:24 +00:00
Stanislav Shwartsman
a7cad86666 clean code 2004-06-19 19:16:02 +00:00
Stanislav Shwartsman
5873b26a82 Speed up compilation process. 
bochs.h already not include iodev.h which reduces compilation dependences for almost all cpu and fpu files, now cpu files will not be recompiled if iodev includes was changed
 2004-06-19 15:20:15 +00:00
Stanislav Shwartsman
5c5b556f24 Merge softfloat-fpu-implementation_ver4_branch branch 2004-06-18 14:11:11 +00:00
Stanislav Shwartsman
e6991f043f pply patch 
[ 924428 ] ET bit mismatch between CR0 and MSW
 2004-06-03 17:57:29 +00:00
Volker Ruppert
25582ed29d - fixed cpu/Makefile.in after renaming file 
- reg_ld_str.c: fixed regparm argument (bugfix found in SuSE 9.1 sources of Bochs 2.1.1)
 2004-05-17 19:50:43 +00:00
Stanislav Shwartsman
14b70fa9ed rename fpu.cc in cpu folder 
this fixed bug
[954751] Two FPU.CPP in project
 2004-05-16 18:46:42 +00:00
Stanislav Shwartsman
4eea772270 LOADALL for cpu-level=2 in fetchdecode 2004-05-11 16:44:58 +00:00
Stanislav Shwartsman
3274e0dd12 Commit patch 
[ 950905 ] Do not PANIC on rare, bad input from user-mode
by h.johansson
with little changes and fixes
 2004-05-10 21:05:51 +00:00
Stanislav Shwartsman
279d207d45 Fix fetchdecode bugs reported by Gilbert Netzer 
(opcode patches for x86_64 cpu)
 2004-05-03 17:58:36 +00:00
Christophe Bothamy
f4dbefad66 - fix bug reported by Thomas Weidner [ 877510 ] amd64 fixes... 2004-04-28 19:57:37 +00:00
Stanislav Shwartsman
0c47a35c99 Change BX_PANIC to BX_INFO if the behaviour exactly matches Intel docs 2004-04-17 17:10:58 +00:00
Stanislav Shwartsman
c2c447d301 Change BX_PANIC to BX_INFO in BOUND instruction 2004-04-17 16:42:11 +00:00
Stanislav Shwartsman
cf6d1b8bd9 port some changes from spftfloat-fpu branch to the MT 2004-04-09 15:34:59 +00:00
Stanislav Shwartsman
6de2dbeb49 these files should not be in MT 2004-04-09 14:27:06 +00:00
Christophe Bothamy
17328faa03 - triple fault now call bx_pc_system.ResetCpus 2004-04-08 20:57:33 +00:00
Stanislav Shwartsman
33b50ec4c4 For spammers o 2004-04-08 17:17:47 +00:00
Stanislav Shwartsman
f2dc00dda3 merge patch 
[ 904549 ] imul gives incorrect result in long mode
 2004-04-07 19:46:13 +00:00
Stanislav Shwartsman
bb1271cab6 little bit clean 64b code 2004-04-07 19:23:06 +00:00
Stanislav Shwartsman
9c4fd5ff36 clean soft_int code 2004-03-26 18:41:12 +00:00
Stanislav Shwartsman
6441d290f8 speedup and fix BCD instructions 2004-03-26 12:43:19 +00:00
Stanislav Shwartsman
02d18a283f backport softfloat changes 2004-03-20 20:01:03 +00:00
Stanislav Shwartsman
78a2976b49 backport some softfloat changes to CVS 2004-03-19 18:11:10 +00:00
Stanislav Shwartsman
b7b0b604ef implement undocumented flags modifications for BCD instructions 2004-03-18 21:43:18 +00:00
Stanislav Shwartsman
cf1d0d0aaa add comments about undocumented flags modifications in BCD.CC 
we are still need to study the flags modifications
 2004-03-13 19:37:57 +00:00
Stanislav Shwartsman
967297b8a4 new version of softfloat-fpu branch 
currectly stable
 2004-03-12 20:08:50 +00:00
Stanislav Shwartsman
dfef46e311 removed unused variables 2004-03-10 20:39:47 +00:00
Stanislav Shwartsman
58a7652aea fixed problems in BCD instructions 2004-03-10 20:14:56 +00:00
Stanislav Shwartsman
8484a03394 Fixed BCD instructions to be suitable with Intel docs 2004-03-09 20:45:17 +00:00
Stanislav Shwartsman
f50f664b10 * fixed convert float2int SSE instructions (bugfix in softfloat lib) 
* set default .bochssrc IPS to 10M
 2004-03-08 05:29:14 +00:00
Stanislav Shwartsman
97135a723f floatx80 bugfixes 2004-03-05 11:39:10 +00:00
Stanislav Shwartsman
f5316dad70 fixed bug in HADDPD/HSUBPD instructions 2004-03-05 09:19:58 +00:00
Stanislav Shwartsman
652d4ca24f wouldn't elliminate aligment for now 2004-03-03 21:15:19 +00:00
Stanislav Shwartsman
1706beda30 fixed bug in floatx80_class function 
mmx code optimizations
 2004-03-03 21:09:08 +00:00
Stanislav Shwartsman
f552a1c861 Apply patches: 
907163 ctrl_xfer8 clean/speed up   2004-02-29 14:32 nobody psychosmurf
907161 clean/speed up of io.cc   2004-02-29 14:31 nobody psychosmurf
 2004-03-02 20:48:48 +00:00
Stanislav Shwartsman
6b565750b7 port changes in softfloat to main trunk 2004-02-28 09:46:46 +00:00
Stanislav Shwartsman
3f7c794b26 commit patch 
899972 data xfer performance patch V 2.0.4   2004-02-18 15:38 nobody psychosmur
 2004-02-26 19:17:40 +00:00
Stanislav Shwartsman
c2959f7685 added floatx80_compares for future use with FPU code 
fixed floatx80 prototypes
 2004-02-25 19:18:56 +00:00
Stanislav Shwartsman
9d7d634ebc add these files to main trunk later 2004-02-21 14:48:42 +00:00
Stanislav Shwartsman
adbdde37e9 merge with latest CVS 2004-02-21 14:40:39 +00:00
Stanislav Shwartsman
320ae34cb9 Fix compile error 2004-02-18 05:22:07 +00:00
Stanislav Shwartsman
c3066a44bb added functions to softfloat for future fpu implementation 2004-02-17 21:59:24 +00:00
Christophe Bothamy
e17995f5db - host asms in a specific file 
- add msvcc host asm instructions, patch by suzu
 2004-02-15 17:57:45 +00:00
Stanislav Shwartsman
cc7b85ae7e just update release dates 2004-02-13 21:27:45 +00:00
Stanislav Shwartsman
196aee98d7 Fix for FWAIT instruction 2004-02-12 21:34:28 +00:00
Christophe Bothamy
45bd1edfbf - apply patch #894595 MSR_APICBASE always returns APIC ADDRESS 0 
by Kangmo Kim
 2004-02-12 00:56:21 +00:00
Christophe Bothamy
82429b5ac5 - fixes for booting OS/2 by Dmitri Froloff 
- v8086 priveleged instruction processing bug (was also reported by
  LightCone Aug  7 2003)
  - exception process bug (was reported by Diego Henriquez Sat Nov 15
  01:16:51 CET 2003)
  - segment validation with IRET instruction
  - CS segment not present exception processing with IRET
 2004-02-11 23:47:55 +00:00
Stanislav Shwartsman
75bbf3bc5f remove duplicated include 2004-02-11 20:04:34 +00:00
Daniel Gimpelevich
5366cc369e Added Brian Huffman's Sound for OSX code with a couple of tweaks. 2004-02-09 22:23:53 +00:00
Daniel Gimpelevich
126971af49 Made to compile on MacOS9 2004-02-06 22:28:00 +00:00
Stanislav Shwartsman
c84deba786 * FNOP instruction checks for pending FPU exceptions 
* prepared softfloatx80 code for future use with FPU
 2004-02-06 12:45:43 +00:00
Christophe Bothamy
4a22763b3a - fix sign comparison whenchecking io address in the tss io bitmap 2004-02-03 02:03:24 +00:00
Stanislav Shwartsman
dd38f0b021 fixed performance bug 
aligment field changed from 32bit (unsigned) to 8bit (unsigned char) as it should be
 2004-02-01 20:19:52 +00:00
Stanislav Shwartsman
ecdbf40aac fixed compilation error for case when 3dnow! enabled and sse not 2004-01-31 17:13:05 +00:00
Stanislav Shwartsman
77cb1436fb fix bug 2004-01-31 15:11:41 +00:00
Stanislav Shwartsman
9120961241 update checking for pending FPU exceptions code 2004-01-31 13:43:26 +00:00
Michael Brown
d1922bc835 Changed #ifdef MAGIC_BREAKPOINT to #if BX_MAGIC_BREAKPOINT and added a 
configure script option --enable-magic-breakpoints (enabled by default).

Documented the instruction required to trigger the magic breakpoint
(xchgw %bx,%bx).
 2004-01-29 17:49:03 +00:00
Christophe Bothamy
be57f55969 - fix FWAIT instruction acording to intel specs 
NM exception is raised only when cr0.mp and cr0.ts are set
 2004-01-18 16:42:05 +00:00
Daniel Gimpelevich
ae66bb33c0 Applied Russ Cox's CPU panic debug patch from Oct 2003. 2004-01-17 08:36:29 +00:00
Stanislav Shwartsman
49c6fd55e4 Remove redundant ifdefs 2004-01-10 19:45:53 +00:00
Stanislav Shwartsman
f3730cd784 Implemented two last SSE instructions RSQRTSS and RSQRTPS 
MSDEV workspaces updated with new file
CPUID will detect and CPU will execute FXSAVE/FXRSTOR instructions when cpu-level-hacked=6 and not only when cpu-level=6
 2003-12-31 17:35:43 +00:00
Stanislav Shwartsman
2dae51fc3f Fixed compilation error 2003-12-30 23:14:47 +00:00
Stanislav Shwartsman
52d75d7aed Fast table-based implementation of reciprocal (RCPSS/RCPPS) 
This implemntation is much more clear than old one.
RSQRTSS/RSQRTPS coming soon.
 2003-12-30 23:06:59 +00:00
Christophe Bothamy
e7e0b40bd1 - remove calculation on cr3 in dtranslate_linear, one of the most called functions (patch by Conn Clark) 2003-12-30 22:12:45 +00:00
Christophe Bothamy
e3bec02532 - fix bug preventing x86-64 detection 2003-12-30 14:14:28 +00:00
Stanislav Shwartsman
6fe8e9260b remove redundant CPU LEVEL checks for x86-64 2003-12-29 21:47:36 +00:00
Daniel Gimpelevich
fb80d47dbf *** empty log message *** 2003-12-29 21:24:35 +00:00
Stanislav Shwartsman
be9c0aeeec Enable FXSAVE/FXRESTOR instructions for BX_HACKED_CPU_LEVEL=6 also 2003-12-29 21:23:46 +00:00
Stanislav Shwartsman
b770d809d3 Clearify disagnostic messages. 
Remove redundant cpu level checks for x86-64
 2003-12-29 21:20:58 +00:00
Stanislav Shwartsman
7deb9491da Fixed compilation error for FPU disabled case 2003-12-29 20:26:05 +00:00
Daniel Gimpelevich
68fd1dc95b cleanup optimizations & fix compile error 2003-12-29 07:28:28 +00:00
Stanislav Shwartsman
fd60a984a0 Instructions that should not check pending FPU exceptions 2003-12-28 18:58:15 +00:00
Stanislav Shwartsman
0eb71999db Added missed 287 opcodes which should be executed as NOP in 387+ 2003-12-28 18:19:41 +00:00
Stanislav Shwartsman
9ccb363ec3 bochs style decode/execute of FPU instructions. 
With this coding style each instruction could be implemented separatelly even not together with current Bochs FPU emulator.
Step-by-step I am going to transfer all FPU instructions from current Bochs FPU emulator to new style and remove an old bugged emulator.
Anyway, now I could implement all currently missed FPU instructions without hacking wm-fpu-emu.
 2003-12-27 13:50:06 +00:00
Stanislav Shwartsman
ab6b9c7dcb New table-based disassembler: 
* Fully supports
	* MMX/XMM/3DNOW instruction sets
	* FPU instruction
	* SSE3 extensions
 currently only 16/32 bit mode bug anyway, it is much better that old one ;)
 2003-12-24 20:32:59 +00:00
Daniel Gimpelevich
fff74a6f83 Fixed incompatibility with gcc3.3, I think. 2003-11-28 15:07:29 +00:00
Zwane Mwaikambo
b152c966fc remove 'const' from bx_local_apic_c::get_type declaration, fix for wrong 
class member being called in bx_generic_apic_c::deliver
 2003-11-23 02:44:15 +00:00
Zwane Mwaikambo
8ca600665e Fix 3DNow compilation 2003-11-22 22:39:55 +00:00
Stanislav Shwartsman
b17671f5ef Fixed compilation error 2003-11-19 20:57:13 +00:00
Stanislav Shwartsman
a6c1bdbbb2 Optimization of RCPSS/RCPPS functions 2003-11-19 20:27:58 +00:00
Stanislav Shwartsman
cdb68ff8c8 Reverting back the changes in data_xfer16.cc 
Add/Fix bx_info messages in proc_ctrl.cc
 2003-11-13 21:57:13 +00:00
Stanislav Shwartsman
d51aece0c1 Change BX_PANIC messages to BX_INFO when behaviour is accepted with Intel/AMD docs. 
Instructions MOV_CxRx and MOV_RxCx are not supported in v8086 mode according to Intel manuals.
Also these instructions are treated as register-to-register regardless to MODRM byte fields (according to AMD manuals)
Also commit fix for MOV_EwSw by Kevin
 2003-11-13 21:17:31 +00:00
Stanislav Shwartsman
ac50ab3760 Implemented RCPSS/RCPPS SSE instructions 2003-11-07 20:53:27 +00:00
Stanislav Shwartsman
2f20c087c3 Remove code duplication from FXRSTOR functioN 2003-10-25 10:32:54 +00:00
Stanislav Shwartsman
4e74efdf0c Fast fxsave/fxrstor 2003-10-24 20:44:43 +00:00
Stanislav Shwartsman
ac739aa8b7 Fixed possible compilation problem 2003-10-24 20:06:12 +00:00
Stanislav Shwartsman
ac20b6405a - FXSAVE/FXRSTOR instructions should be available in P6 mode 
- Added second UD2 opcode to fetchdecode
- Added RDPMC instruction to fetchdecode
- 'changes' updated
 2003-10-24 18:34:16 +00:00
Stanislav Shwartsman
d5210af668 Two new bx_instrumentation callbacks 2003-10-09 19:05:13 +00:00
Stanislav Shwartsman
e57662214a Change BX_PANIC to BX_INFO when behaviour exactly matches Intel docs 2003-10-06 10:01:12 +00:00
Stanislav Shwartsman
9690ed763b // is not allowed in pure-C 2003-10-05 12:14:02 +00:00
Stanislav Shwartsman
149f8aef82 dos2unix fix 2003-10-05 10:05:05 +00:00
Stanislav Shwartsman
8bf447d0cd Implement a few 3DNOW instructions 2003-10-05 09:51:26 +00:00
Stanislav Shwartsman
3084a41abf Changes BX_PANIC to BX_INFO if Bochs behavour is exactly matches Intel docs 2003-10-04 20:48:13 +00:00
Stanislav Shwartsman
1e996cc329 According to Intel documentation instructions ARPL,LAR,LSL,SLDT/LLDT, 
STR/LTR,VERR/VERW are not recognized in v8086 or real mode and should
generate #UD exception
 2003-10-04 20:22:24 +00:00
Stanislav Shwartsman
03b41ad14f Small i387 structure size optimization 2003-10-04 11:04:10 +00:00
Stanislav Shwartsman
b50fb9e76e code simplification before FPU development 
print if Bochs supports 3DNOW to log file
 2003-09-27 20:58:46 +00:00
Stanislav Shwartsman
56beb4110c Little code optimization 2003-09-26 19:20:17 +00:00
Stanislav Shwartsman
15e84d0f5d dos2unix fixes 2003-09-26 16:07:38 +00:00
Stanislav Shwartsman
789db2603e Added P4 support to CPUID instruction 
Extracted CPUIS instructions to separate file
 2003-09-26 15:32:41 +00:00
Stanislav Shwartsman
bf2e0a109d Fixed compilation error (occures when fpu disabled) 2003-09-01 19:05:10 +00:00
Stanislav Shwartsman
7f570b0150 Added PNI new streaming extensions instructions 
PNI could be enabled by setting BX_SUPPORT_PNI in config.h
After the feature will be fully validation I'll also add configure option.

The implemntation is ~complete. I've missed only three FPU new opcodes of FUSTTP instruction and MONITOR/WAIT instructions.

Enjoy ! ;)
 2003-08-29 21:20:52 +00:00
Stanislav Shwartsman
254ad17328 Changes method of resolving opcode/attributes from group table 
New method more flexible and easy to understanding.
Reorganizing fetchdecode code and make it more easy and understandable
 2003-08-28 19:25:23 +00:00
Christophe Bothamy
cf70d952bc - reset also on other triple fault 2003-08-28 00:10:40 +00:00
Christophe Bothamy
9f31872f4b - implement reset on triple fault 
- old behavior (panic) can be used by setting BX_RESET_ON_TRIPLE_FAULT to 0 in config.h
 2003-08-24 23:39:33 +00:00
Christophe Bothamy
6977467ed7 - fix flaw in IO bitmap permission handling (anonymous patch) 
From the author (see bug #663320) :
  In the code there is a check to verify that an IO bitmap
  is defined (io_base > BX_CPU_THIS_PTR
  tr.cache.u.tss386.limit_scaled) but there is no check if
  an accessed IO port's address actually falls within the
  defined limit of the TSS segment. So if I define an IO
  bitmap with 100 entries, port 101 may or may not be
  allowed depending on whatever bytes follow the TSS in
  memory
 2003-08-24 23:14:52 +00:00
Christophe Bothamy
68f3624f66 - fix compile and segfault problems when configuring debugger and smp 2003-08-24 10:30:07 +00:00
Stanislav Shwartsman
79f46df971 separate APIC from CPU 2003-08-17 18:55:16 +00:00
Alexander Krisak
8559551001 iretd cpu instruction in real mode implemented, i hope this closes bugs 537047, 
603410, 637822, 664544, 687619.
 2003-08-17 18:15:04 +00:00
Stanislav Shwartsman
ecd8077b99 Fixed fetch qword function 2003-08-15 15:17:56 +00:00
Stanislav Shwartsman
60ca3ac674 ;; is not so necessary ;) 2003-08-15 13:18:53 +00:00
Stanislav Shwartsman
f6711d51f2 Fixed very serious bug in x86-64 with wrong decoding of opcodes with two immediates 2003-08-15 13:17:16 +00:00
Stanislav Shwartsman
6aa0a62fe7 Optimizing fetchdecode 2003-08-15 13:08:24 +00:00
Stanislav Shwartsman
34e6a8ed15 update sanity checks 2003-08-07 19:22:37 +00:00
Alexander Krisak
45df735c30 Apply Vitaly's Vorobyov debugger patch 2003-08-04 16:03:09 +00:00
Stanislav Shwartsman
549eb70324 Committed CPU fixes from Vitaly Vorobyov: 
[x] fixed bug in int01 (opcode 0xF1) emulation
[x] fixed bug in x86 debugger with dr0-dr3 registers

Committed disassembler bugfix from Dirk Thierbach:

[x] fixed bug in relative addresses in Jmp, Jcc, Call and so on
 2003-08-03 16:44:53 +00:00
Stanislav Shwartsman
1616539667 additional FPU changes 2003-08-01 09:32:33 +00:00
Stanislav Shwartsman
96984cb6cb Added missed fetchdecode table entry for SYSENTER/SYSEXIT 2003-06-20 08:58:12 +00:00
Stanislav Shwartsman
58efdfb31f An illegal lock prefix was not checked for instructions without any attributes (i.e. without immediate, modrm or any other additional bytes except prefixes). 2003-06-12 17:01:37 +00:00
Stanislav Shwartsman
8ee1b70016 Fixed compilation/linking problem 2003-06-11 14:50:09 +00:00
Volker Ruppert
2ef0c43c7d - description of ldtr fixed 2003-06-08 09:55:50 +00:00
Volker Ruppert
d1652093ac - applied some parts of the patch from Andrew Zabolotny <zap@cobra.ru> 
* changed all %ll format descriptions to FMT_LL macro so that
    Microsoft Visual C works correctly (it uses %I64)
  * missing type conversions added
  * cdrom.cc: variable types for win32 fixed
  * removed some unused variables in eth_win32.cc and harddrv.cc
  * added missing includes in make_cmos_image.c and niclist.c
 2003-06-07 19:16:55 +00:00
Stanislav Shwartsman
3c00944998 I hope this is the last one ... 2003-05-29 19:44:59 +00:00
Stanislav Shwartsman
56cc6469e3 Ops, missed one ... 2003-05-29 17:19:38 +00:00
Stanislav Shwartsman
f933d604d3 Fixed missed BxLockable for XCHG instruction 2003-05-29 17:15:08 +00:00
Stanislav Shwartsman
1024cb16ca Fixed denormal problem in fload64_add operation 2003-05-27 20:30:19 +00:00
Stanislav Shwartsman
b6ff1e6d9d dos2unix for softfloat 
fixed denormals handling for MUL/DIV instructions
 2003-05-26 19:30:33 +00:00
Stanislav Shwartsman
ab3320c6eb Fixed denormal operand handling for add/sub instructions 2003-05-26 19:00:19 +00:00
Stanislav Shwartsman
0cb847f6d3 Quite different implementation of DAZ feature 
Fixed bugs in execution of float64 packed instructions (almost all instructions affected)
 2003-05-26 18:06:09 +00:00
Stanislav Shwartsman
c82060a215 Fixed problem with compare unordered and denormals exceptions 2003-05-25 20:18:46 +00:00
Stanislav Shwartsman
39ab1d18ac Fixed compilation error 2003-05-23 08:49:55 +00:00
Stanislav Shwartsman
777e0db06b Fixed cpu.cc compilation error with ICache disabled 
Added --enable-3dnow configuration option
 2003-05-21 15:48:55 +00:00
Stanislav Shwartsman
140ff2541b Ability to configure x86-64 without 3DNOW 2003-05-21 15:20:51 +00:00
Stanislav Shwartsman
04ebd29f92 dos2unix fix 2003-05-19 15:02:47 +00:00
Stanislav Shwartsman
e5c647ad01 Removed unused some unused functions from softfloat 2003-05-18 03:52:18 +00:00
Stanislav Shwartsman
36a8c8a6ac Compare unordered relation also raises denormal 2003-05-17 18:11:22 +00:00
Stanislav Shwartsman
338e7b4fe2 DAZ support (still under validation) 2003-05-17 17:45:54 +00:00
Stanislav Shwartsman
7e7cbdba6f Bugdfix for pfp compare operation (affected 'greater_than' relation) 2003-05-17 14:49:21 +00:00
Stanislav Shwartsman
09b987a9e8 Denormals support for all SSE instructions 2003-05-17 09:08:18 +00:00
Stanislav Shwartsman
6fdecf77a1 New dependencies for CPU directory 2003-05-15 18:46:01 +00:00
Stanislav Shwartsman
928e20bd49 Changed some BX_INFO messages to BX_DEBUG 2003-05-15 18:32:27 +00:00
Stanislav Shwartsman
1d45167e5b Merged NEW-INSTRUCTIONS branch 2003-05-15 16:41:17 +00:00
Kevin Lawton
a17d06abcb Optimized the main cpu loop iCache checks to remove a redundant 
check.

Commented out a number of instances of invalidate_prefetch_q(),
for branches which do not change CS since the EIP window mechanism
takes care of validating that EIP lands in the current page or not
in the main cpu loop anyways.

Fixed a couple cases (v8086 mode and real mode) of loading CS where
the EIP page window was not invalidated in segment_ctrl_pro.cc.
That may fix some aliasing problems reported before (OS2).
 2003-05-10 22:25:55 +00:00
Christophe Bothamy
091052e199 - reverting to previous revision (xfer8 1.15, xfer16 1.21, xfer32 1.21) 
as it breaks AMD64 support.
 2003-05-08 17:56:48 +00:00
Christophe Bothamy
b3d16a48ef - apply another speedup patch from Conn Clark. 
Notes from the author:
Here is another one of my speed up patches. Unlike my previous speedups
this one will help more platforms than just X86. It cleans up the Data
Xfer instructions. Since the Data Xfer instructions are the most often
executed instructions it gives a noticable boost in speed. The basic
optimization technique was to eliminate intermediate variables and pass
a pointer to the final destination or original source to the
read_virtual_whatever and the write_virtual_whatever functions.
 2003-05-03 16:19:07 +00:00
Volker Ruppert
79b811f23f - fixed warnings in these files: 
cpu/fetchdecode.cc
  cpu/mmx.cc
  cpu/proc_ctrl.cc
  iodev/virt_timer.cc
  plugin.cc
 2003-05-02 12:22:48 +00:00
Christophe Bothamy
83b8bbedff - fix REX MOVB immediate for x86_64 (patch by Arnd Bergmann) 
(bug [ 720776 ] REX MOVB immediate broken for x86_64)
 2003-04-26 10:02:03 +00:00
Stanislav Shwartsman
fa623fda74 FPU tag word is 16bit only 2003-04-25 18:43:48 +00:00
Stanislav Shwartsman
88d433bb73 Implemented MASKMOVQ 2003-04-23 18:57:57 +00:00
Stanislav Shwartsman
3485368ead Ups, forgot smth ;) 2003-04-23 18:55:25 +00:00
Stanislav Shwartsman
ba2b84e604 Implemented MASKMOVQ and MASKMOVDQU instructions 2003-04-23 18:51:37 +00:00
Stanislav Shwartsman
446fca9ed0 Superfluous braces in initializers in fetchdecode.cc 2003-04-23 17:52:59 +00:00
Stanislav Shwartsman
d1d2fb34f0 Fixed number of compilation errors for FPU disabled case 
Transfer fpu.cc from /fpu to /cpu
 2003-04-22 20:21:34 +00:00
Stanislav Shwartsman
40bd4f138b Little style changes 
Elliminated i387_t alimit field (not used in FPU)
 2003-04-16 18:38:53 +00:00
Stanislav Shwartsman
aa9152129c Changes in i387 register file definition. Define common FPU/MMX register file. 2003-04-12 21:02:08 +00:00
Stanislav Shwartsman
1d54caca9b Fixed compilation error 2003-04-09 19:20:05 +00:00
Stanislav Shwartsman
7db893970c Read attributes bits even for BxSplit11b opcodes 
Move lock prefix check later in fetchdecode function when all attributes is ready.
 2003-04-06 19:08:31 +00:00
Stanislav Shwartsman
a050c1ac7d Reserved cpu attribute bit for 3DNOW instructions decoding 2003-04-05 16:40:55 +00:00
Stanislav Shwartsman
216124c6c3 Send #MF exception for MMX instructions if there is a pending FPU exception 2003-04-05 12:49:14 +00:00
Stanislav Shwartsman
1e71c9e56e Merged patch-unallowed-lock-cases patch. 
According to the Intel manuals:

  The  LOCK  prefix  can be prepended only to the following instructions
  and  only  to  those  forms  of the instructions where the destination
  operand  is  a  memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG,
  CMPXCH8B,  DEC,  INC,  NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. If
  the  LOCK prefix is used with one of these instructions and the source
  operand  is a memory operand, an undefined opcode exception (#UD) will
  be  generated. An undefined opcode exception will also be generated if
  the  LOCK  prefix  is used with any instruction not in the above list.

 Checking of the LOCK prefix done in fetchDecode state and not overloads
 Bochs's execution.
 2003-04-05 12:16:53 +00:00
Stanislav Shwartsman
8193a710ad Changed MMX/SSE/SSE2 diagnostic messages to be more informative 2003-03-21 20:33:23 +00:00
Stanislav Shwartsman
1224c2d307 #UD exception should be generated when using MOV_SwEw opcode for 
loading CS register
 2003-03-21 13:34:24 +00:00
Christophe Bothamy
1a518b81fe - add __attribute__((regparm(X))) performance trick with gcc on x86 
on some cpu instructions (patch from Conn Clark)
- performance improvement is 1% on win95 boot
 2003-03-17 00:41:01 +00:00
Peter Tattam
752caf8e21 x86-64 emulation 
Fixed PUSHFW/POPFW for 64 bit mode. (was doing PUSHFQ/POPFQ)
 2003-03-13 00:49:20 +00:00
Peter Tattam
2f9088a223 x86-64 emulation. 
Fixed IRETD in 64 bit mode
 2003-03-13 00:45:44 +00:00
Peter Tattam
530f482c79 x86-64 Update - Fixed bad JMP far indirect 2003-03-13 00:43:00 +00:00
Peter Tattam
cb492ae7b5 x86-64 emulation. 
Perform Canonical Address Checking.

Only does basic checking (only offset, not offset+size-1)
 2003-03-13 00:37:40 +00:00
Christophe Bothamy
50efc3b8c7 - apply Conn Clark's patch.perf-regparm-cclark : 
- it works only on x86 with gcc2.95+
  - uses the GCC function atribute "regparm(n)" to declare that certain
    functions use the register calling convention
  - performance improvement is about 6%
 2003-03-02 23:59:12 +00:00
Stanislav Shwartsman
8665979c87 * Fixed behavior of BX_INSTR_MEM_DATA callback for RMW memory accesses 
See instrumentation.txt for details
 2003-02-28 20:51:08 +00:00
Peter Tattam
94880d1412 Fix guest2host and related optimizations to work on 64 bit host. 
1) fixed the type of "hostPageAddr" and associated typecasts.
2) fixed the type of "pages" and associated typecasts (overloaded variable)
3) patch to cpu.cc to calculate "eipPageBias" correctly in 64 bit mode
 2003-02-28 02:37:18 +00:00
Peter Tattam
11a12142bc x64-64 emulation updates. 
1) fixed some errors running 32 bit compat mode.  IMPORTANT FIX.
2) added IST processing (uses IST1-IST7 in 64 bit TSS)
3) cosmetic - debugging stuff to console.
 2003-02-26 02:48:12 +00:00
Peter Tattam
70d752c8c2 external debugger only: fixed ask() to be virtual to let a panic trap into external debugger 2003-02-26 02:41:30 +00:00
Peter Tattam
0c39404940 cosmetic - extra console debugging for 64 bit mode. 2003-02-26 02:37:08 +00:00
Peter Tattam
4cc7139c3a fix for BX_CPU_LEVEL < 4 2003-02-26 02:35:11 +00:00
Peter Tattam
3aa1b591c1 add some debugging info for 64 bit mode. 2003-02-26 02:24:15 +00:00
Peter Tattam
0f94706c80 minor tweak to 64 bit stack push to ignore segmentation checks. Not required in 64 bit mode so is 
a minor optimization.  Also in transition from compat mode to 64 bit mode (e.g. interrupt to inner
privelege with mode change), SS may not be properly defined - this avoids other messiness.
 2003-02-26 00:59:31 +00:00
Peter Tattam
131bbb54c5 When external debugger enabled, change INT1 to be 
transparent (i.e. not call the guest int1 ISR)
 2003-02-26 00:53:38 +00:00
Stanislav Shwartsman
7fa75388a1 Added bx_cpuid value to the BX_CPU class to avoid any problems with BX_CPU_ID implementation 2003-02-13 15:51:22 +00:00
Stanislav Shwartsman
cdfc3cbce4 instrumentation enchancements: 
* renamed CPU_ID to BX_CPU_ID.
  with this new name there is no possibility for name contentions and BX_CPU_ID
  definition could be moved out to NEED_CPU_REG_SHORTCUTS block

* returned back `unsigned BX_CPU::which_cpu(void)` function

* added BX_CPU_ID parameter for
	BX_INSTR_PHY_READ(a20addr, len);
	BX_INSTR_PHY_WRITE(a20addr, len);
    now it will be
	BX_INSTR_PHY_READ(cpu_id, a20addr, len);
	BX_INSTR_PHY_WRITE(cpu_id, a20addr, len);
 2003-02-13 15:04:11 +00:00
Bryce Denney
7336c891ee - CPU_ID fix from Shai Fultheim, who writes: 
> CPU_ID is defined as
  > #define CPU_ID (BX_CPU_THIS_PTR local_apic.get_id())
  > This is not true when the APIC name is changed (true in Linux). Please
  > change this to:
  > #define CPU_ID (BX_CPU_THIS - BX_CPU(0))
 2003-02-09 13:30:39 +00:00
Peter Tattam
22d855a6c0 Fixed wrong RETF instructions for 64 bit mode. 2003-02-08 05:51:38 +00:00
Peter Tattam
c4bf554432 Fixed wrong increment for enter where level > 0 2003-02-08 05:48:01 +00:00
Stanislav Shwartsman
5991599dca Added BX_INFO messages when execution FXSAVE/FXRSTOR instructions 2003-01-23 18:50:37 +00:00
Stanislav Shwartsman
5222261080 Save/Restore FPU TOP-OF-STACK in FXSAVE/FXRSTOR instructions 2003-01-23 18:33:35 +00:00
Stanislav Shwartsman
e1b8e5b9f9 Fixed FTW save/restore in FXSAVE/FXRSTOR opcodes 2003-01-23 17:53:11 +00:00
Christophe Bothamy
77e33ccf26 - fix a "too many arguments for format" warning 2003-01-22 21:43:34 +00:00
Christophe Bothamy
c6abf1d0d1 - fix old #if BX_SUPPORT_SYSENTEREXIT found by Stanislav. The sysenter/exit code was not called at all! 2003-01-20 21:30:00 +00:00
Christophe Bothamy
939b558fdf - apply patch.sysenterexit-mrieker: 
- adds sysenter/sysexit support for cpu-level>=6
  - enabled by ./configure --enable-sep
 2003-01-20 20:10:31 +00:00
Christophe Bothamy
ed57d3d45d - add changes requested by ams, sgdt and sidt in v8086 mode 2003-01-17 18:08:13 +00:00
Stanislav Shwartsman
d1edcde9ed Cleanup Peter's change in MOVNTI instruction 2003-01-14 14:58:56 +00:00
Peter Tattam
24d4a5003c patches to CPUID required to get latest x86-64 linux kernel (2.4.20) to run. 
I believe this patch is ok, however it should be regression tested to make sure
nothing is broken.
 2003-01-14 07:46:05 +00:00
Peter Tattam
6e359d62ed disable calling external debugger when jumping in & out of 64 bit mode. 2003-01-14 07:40:21 +00:00
Peter Tattam
b2622c5d04 Temporary tweak to reinstate a change that disappeared when sse2.cc was removed. 
The 64 bit variant of MOVNTI was not decoded.  The proper fix for this is to work on
fetchdecode64.cc to call a 64 bit variant of SSE instructions or fail it with a
invalid op.  A careful check needs to be done with the AMD manuals to determine if
there are any other SSE instructions that have a special 64 bit decoding.
 2003-01-14 06:50:01 +00:00
Stanislav Shwartsman
513db033ab fixed compilation error and a logic bug together 2003-01-09 05:21:22 +00:00
Stanislav Shwartsman
e6eacd984f Implemented MOVD 64bit extensions 2003-01-08 20:33:28 +00:00
Stanislav Shwartsman
633d0b59fb clean up of error messages 2002-12-30 18:51:09 +00:00
Stanislav Shwartsman
7dcd9ab8ec * implemented MOVLHS/MOVHPS/MOVHLPS/MOVLHPS opcodes 
* another reorganization of SSE code
 2002-12-30 18:10:10 +00:00
Stanislav Shwartsman
7e41d08620 Fixed problem with shift imm instructions 2002-12-30 08:03:34 +00:00
Stanislav Shwartsman
e1d5cddc6d Fixed a problem with zero-count shift in following instructions: 
PSRAW_PqQq    (MMX)
PSRAD_PqQq    (MMX)
PSRAW_PqIb    (MMX)
PSRAD_PqIb    (MMX)

PSRAW_VdqWdq  (SSE)
PSRAD_VdqWdq  (SSE)
PSRAW_PdqIb   (SSE)
PSRAD_PdqIb   (SSE)

When register was shifted by 0 bits the result produced was incorrect.

Now Bochs fully passes MMX test provided by
Hentai Yagi [hentai_yagi@yahoo.com.au] !
 2002-12-29 21:14:25 +00:00
Stanislav Shwartsman
8909ce442c Fixed problem in PSRLD_PqIb instruction 2002-12-28 20:18:56 +00:00
Stanislav Shwartsman
6ccd2fb7fa Fixed bug in following MMX instructions: 
void BX_CPU_C::PUNPCKLBW_PqQd(bxInstruction_c *i)
void BX_CPU_C::PUNPCKLWD_PqQd(bxInstruction_c *i)
void BX_CPU_C::PUNPCKLDQ_PqQd(bxInstruction_c *i)

Thanks to Hentai Yagi [hentai_yagi@yahoo.com.au]
that provided nessesary test application.
 2002-12-28 19:06:29 +00:00
Stanislav Shwartsman
9c5c40e8ce Fixed BX_INSTR_OPCODE call when instruction was found in the ICache 2002-12-26 20:22:35 +00:00
Stanislav Shwartsman
b08f208b9f Fixed compilation error 2002-12-24 20:59:55 +00:00
Stanislav Shwartsman
6acff47112 Implemented the following SSE instructions (sse_move.cc): 
MOVSS_VssWss
MOVSS_WssVss
MOVSD_VsdWsd
MOVSD_WsdVsd
MOVMSKPS_GdVRps
MOVMSKPD_EdVRpd
MOVQ_VqWq
MOVQ_WqVq
SHUFPS_VpsWpsIb
SHUFPD_VpdWpdIb
 2002-12-24 20:19:35 +00:00
Stanislav Shwartsman
4b59ecbc62 Implemented SSE/SSE2 duplicate opcodes in more intellegent way ... 2002-12-22 21:48:23 +00:00
Stanislav Shwartsman
29ab05b4da Removed duplicate SSE opcodes 2002-12-22 20:48:45 +00:00
Stanislav Shwartsman
e73df72525 implementation of additional SSE/SSE2 instructions 2002-12-22 20:42:56 +00:00
Stanislav Shwartsman
1cd38bb7dd Recommitted SSE code reorganization. 
Fix in FXSAVE/FXRESTOR opcodes -> If the OSFXSR bitCR4 is not set, the FXRSTOR instruction does not restore the states of the XMM and MXCSR registers.
 2002-12-22 20:13:00 +00:00
Bryce Denney
90d711e5d1 - add missing break stmts, pointed out by Shai Fultheim 2002-12-22 15:15:56 +00:00
Stanislav Shwartsman
f2f976d736 Add BX_INSTR_FETCH_DECODE_COMPLETED call even if an instruction hitten in ICache 2002-12-20 13:36:50 +00:00
Stanislav Shwartsman
4906ffef7c Clean Peter's commit with MOVNTDQ instruction implementation 2002-12-20 09:11:39 +00:00
Peter Tattam
c173034663 Patches to round off the x86-64 emulation to get the Linux x86-64 kernel and 
sash to run.

1) fixed fetchdecode64.cc to fix the operand size at 64 bits in long mode for moves
   to/from CRx

2) minor patches to sse2.cc to fix unimplemented and 64 bit variants of sse2
instructions.
 2002-12-20 07:11:29 +00:00
Bryce Denney
9b2914fd1d - Temporarily revert Stanislav's changes between 2002-12-18 and 2002-12-19. 
Because source files were added/removed it would require an update
  of the windows and macos project files, so I want to wait until after 2.0.
    M Makefile.in         1.51 back to 1.50
    M cpu.h               1.121 back to 1.120
    M fetchdecode.cc      1.37 back to 1.36
    M fetchdecode64.cc    1.33 back to 1.32
    M sse.cc              1.17 back to 1.16
    A sse2.cc             1.27 back to 1.26  (added back)
    R sse_move.cc         removed
    R sse_pfp.cc          removed
- to bring these changes back again, all we have to do is
  "cvs update -j tmp-before1 -j tmp-after1"
 2002-12-19 05:53:18 +00:00
Stanislav Shwartsman
aa361badf2 Reorganized SSE/SSE2 code 
sse.cc -> general SSE stuff and SSE integer (MMX extensions)
sse_move.cc -> memory transfer and shuffle opcodes
sse_pfp.cc -> packed floating point operations
 2002-12-18 22:33:44 +00:00
Bryce Denney
9a204569b7 - patch from Zwane on December 9. He writes: 
> It's safe to deliver ExtINT as Fixed in our setup and just leave a comment
  > there instead of the panic.
 2002-12-14 08:48:20 +00:00
Christophe Bothamy
16ebfdb9e1 - update for macos compile 2002-12-12 15:29:45 +00:00
Christophe Bothamy
ff89875ffd - remove unused (seems to be) typedef 2002-12-12 13:26:29 +00:00
Stanislav Shwartsman
04c7d9301b implemented 
PINSRW_VdqEdIb
PEXTRW_VdqEdIb
PINSRW_PqEdIb
PEXTRW_PqEdIb

instructions
 2002-12-02 21:24:09 +00:00
Stanislav Shwartsman
3012e7c361 Fixed representation and aligment of FPU/MMX register(s). 
Description/justification:

Endian  Host byte order         Guest (x86) byte order
======================================================
Little  FFFFFFFFEEAAAAAA        FFFFFFFFEEAAAAAA
Big     AAAAAAEEFFFFFFFF	FFFFFFFFEEAAAAAA

F - fraction/mmx
E - exponent
A - aligment
 2002-11-30 17:15:59 +00:00
Stanislav Shwartsman
57fd94744d Implemented MOVQ2DQ/MOVDQ2Q instructions 
Small fixes with MMX environment
 2002-11-30 14:42:41 +00:00
Stanislav Shwartsman
bcd57bdcaf *** Current duplicate SSE/SSE2 instructions list *** 
MOVUPS_VpsWps  (0f 10) = MOVUPD_VpdWpd  (66 0f 10) = MOVDQU_VdqWdq (f3 0f 6f)
MOVUPS_WpsVps  (0f 11) = MOVUPD_WpdVpd  (66 0f 11) = MOVDQU_WdqVdq (f3 0f 7f)
MOVAPS_VpsWps  (0f 28) = MOVAPD_VpdWpd  (66 0f 28) = MOVDQA_VdqWdq (66 0f 6f)
MOVAPS_WpsVps  (0f 29) = MOVAPD_WpdVpd  (66 0f 29) = MOVDQA_WdqVdq (66 0f 7f)

MOVNTPS_MdqVps (0f 2b) = MOVNTPD_MdqVpd (66 0f 2b)
MOVLPS_VpsMq   (0f 12) = MOVLPD_VsdMq   (66 0f 12)
MOVLPS_MqVps   (0f 13) = MOVLPD_MqVsd   (66 0f 13)
MOVHPS_VpsMq   (0f 16) = MOVHPD_VpdMq   (66 0f 16)
MOVHPS_MqVps   (0f 17) = MOVHPD_MqVpd   (66 0f 17)

ANDPS_VpsWps   (0f 54) = ANDPD_VpdWpd   (66 0f 54) = PAND_VpdWpd   (66 0f db)
ANDNPS_VpsWps  (0f 55) = ANDNPD_VpdWpd  (66 0f 55) = PANDN_VpdWpd  (66 0f df)
ORPS_VpsWps    (0f 56) = ORPD_VpdWpd    (66 0f 56) = POR_VpdWpd    (66 0f eb)
XORPS_VpsWps   (0f 57) = XORPD_VpdWpd   (66 0f 57) = PXOR_VpdWpd   (66 0f ef)

Removed dupes
 2002-11-25 21:58:55 +00:00
Bryce Denney
3edf45a1d9 - regenerate makefile dependencies 2002-11-25 15:05:51 +00:00
Stanislav Shwartsman
a4806d3fce Fixed the MXCSR mask value 2002-11-22 21:42:46 +00:00
Stanislav Shwartsman
9bf3b44665 Fixed a little logic problem with FPU TWD save/restore 2002-11-22 21:33:12 +00:00
Stanislav Shwartsman
2b2e773dde Fixed a problem in LDMXCSR instruction 
Beta version of FXSAVE/FXRSTOR instructions implementation
(still imcomplete, doesn't fully restore FPU state)
 2002-11-22 21:21:31 +00:00
Stanislav Shwartsman
b4f060e698 Initialize SSE environment at reset 2002-11-22 09:36:28 +00:00
Bryce Denney
dcedff8d46 - fix some minor compile bugs that appear when you mix up instrumentation, 
debugger, SMP, and x86-64.  A few macros were missing the CPU_ID argument,
  and a few passed nonexistent variables to the instrumentation macros.
- I changed CPU_ID into a plain old macro instead of an inline call to a
  trivial which_cpu() function, and removed which_cpu().

Modified Files:
  cpu/cpu.h cpu/ctrl_xfer64.cc debug/dbg_main.cc
 2002-11-21 18:22:03 +00:00
Christophe Bothamy
3104ba6bea - fix [ 625878 ] reset doesn't reset something(?) 
In bx_cpu_c::reset method I set bx_cpu->async_event to 2
  so execution in the cpu_loop gets stopped early.

  Previously, async_event was set to 0, and with repeatable
  instructions, after reset, eip was incremented by the instruction
  length, so execution would resume at 0xffffX (X being >0, the current
  instruction length).

  In halt state I check now for reset with async_event is 2, so
  reset works also when the cpu is halted. (update to Peter change)

  I hope I fixed this the right way, please report any strange behaviour.
 2002-11-21 08:08:29 +00:00
Bryce Denney
9b14101a05 - rewrite typecast of temp to Bit64u to keep VC++ happy. I don't really 
know what it thought was wrong.
 2002-11-19 05:53:47 +00:00
Bryce Denney
dcc6d6038a - we forgot to initialize trace_reg and kill_bochs_request to 0. 2002-11-19 05:52:52 +00:00
Bryce Denney
97f911d1fe - when VC++ sees local variables in a for statement, it doesn't think 
that they go out of scope at the end, so it complains about duplicate
  definitions.
 2002-11-19 05:51:52 +00:00
Bryce Denney
0a7cb3a43c - apply patch.ifdef-disabled-options. Comments from that patch are below: 
For a whole lot of configure options, I put #if...#endif around code that
  is specific to the option, even in files which are normally only compiled
  when the option is on.  This allows me to create a MS Visual C++ 6.0
  workspace that supports many of these options.  The workspace will basically
  compile every file all the time, but the code for disabled options will
  be commented out by the #if...#endif.

  This may one day lead to simplification of the Makefiles and configure
  scripts, but for the moment I'm leaving Makefiles and configure scripts
  alone.

  Affected options:
    BX_SUPPORT_APIC (cpu/apic.cc)
    BX_SUPPORT_X86_64 (cpu/*64.cc)
    BX_DEBUGGER (debug/*)
    BX_DISASM (disasm/*)
    BX_WITH_nameofgui (gui/*)
    BX_SUPPORT_CDROM (iodev/cdrom.cc)
    BX_NE2K_SUPPORT (iodev/eth*.cc, iodev/ne2k.cc)
    BX_SUPPORT_APIC (iodev/ioapic.cc)
    BX_IODEBUG_SUPPORT (iodev/iodebug.cc)
    BX_PCI_SUPPORT (iodev/pci*.cc)
    BX_SUPPORT_SB16 (iodev/sb*.cc)

Modified Files:
  cpu/apic.cc cpu/arith64.cc cpu/ctrl_xfer64.cc
  cpu/data_xfer64.cc cpu/fetchdecode64.cc cpu/logical64.cc
  cpu/mult64.cc cpu/resolve64.cc cpu/shift64.cc cpu/stack64.cc
  debug/Makefile.in debug/crc.cc debug/dbg_main.cc debug/lexer.l
  debug/linux.cc debug/parser.c debug/parser.y
  disasm/dis_decode.cc disasm/dis_groups.cc gui/amigaos.cc
  gui/beos.cc gui/carbon.cc gui/macintosh.cc gui/rfb.cc
  gui/sdl.cc gui/term.cc gui/win32.cc gui/wx.cc gui/wxdialog.cc
  gui/wxmain.cc gui/x.cc iodev/cdrom.cc iodev/eth.cc
  iodev/eth_arpback.cc iodev/eth_fbsd.cc iodev/eth_linux.cc
  iodev/eth_null.cc iodev/eth_packetmaker.cc iodev/eth_tap.cc
  iodev/eth_tuntap.cc iodev/eth_win32.cc iodev/ioapic.cc
  iodev/iodebug.cc iodev/ne2k.cc iodev/pci.cc iodev/pci2isa.cc
  iodev/sb16.cc iodev/soundlnx.cc iodev/soundwin.cc
 2002-11-19 05:47:45 +00:00
Bryce Denney
add9107dae - add BOCHSAPI to bxICache_c 2002-11-15 18:12:04 +00:00
Stanislav Shwartsman
3217759a75 Implemented 
PSHUFLW_VqWqIb, PSHUFHW_VqWqIb instructions
 2002-11-15 17:34:47 +00:00
Stanislav Shwartsman
da8a2a71b1 Fixed bug PSHUFW instruction 2002-11-15 17:02:06 +00:00
Stanislav Shwartsman
62e362afc2 just typo 2002-11-15 15:55:36 +00:00
Stanislav Shwartsman
34dd74fe6c Fixed BUG in PMADDWD instruction 2002-11-15 15:51:12 +00:00
Stanislav Shwartsman
189f64b533 SSE2 shifts uses as count only low 64 bits of XMM register/mem128 2002-11-15 14:48:24 +00:00
Stanislav Shwartsman
d4426dc60b More bugfix in SSE 2002-11-15 14:33:44 +00:00
Stanislav Shwartsman
88ce9917e6 Replace BX_PANIC to BX_INFO for FXSAVE/FXRSTOR instruction 
because their is required for booting Windows with SSE enabled.
 2002-11-15 13:10:06 +00:00
Stanislav Shwartsman
121de7d960 Fixed bug with decoding of Group15 2002-11-15 13:05:19 +00:00
Stanislav Shwartsman
ccbc8e0ef7 MOVAPS/MOVAPD have a different exceptions 2002-11-15 12:44:39 +00:00
Stanislav Shwartsman
65b8712d04 More tuning of SSE 2002-11-14 19:59:29 +00:00
Stanislav Shwartsman
7ccf1de78f According to the Intel (and AMD) manuals a lot different SSE/SSE2 opcodes has EXACTLY the same operation. 
Deleted first three redundant opcodes (move integer data):
   MOVLPS_VpsMq   (0f 12) = MOVLPD_VsdMq   (66 0f 12)
   MOVLPS_MqVps   (0f 13) = MOVLPD_MqVsd   (66 0f 13)
   MOVHPS_VpsMq   (0f 16) = MOVHPD_VpdMq   (66 0f 16)
   MOVHPS_MqVps   (0f 17) = MOVHPD_MqVpd   (66 0f 17)

Until under examination:
XORPS,XORPD
ORPS,ORPD
ANDPS,ANDPD
ANDNPS,ANDNPD
MOVUPS,MOVUPD
 2002-11-13 22:24:03 +00:00
Stanislav Shwartsman
968b2744f4 According to the Intel (and AMD) manuals a lot different SSE/SSE2 opcodes 
has EXACTLY the same operation.

Deleted first three redundant opcodes:
   MOVAPS_VpsWps  (0f 28) = MOVAPD_VpdWpd  (66 0f 28)
   MOVAPS_WpsVps  (0f 29) = MOVAPD_WpdVpd  (66 0f 29)
   MOVNTPS_MdqVps (0f 2b) = MOVNTPD_MdqVpd (66 0f 2b)

Until checking:
XORPS,XORPD
ORPS,ORPD
ANDPS,ANDPD
ANDNPS,ANDNPD
MOVUPS,MOVUPD
MOVLPS,MOVLPD
MOVHPS,MOVHPD
 2002-11-13 21:35:17 +00:00
Stanislav Shwartsman
5803e20240 Changed policy of SSE/SSE2 checking 2002-11-13 21:00:05 +00:00
Stanislav Shwartsman
6c6519a73d Implemented SSE2 integer instructions: 
PMULHW_VdqWdq
PMULHUW_VdqWdq
PMULLW_VdqWdq
MOVNTI_MdGd

Somedoby that is the difference between MOVNTPD, MOVNTPS, MPVNTDQ instructions ?
 2002-11-09 19:22:00 +00:00
Stanislav Shwartsman
bc0463f08a Implemented 
PSRLDQ_WdqIb
PSLLDQ_WdqIb
instructions
 2002-11-08 21:09:17 +00:00