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Little code optimization

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This commit is contained in:
Stanislav Shwartsman 2003-09-26 19:20:17 +00:00
parent 15e84d0f5d
commit 56beb4110c
2 changed files with 14 additions and 14 deletions
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12
bochs/cpu/mmx.cc
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@ -1237,7 +1237,7 @@ void BX_CPU_C::PANDN_PqQq(bxInstruction_c *i)
#if BX_SUPPORT_MMX
BX_CPU_THIS_PTR prepareMMX();
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
/* op2 is a register or memory reference */
if (i->modC0()) {
@ -1248,10 +1248,10 @@ void BX_CPU_C::PANDN_PqQq(bxInstruction_c *i)
read_virtual_qword(i->seg(), RMAddr(i), (Bit64u *) &op2);
}
MMXUQ(result) = ~(MMXUQ(op1)) & MMXUQ(op2);
MMXUQ(op1) = ~(MMXUQ(op1)) & MMXUQ(op2);
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), result);
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PANDN_PqQq: required MMX, use --enable-mmx option"));
UndefinedOpcode(i);
@ -1925,7 +1925,7 @@ void BX_CPU_C::PSADBW_PqQq(bxInstruction_c *i)
#if BX_SUPPORT_3DNOW || BX_SUPPORT_SSE >= 1
BX_CPU_THIS_PTR prepareMMX();
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
Bit16u temp = 0;
/* op2 is a register or memory reference */
@ -1946,10 +1946,10 @@ void BX_CPU_C::PSADBW_PqQq(bxInstruction_c *i)
temp += abs(MMXUB6(op1) - MMXUB6(op2));
temp += abs(MMXUB7(op1) - MMXUB7(op2));
MMXUW0(result) = (Bit64u) temp;
MMXUW0(op1) = (Bit64u) temp;
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), result);
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PSADBW_PqQq: required SSE or 3DNOW, use --enable-sse or --enable-3dnow options"));
UndefinedOpcode(i);

16
bochs/cpu/sse.cc
View File

@ -838,7 +838,7 @@ void BX_CPU_C::PANDN_VdqWdq(bxInstruction_c *i)
#if BX_SUPPORT_SSE >= 1
BX_CPU_THIS_PTR prepareSSE();
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
/* op2 is a register or memory reference */
if (i->modC0()) {
@ -849,11 +849,11 @@ void BX_CPU_C::PANDN_VdqWdq(bxInstruction_c *i)
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
}
result.xmm64u(0) = ~(op1.xmm64u(0)) & op2.xmm64u(0);
result.xmm64u(1) = ~(op1.xmm64u(1)) & op2.xmm64u(1);
op1.xmm64u(0) = ~(op1.xmm64u(0)) & op2.xmm64u(0);
op1.xmm64u(1) = ~(op1.xmm64u(1)) & op2.xmm64u(1);
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PANDN_VdqWdq: required SSE, use --enable-sse option"));
UndefinedOpcode(i);
@ -1575,7 +1575,7 @@ void BX_CPU_C::PSADBW_VdqWdq(bxInstruction_c *i)
#if BX_SUPPORT_SSE >= 2
BX_CPU_THIS_PTR prepareSSE();
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
Bit16u temp1 = 0, temp2 = 0;
/* op2 is a register or memory reference */
@ -1605,11 +1605,11 @@ void BX_CPU_C::PSADBW_VdqWdq(bxInstruction_c *i)
temp2 += abs(op1.xmmubyte(0xE) - op2.xmmubyte(0xE));
temp2 += abs(op1.xmmubyte(0xF) - op2.xmmubyte(0xF));
result.xmm64u(0) = Bit64u(temp1);
result.xmm64u(1) = Bit64u(temp2);
op1.xmm64u(0) = Bit64u(temp1);
op1.xmm64u(1) = Bit64u(temp2);
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PSADBW_VdqWdq: required SSE2, use --enable-sse option"));
UndefinedOpcode(i);