Changed policy of SSE/SSE2 checking
This commit is contained in:
Stanislav Shwartsman
parent
84b4cf6d4c
commit
5803e20240
@ -670,8 +670,7 @@ typedef
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#define BX_SUPPORT_FPU 0
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#define BX_SUPPORT_MMX 0
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#define BX_SUPPORT_SSE 0
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#define BX_SUPPORT_SSE2 0
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#define BX_SUPPORT_SSE 0
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#define BX_SUPPORT_4MEG_PAGES 0
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#define BX_SupportGuest2HostTLB 0
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#define BX_SupportRepeatSpeedups 0
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14
bochs/configure
vendored
14
bochs/configure
vendored
@ -19842,29 +19842,17 @@ fi;
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if test "$support_sse" = 2; then
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cat >>confdefs.h <<\_ACEOF
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#define BX_SUPPORT_SSE 1
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_ACEOF
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cat >>confdefs.h <<\_ACEOF
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#define BX_SUPPORT_SSE2 1
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#define BX_SUPPORT_SSE 2
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_ACEOF
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elif test "$support_sse" = 1; then
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cat >>confdefs.h <<\_ACEOF
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#define BX_SUPPORT_SSE 1
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_ACEOF
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cat >>confdefs.h <<\_ACEOF
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#define BX_SUPPORT_SSE2 0
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_ACEOF
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else
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cat >>confdefs.h <<\_ACEOF
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#define BX_SUPPORT_SSE 0
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_ACEOF
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cat >>confdefs.h <<\_ACEOF
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#define BX_SUPPORT_SSE2 0
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_ACEOF
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fi
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@ -2,7 +2,7 @@ dnl // Process this file with autoconf to produce a configure script.
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AC_PREREQ(2.50)
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AC_INIT(bochs.h)
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AC_REVISION([[$Id: configure.in,v 1.162 2002-11-12 21:07:16 vruppert Exp $]])
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AC_REVISION([[$Id: configure.in,v 1.163 2002-11-13 21:00:02 sshwarts Exp $]])
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AC_CONFIG_HEADER(config.h)
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AC_CONFIG_HEADER(ltdlconf.h)
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@ -1314,14 +1314,11 @@ AC_ARG_ENABLE(sse,
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)
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if test "$support_sse" = 2; then
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AC_DEFINE(BX_SUPPORT_SSE, 1)
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AC_DEFINE(BX_SUPPORT_SSE2, 1)
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AC_DEFINE(BX_SUPPORT_SSE, 2)
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elif test "$support_sse" = 1; then
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AC_DEFINE(BX_SUPPORT_SSE, 1)
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AC_DEFINE(BX_SUPPORT_SSE2, 0)
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else
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AC_DEFINE(BX_SUPPORT_SSE, 0)
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AC_DEFINE(BX_SUPPORT_SSE2, 0)
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fi
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AC_MSG_CHECKING(for x86 debugger support)
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: access.cc,v 1.34 2002-10-24 21:05:07 bdenney Exp $
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// $Id: access.cc,v 1.35 2002-11-13 21:00:03 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1158,7 +1158,7 @@ accessOK:
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}
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE != 0
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// Some macro defs to make things cleaner for endian-ness issues.
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// The following routines access a double qword, ie 16-bytes.
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.112 2002-11-08 12:47:24 sshwarts Exp $
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// $Id: cpu.h,v 1.113 2002-11-13 21:00:04 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1274,7 +1274,7 @@ class BX_MEM_C;
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#include "cpu/i387.h"
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#if BX_SUPPORT_SSE || BX_SUPPORT_SSE2
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#if BX_SUPPORT_SSE != 0
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#include "cpu/xmm.h"
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#endif
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@ -1412,7 +1412,7 @@ union {
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i387_t the_i387;
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#if BX_SUPPORT_SSE || BX_SUPPORT_SSE2
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#if BX_SUPPORT_SSE != 0
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bx_xmm_reg_t xmm[BX_XMM_REGISTERS];
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bx_mxcsr_t mxcsr;
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#endif
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@ -2033,12 +2033,12 @@ union {
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BX_SMF void PSLLQ_PqIb(bxInstruction_c *i);
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/* MMX */
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#if BX_SUPPORT_MMX || BX_SUPPORT_SSE || BX_SUPPORT_SSE2
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#if BX_SUPPORT_MMX || BX_SUPPORT_SSE != 0
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BX_SMF void prepareMMX(void);
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BX_SMF void printMmxRegisters(void);
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#endif
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#if BX_SUPPORT_SSE || BX_SUPPORT_SSE2
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#if BX_SUPPORT_SSE != 0
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BX_SMF void prepareSSE(void);
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#endif
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@ -2722,7 +2722,7 @@ union {
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#define Write_RMW_virtual_dword(val32) write_RMW_virtual_dword(val32)
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#define Write_RMW_virtual_qword(val64) write_RMW_virtual_qword(val64)
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE != 0
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BX_SMF void readVirtualDQword(unsigned s, bx_address off, Bit8u *data);
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BX_SMF void readVirtualDQwordAligned(unsigned s, bx_address off, Bit8u *data);
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BX_SMF void writeVirtualDQword(unsigned s, bx_address off, Bit8u *data);
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@ -25,7 +25,7 @@
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_MMX || BX_SUPPORT_SSE || BX_SUPPORT_SSE2
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#if BX_SUPPORT_MMX || BX_SUPPORT_SSE != 0
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#define MMX_REGFILE ((BX_CPU_THIS_PTR the_i387).mmx)
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@ -552,7 +552,7 @@ void BX_CPU_C::MOVQ_PqQq(bxInstruction_c *i)
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/* 0F 70 */
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void BX_CPU_C::PSHUFW_PqQqIb(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareMMX();
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BxPackedMmxRegister op, result;
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@ -840,7 +840,7 @@ void BX_CPU_C::PSRLQ_PqQq(bxInstruction_c *i)
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/* 0F D4 */
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void BX_CPU_C::PADDQ_PqQq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE2
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#if BX_SUPPORT_SSE >= 2
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BX_CPU_THIS_PTR prepareMMX();
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BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
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@ -902,7 +902,7 @@ void BX_CPU_C::PMULLW_PqQq(bxInstruction_c *i)
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/* 0F D7 */
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void BX_CPU_C::PMOVMSKB_GdPRq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareMMX();
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BxPackedMmxRegister op = BX_READ_MMX_REG(i->rm());
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@ -997,7 +997,7 @@ void BX_CPU_C::PSUBUSW_PqQq(bxInstruction_c *i)
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/* 0F DA */
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void BX_CPU_C::PMINUB_PqQq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareMMX();
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BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
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@ -1122,7 +1122,7 @@ void BX_CPU_C::PADDUSW_PqQq(bxInstruction_c *i)
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/* 0F DE */
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void BX_CPU_C::PMAXUB_PqQq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareMMX();
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BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
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@ -1183,7 +1183,7 @@ void BX_CPU_C::PANDN_PqQq(bxInstruction_c *i)
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/* 0F E0 */
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void BX_CPU_C::PAVGB_PqQq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareMMX();
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BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
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@ -1304,7 +1304,7 @@ void BX_CPU_C::PSRAD_PqQq(bxInstruction_c *i)
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/* 0F E3 */
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void BX_CPU_C::PAVGW_PqQq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareMMX();
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BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
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@ -1334,7 +1334,7 @@ void BX_CPU_C::PAVGW_PqQq(bxInstruction_c *i)
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/* 0F E4 */
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void BX_CPU_C::PMULHUW_PqQq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareMMX();
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BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
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@ -1404,7 +1404,7 @@ void BX_CPU_C::PMULHW_PqQq(bxInstruction_c *i)
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/* 0F E7 */
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void BX_CPU_C::MOVNTQ_MqPq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareMMX();
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if (i->modC0()) {
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@ -1488,7 +1488,7 @@ void BX_CPU_C::PSUBSW_PqQq(bxInstruction_c *i)
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/* 0F EA */
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void BX_CPU_C::PMINSW_PqQq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareMMX();
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BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
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@ -1609,7 +1609,7 @@ void BX_CPU_C::PADDSW_PqQq(bxInstruction_c *i)
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/* 0F EE */
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void BX_CPU_C::PMAXSW_PqQq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareMMX();
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BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
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@ -1768,7 +1768,7 @@ void BX_CPU_C::PSLLQ_PqQq(bxInstruction_c *i)
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/* 0F F4 */
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void BX_CPU_C::PMULUDQ_PqQq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE2
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#if BX_SUPPORT_SSE >= 2
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BX_CPU_THIS_PTR prepareMMX();
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BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
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@ -1834,7 +1834,7 @@ void BX_CPU_C::PMADDWD_PqQq(bxInstruction_c *i)
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/* 0F F6 */
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void BX_CPU_C::PSADBW_PqQq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareMMX();
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BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
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@ -1963,7 +1963,7 @@ void BX_CPU_C::PSUBD_PqQq(bxInstruction_c *i)
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/* 0F FB */
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void BX_CPU_C::PSUBQ_PqQq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE2
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#if BX_SUPPORT_SSE >= 2
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BX_CPU_THIS_PTR prepareMMX();
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BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: proc_ctrl.cc,v 1.62 2002-11-08 20:26:12 sshwarts Exp $
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// $Id: proc_ctrl.cc,v 1.63 2002-11-13 21:00:04 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -58,7 +58,7 @@ BX_CPU_C::NOP(bxInstruction_c *i)
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void BX_CPU_C::PREFETCH(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE != 0
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BX_INSTR_PREFETCH_HINT(CPU_ID, i->nnn(), i->seg(), RMAddr(i));
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#else
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UndefinedOpcode(i);
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@ -1443,11 +1443,11 @@ BX_CPU_C::CPUID(bxInstruction_c *i)
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# if BX_SUPPORT_MMX
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features |= (1<<23); // support MMX
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# endif
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# if BX_SUPPORT_SSE
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# if BX_SUPPORT_SSE >= 1
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features |= (1<<24); // support FSAVE/FXRSTOR
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features |= (1<<25); // support SSE
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# endif
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# if BX_SUPPORT_SSE2
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# if BX_SUPPORT_SSE >= 2
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features |= (1<<26); // support SSE2
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# endif
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@ -1633,7 +1633,7 @@ BX_CPU_C::SetCR4(Bit32u val_32)
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allowMask |= (1<<5);
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#endif
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#if BX_SUPPORT_SSE || BX_SUPPORT_SSE2
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#if BX_SUPPORT_SSE != 0
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allowMask |= (1<<9); /* OSFXSR */
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#endif
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112
bochs/cpu/sse.cc
112
bochs/cpu/sse.cc
@ -24,7 +24,7 @@
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_SSE || BX_SUPPORT_SSE2
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#if BX_SUPPORT_SSE >= 1
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void BX_CPU_C::prepareSSE(void)
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{
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@ -45,7 +45,7 @@ void BX_CPU_C::prepareSSE(void)
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/* 0F AE Grp15 010 */
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void BX_CPU_C::LDMXCSR(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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read_virtual_dword(i->seg(), RMAddr(i), &BX_MXCSR_REGISTER);
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@ -60,7 +60,7 @@ void BX_CPU_C::LDMXCSR(bxInstruction_c *i)
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/* 0F AE Grp15 011 */
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void BX_CPU_C::STMXCSR(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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Bit32u mxcsr = BX_MXCSR_REGISTER & MXCSR_MASK;
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@ -73,7 +73,7 @@ void BX_CPU_C::STMXCSR(bxInstruction_c *i)
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void BX_CPU_C::FXSAVE(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_PANIC(("FXSAVE: SSE instruction still not implemented"));
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#else
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BX_INFO(("FXSAVE: SSE not supported in current configuration"));
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@ -83,7 +83,7 @@ void BX_CPU_C::FXSAVE(bxInstruction_c *i)
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void BX_CPU_C::FXRSTOR(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_PANIC(("FXRSTOR : SSE instruction still not implemented"));
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#else
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BX_INFO(("FXRSTOR: SSE not supported in current configuration"));
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@ -93,7 +93,7 @@ void BX_CPU_C::FXRSTOR(bxInstruction_c *i)
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void BX_CPU_C::MOVUPS_VpsWps(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVUPS_VpsWps: SSE instruction still not implemented"));
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@ -105,7 +105,7 @@ void BX_CPU_C::MOVUPS_VpsWps(bxInstruction_c *i)
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void BX_CPU_C::MOVSS_VssWss(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVSS_VssWss: SSE instruction still not implemented"));
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@ -117,7 +117,7 @@ void BX_CPU_C::MOVSS_VssWss(bxInstruction_c *i)
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void BX_CPU_C::MOVUPS_WpsVps(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVUPS_WpsVps: SSE instruction still not implemented"));
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@ -129,7 +129,7 @@ void BX_CPU_C::MOVUPS_WpsVps(bxInstruction_c *i)
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void BX_CPU_C::MOVSS_WssVss(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVSS_WssVss: SSE instruction still not implemented"));
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@ -141,7 +141,7 @@ void BX_CPU_C::MOVSS_WssVss(bxInstruction_c *i)
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void BX_CPU_C::MOVLPS_VpsMq(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareSSE();
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BX_PANIC(("MOVLPS_VpsMq: SSE instruction still not implemented"));
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@ -153,7 +153,7 @@ void BX_CPU_C::MOVLPS_VpsMq(bxInstruction_c *i)
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|
||||
void BX_CPU_C::MOVLPS_MqVps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MOVLPS_MqVps: SSE instruction still not implemented"));
|
||||
@ -165,7 +165,7 @@ void BX_CPU_C::MOVLPS_MqVps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::UNPCKLPS_VpsWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("UNPCKLPS_VpsWq: SSE instruction still not implemented"));
|
||||
@ -177,7 +177,7 @@ void BX_CPU_C::UNPCKLPS_VpsWq(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::UNPCKHPS_VpsWq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("UNPCKHPS_VpsWq: SSE instruction still not implemented"));
|
||||
@ -189,7 +189,7 @@ void BX_CPU_C::UNPCKHPS_VpsWq(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::MOVHPS_VpsMq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MOVHPS_VpsMq: SSE instruction still not implemented"));
|
||||
@ -201,7 +201,7 @@ void BX_CPU_C::MOVHPS_VpsMq(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::MOVHPS_MqVps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MOVHPS_MqVps: SSE instruction still not implemented"));
|
||||
@ -213,7 +213,7 @@ void BX_CPU_C::MOVHPS_MqVps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::MOVAPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MOVAPS_VpsWps: SSE instruction still not implemented"));
|
||||
@ -225,7 +225,7 @@ void BX_CPU_C::MOVAPS_VpsWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::MOVAPS_WpsVps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MOVAPS_WpsVps: SSE instruction still not implemented"));
|
||||
@ -237,7 +237,7 @@ void BX_CPU_C::MOVAPS_WpsVps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::CVTPI2PS_VpsQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTPI2PS_VpsQq: SSE instruction still not implemented"));
|
||||
@ -249,7 +249,7 @@ void BX_CPU_C::CVTPI2PS_VpsQq(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::CVTSI2SS_VssEd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTSI2SS_VssEd: SSE instruction still not implemented"));
|
||||
@ -261,7 +261,7 @@ void BX_CPU_C::CVTSI2SS_VssEd(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::MOVNTPS_MdqVps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MOVNTPS_MdqVps: SSE instruction still not implemented"));
|
||||
@ -273,7 +273,7 @@ void BX_CPU_C::MOVNTPS_MdqVps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::CVTTPS2PI_PqWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTTPS2PI_PqWps: SSE instruction still not implemented"));
|
||||
@ -285,7 +285,7 @@ void BX_CPU_C::CVTTPS2PI_PqWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::CVTTSS2SI_GdWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTTSS2SI_GdWss: SSE instruction still not implemented"));
|
||||
@ -297,7 +297,7 @@ void BX_CPU_C::CVTTSS2SI_GdWss(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::CVTPS2PI_PqWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTPS2PI_PqWps: SSE instruction still not implemented"));
|
||||
@ -309,7 +309,7 @@ void BX_CPU_C::CVTPS2PI_PqWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::CVTSS2SI_GdWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CVTSS2SI_GdWss: SSE instruction still not implemented"));
|
||||
@ -321,7 +321,7 @@ void BX_CPU_C::CVTSS2SI_GdWss(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::UCOMISS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("UCOMISS_VssWss: SSE instruction still not implemented"));
|
||||
@ -333,7 +333,7 @@ void BX_CPU_C::UCOMISS_VssWss(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::COMISS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("COMISS_VpsWps: SSE instruction still not implemented"));
|
||||
@ -345,7 +345,7 @@ void BX_CPU_C::COMISS_VpsWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::MOVMSKPS_GdVRps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MOVMSKPS_GdVRps: SSE instruction still not implemented"));
|
||||
@ -357,7 +357,7 @@ void BX_CPU_C::MOVMSKPS_GdVRps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::SQRTPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("SQRTPS_VpsWps: SSE instruction still not implemented"));
|
||||
@ -369,7 +369,7 @@ void BX_CPU_C::SQRTPS_VpsWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::SQRTSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("SQRTSS_VssWss: SSE instruction still not implemented"));
|
||||
@ -381,7 +381,7 @@ void BX_CPU_C::SQRTSS_VssWss(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::RSQRTPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("RSQRTPS_VpsWps: SSE instruction still not implemented"));
|
||||
@ -393,7 +393,7 @@ void BX_CPU_C::RSQRTPS_VpsWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::RSQRTSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("RSQRTSS_VssWss: SSE instruction still not implemented"));
|
||||
@ -405,7 +405,7 @@ void BX_CPU_C::RSQRTSS_VssWss(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::RCPPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("RCPPS_VpsWps: SSE instruction still not implemented"));
|
||||
@ -417,7 +417,7 @@ void BX_CPU_C::RCPPS_VpsWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::RCPSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("RCPSS_VssWss: SSE instruction still not implemented"));
|
||||
@ -429,7 +429,7 @@ void BX_CPU_C::RCPSS_VssWss(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::ANDPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("ANDPS_VpsWps: SSE instruction still not implemented"));
|
||||
@ -441,7 +441,7 @@ void BX_CPU_C::ANDPS_VpsWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::ANDNPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("ANDNPS_VpsWps: SSE instruction still not implemented"));
|
||||
@ -453,7 +453,7 @@ void BX_CPU_C::ANDNPS_VpsWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::ORPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("ORPS_VpsWps: SSE instruction still not implemented"));
|
||||
@ -465,7 +465,7 @@ void BX_CPU_C::ORPS_VpsWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::XORPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("XORPS_VpsWps: SSE instruction still not implemented"));
|
||||
@ -477,7 +477,7 @@ void BX_CPU_C::XORPS_VpsWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::ADDPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("ADDPS_VpsWps: SSE instruction still not implemented"));
|
||||
@ -489,7 +489,7 @@ void BX_CPU_C::ADDPS_VpsWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::ADDSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("ADDSS_VssWss: SSE instruction still not implemented"));
|
||||
@ -501,7 +501,7 @@ void BX_CPU_C::ADDSS_VssWss(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::MULPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MULPS_VpsWps: SSE instruction still not implemented"));
|
||||
@ -513,7 +513,7 @@ void BX_CPU_C::MULPS_VpsWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::MULSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MULSS_VssWss: SSE instruction still not implemented"));
|
||||
@ -525,7 +525,7 @@ void BX_CPU_C::MULSS_VssWss(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::SUBPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("SUBPS_VpsWps: SSE instruction still not implemented"));
|
||||
@ -537,7 +537,7 @@ void BX_CPU_C::SUBPS_VpsWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::SUBSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("SUBSS_VssWss: SSE instruction still not implemented"));
|
||||
@ -549,7 +549,7 @@ void BX_CPU_C::SUBSS_VssWss(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::MINPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MINPS_VpsWps: SSE instruction still not implemented"));
|
||||
@ -561,7 +561,7 @@ void BX_CPU_C::MINPS_VpsWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::MINSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MINSS_VssWss: SSE instruction still not implemented"));
|
||||
@ -573,7 +573,7 @@ void BX_CPU_C::MINSS_VssWss(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::DIVPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("DIVPS_VpsWps: SSE instruction still not implemented"));
|
||||
@ -585,7 +585,7 @@ void BX_CPU_C::DIVPS_VpsWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::DIVSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("DIVSS_VssWss: SSE instruction still not implemented"));
|
||||
@ -597,7 +597,7 @@ void BX_CPU_C::DIVSS_VssWss(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::MAXPS_VpsWps(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MAXPS_VpsWps: SSE instruction still not implemented"));
|
||||
@ -609,7 +609,7 @@ void BX_CPU_C::MAXPS_VpsWps(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::MAXSS_VssWss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("MAXSS_VssWss: SSE instruction still not implemented"));
|
||||
@ -621,7 +621,7 @@ void BX_CPU_C::MAXSS_VssWss(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::PSHUFLW_VqWqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("PSHUFLW_VqWqIb: SSE instruction still not implemented"));
|
||||
@ -633,7 +633,7 @@ void BX_CPU_C::PSHUFLW_VqWqIb(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::CMPPS_VpsWpsIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CMPPS_VpsWpsIb: SSE instruction still not implemented"));
|
||||
@ -645,7 +645,7 @@ void BX_CPU_C::CMPPS_VpsWpsIb(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::CMPSS_VssWssIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareSSE();
|
||||
|
||||
BX_PANIC(("CMPSS_VssWssIb: SSE instruction still not implemented"));
|
||||
@ -657,7 +657,7 @@ void BX_CPU_C::CMPSS_VssWssIb(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::PINSRW_PqEdIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BX_PANIC(("PINSRW_PqEdIb: SSE instruction still not implemented"));
|
||||
@ -669,7 +669,7 @@ void BX_CPU_C::PINSRW_PqEdIb(bxInstruction_c *i)
|
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void BX_CPU_C::PEXTRW_PqEdIb(bxInstruction_c *i)
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{
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#if BX_SUPPORT_SSE
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#if BX_SUPPORT_SSE >= 1
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BX_CPU_THIS_PTR prepareMMX();
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BX_PANIC(("PEXTRW_PqEdIb: SSE instruction still not implemented"));
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@ -681,7 +681,7 @@ void BX_CPU_C::PEXTRW_PqEdIb(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::SHUFPS_VpsWpsIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
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||||
#if BX_SUPPORT_SSE >= 1
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||||
BX_CPU_THIS_PTR prepareSSE();
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||||
|
||||
BX_PANIC(("SHUFPS_VpsWpsIb: SSE instruction still not implemented"));
|
||||
@ -693,7 +693,7 @@ void BX_CPU_C::SHUFPS_VpsWpsIb(bxInstruction_c *i)
|
||||
|
||||
void BX_CPU_C::MASKMOVQ_PqPRq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_SSE
|
||||
#if BX_SUPPORT_SSE >= 1
|
||||
BX_PANIC(("MASKMOVQ_PqPRq: SSE instruction still not implemented"));
|
||||
#else
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||||
BX_INFO(("MASKMOVQ_PqPRq: SSE not supported in current configuration"));
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user