mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

implemented

Browse Source 
PINSRW_VdqEdIb
PEXTRW_VdqEdIb
PINSRW_PqEdIb
PEXTRW_PqEdIb

instructions
This commit is contained in:
Stanislav Shwartsman 2002-12-02 21:24:09 +00:00
parent fa012aaa1f
commit 04c7d9301b
3 changed files with 84 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

60
bochs/cpu/mmx.cc
View File

@ -723,6 +723,66 @@ void BX_CPU_C::MOVQ_QqPq(bxInstruction_c *i)
#endif
}
/* 0F C4 */
void BX_CPU_C::PINSRW_PqEdIb(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 1
BX_CPU_THIS_PTR prepareMMX();
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn());
Bit16u op2;
/* op2 is a register or memory reference */
if (i->modC0()) {
op2 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op2);
}
Bit8u count = i->Ib() & 0x3;
switch(count) {
case 0:
MMXUW0(op1) = op2;
break;
case 1:
MMXUW1(op1) = op2;
break;
case 2:
MMXUW2(op1) = op2;
break;
case 3:
MMXUW3(op1) = op2;
break;
}
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), op1);
#else
BX_INFO(("PINSRW_PqEdIb: SSE not supported in current configuration"));
UndefinedOpcode(i);
#endif
}
/* 0F C5 */
void BX_CPU_C::PEXTRW_PqEdIb(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 1
BX_CPU_THIS_PTR prepareMMX();
BxPackedMmxRegister op = BX_READ_MMX_REG(i->rm());
Bit8u count = i->Ib() & 0x3;
Bit32u result = (Bit32u) SelectMmxWord(op, count);
BX_WRITE_32BIT_REG(i->nnn(), result);
#else
BX_INFO(("PEXTRW_PqEdIb: SSE not supported in current configuration"));
UndefinedOpcode(i);
#endif
}
/* 0F D1 */
void BX_CPU_C::PSRLW_PqQq(bxInstruction_c *i)
{

24
bochs/cpu/sse.cc
View File

@ -815,30 +815,6 @@ void BX_CPU_C::CMPSS_VssWssIb(bxInstruction_c *i)
#endif
}
void BX_CPU_C::PINSRW_PqEdIb(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 1
BX_CPU_THIS_PTR prepareMMX();
BX_PANIC(("PINSRW_PqEdIb: SSE instruction still not implemented"));
#else
BX_INFO(("PINSRW_PqEdIb: SSE not supported in current configuration"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::PEXTRW_PqEdIb(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 1
BX_CPU_THIS_PTR prepareMMX();
BX_PANIC(("PEXTRW_PqEdIb: SSE instruction still not implemented"));
#else
BX_INFO(("PEXTRW_PqEdIb: SSE not supported in current configuration"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::SHUFPS_VpsWpsIb(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 1

26
bochs/cpu/sse2.cc
View File

@ -1209,24 +1209,46 @@ void BX_CPU_C::MOVNTI_MdGd(bxInstruction_c *i)
#endif
}
/* 66 0F C4 */
void BX_CPU_C::PINSRW_VdqEdIb(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 2
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("PINSRW_VdqEdIb: SSE2 instruction still not implemented"));
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn());
Bit16u op2;
Bit8u count = i->Ib() & 0x7;
/* op2 is a register or memory reference */
if (i->modC0()) {
op2 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op2);
}
op1.xmm16u(count) = op2;
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), op1);
#else
BX_INFO(("PINSRW_VdqEdIb: SSE2 not supported in current configuration"));
UndefinedOpcode(i);
#endif
}
/* 66 0F C5 */
void BX_CPU_C::PEXTRW_VdqEdIb(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 2
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("PEXTRW_VdqEdIb: SSE2 instruction still not implemented"));
BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
Bit8u count = i->Ib() & 0x7;
Bit32u result = (Bit32u) op.xmm16u(count);
BX_WRITE_32BIT_REG(i->nnn(), result);
#else
BX_INFO(("PEXTRW_VdqEdIb: SSE2 not supported in current configuration"));
UndefinedOpcode(i);