fixed bug in floatx80_class function
mmx code optimizations
This commit is contained in:
Stanislav Shwartsman
parent
f552a1c861
commit
1706beda30
129
bochs/cpu/i387.h
129
bochs/cpu/i387.h
@ -100,89 +100,74 @@ extern "C"
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#if BX_SUPPORT_MMX
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typedef union {
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Bit8u u8;
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Bit8s s8;
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} MMX_BYTE;
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typedef union bx_packed_mmx_reg_t {
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Bit8s _sbyte[8];
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Bit16s _s16[4];
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Bit32s _s32[2];
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Bit64s _s64;
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Bit8u _ubyte[8];
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Bit16u _u16[4];
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Bit32u _u32[2];
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Bit64u _u64;
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} BxPackedMmxRegister;
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typedef union {
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Bit16u u16;
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Bit16s s16;
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struct {
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#ifdef BX_BIG_ENDIAN
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MMX_BYTE hi;
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MMX_BYTE lo;
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#define mmx64s(i) _s64
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#define mmx32s(i) _s32[1 - (i)]
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#define mmx16s(i) _s16[3 - (i)]
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#define mmxsbyte(i) _sbyte[7 - (i)]
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#define mmxubyte(i) _ubyte[7 - (i)]
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#define mmx16u(i) _u16[3 - (i)]
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#define mmx32u(i) _u32[1 - (i)]
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#define mmx64u _u64
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#else
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MMX_BYTE lo;
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MMX_BYTE hi;
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#define mmx64s(i) _s64
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#define mmx32s(i) _s32[(i)]
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#define mmx16s(i) _s16[(i)]
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#define mmxsbyte(i) _sbyte[(i)]
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#define mmxubyte(i) _ubyte[(i)]
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#define mmx16u(i) _u16[(i)]
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#define mmx32u(i) _u32[(i)]
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#define mmx64u _u64
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#endif
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} bytes;
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} MMX_WORD;
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typedef union {
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Bit32u u32;
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Bit32s s32;
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struct {
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#ifdef BX_BIG_ENDIAN
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MMX_WORD hi;
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MMX_WORD lo;
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#else
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MMX_WORD lo;
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MMX_WORD hi;
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#endif
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} words;
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} MMX_DWORD;
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/* for compatability with already written code */
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#define MMXSB0(reg) (reg.mmxsbyte(0))
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#define MMXSB1(reg) (reg.mmxsbyte(1))
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#define MMXSB2(reg) (reg.mmxsbyte(2))
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#define MMXSB3(reg) (reg.mmxsbyte(3))
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#define MMXSB4(reg) (reg.mmxsbyte(4))
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#define MMXSB5(reg) (reg.mmxsbyte(5))
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#define MMXSB6(reg) (reg.mmxsbyte(6))
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#define MMXSB7(reg) (reg.mmxsbyte(7))
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typedef union {
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Bit64u u64;
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Bit64s s64;
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struct {
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#ifdef BX_BIG_ENDIAN
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MMX_DWORD hi;
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MMX_DWORD lo;
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#else
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MMX_DWORD lo;
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MMX_DWORD hi;
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#endif
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} dwords;
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} MMX_QWORD, BxPackedMmxRegister;
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#define MMXSW0(reg) (reg.mmx16s(0))
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#define MMXSW1(reg) (reg.mmx16s(1))
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#define MMXSW2(reg) (reg.mmx16s(2))
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#define MMXSW3(reg) (reg.mmx16s(3))
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#define MMXSB0(reg) (reg.dwords.lo.words.lo.bytes.lo.s8)
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#define MMXSB1(reg) (reg.dwords.lo.words.lo.bytes.hi.s8)
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#define MMXSB2(reg) (reg.dwords.lo.words.hi.bytes.lo.s8)
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#define MMXSB3(reg) (reg.dwords.lo.words.hi.bytes.hi.s8)
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#define MMXSB4(reg) (reg.dwords.hi.words.lo.bytes.lo.s8)
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#define MMXSB5(reg) (reg.dwords.hi.words.lo.bytes.hi.s8)
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#define MMXSB6(reg) (reg.dwords.hi.words.hi.bytes.lo.s8)
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#define MMXSB7(reg) (reg.dwords.hi.words.hi.bytes.hi.s8)
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#define MMXSD0(reg) (reg.mmx32s(0))
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#define MMXSD1(reg) (reg.mmx32s(1))
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#define MMXUB0(reg) (reg.dwords.lo.words.lo.bytes.lo.u8)
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#define MMXUB1(reg) (reg.dwords.lo.words.lo.bytes.hi.u8)
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#define MMXUB2(reg) (reg.dwords.lo.words.hi.bytes.lo.u8)
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#define MMXUB3(reg) (reg.dwords.lo.words.hi.bytes.hi.u8)
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#define MMXUB4(reg) (reg.dwords.hi.words.lo.bytes.lo.u8)
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#define MMXUB5(reg) (reg.dwords.hi.words.lo.bytes.hi.u8)
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#define MMXUB6(reg) (reg.dwords.hi.words.hi.bytes.lo.u8)
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#define MMXUB7(reg) (reg.dwords.hi.words.hi.bytes.hi.u8)
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#define MMXSW0(reg) (reg.dwords.lo.words.lo.s16)
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#define MMXSW1(reg) (reg.dwords.lo.words.hi.s16)
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#define MMXSW2(reg) (reg.dwords.hi.words.lo.s16)
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#define MMXSW3(reg) (reg.dwords.hi.words.hi.s16)
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#define MMXUW0(reg) (reg.dwords.lo.words.lo.u16)
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#define MMXUW1(reg) (reg.dwords.lo.words.hi.u16)
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#define MMXUW2(reg) (reg.dwords.hi.words.lo.u16)
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#define MMXUW3(reg) (reg.dwords.hi.words.hi.u16)
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#define MMXSQ(reg) (reg.mmx64s)
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#define MMXUQ(reg) (reg.mmx64u)
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#define MMXSD0(reg) (reg.dwords.lo.s32)
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#define MMXSD1(reg) (reg.dwords.hi.s32)
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#define MMXUD0(reg) (reg.mmx32u(0))
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#define MMXUD1(reg) (reg.mmx32u(1))
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#define MMXUD0(reg) (reg.dwords.lo.u32)
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#define MMXUD1(reg) (reg.dwords.hi.u32)
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#define MMXUW0(reg) (reg.mmx16u(0))
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#define MMXUW1(reg) (reg.mmx16u(1))
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#define MMXUW2(reg) (reg.mmx16u(2))
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#define MMXUW3(reg) (reg.mmx16u(3))
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#define MMXSQ(reg) (reg.s64)
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#define MMXUQ(reg) (reg.u64)
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#define MMXUB0(reg) (reg.mmxubyte(0))
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#define MMXUB1(reg) (reg.mmxubyte(1))
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#define MMXUB2(reg) (reg.mmxubyte(2))
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#define MMXUB3(reg) (reg.mmxubyte(3))
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#define MMXUB4(reg) (reg.mmxubyte(4))
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#define MMXUB5(reg) (reg.mmxubyte(5))
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#define MMXUB6(reg) (reg.mmxubyte(6))
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#define MMXUB7(reg) (reg.mmxubyte(7))
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// Endian Host byte order Guest (x86) byte order
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// ======================================================
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@ -111,13 +111,6 @@ void BX_CPU_C::prepareFPU2MMX(void)
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#endif
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#if BX_SUPPORT_3DNOW || BX_SUPPORT_SSE >= 1
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BX_CPP_INLINE Bit16u SelectMmxWord(BxPackedMmxRegister mmx, unsigned index)
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{
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return (MMXUQ(mmx) >> ((index & 0x3) * 16)) & 0xffff;
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}
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#endif
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/* 0F 60 */
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void BX_CPU_C::PUNPCKLBW_PqQd(bxInstruction_c *i)
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{
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@ -577,10 +570,10 @@ void BX_CPU_C::PSHUFW_PqQqIb(bxInstruction_c *i)
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read_virtual_qword(i->seg(), RMAddr(i), (Bit64u *) &op);
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}
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MMXUW0(result) = SelectMmxWord(op, order);
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MMXUW1(result) = SelectMmxWord(op, order >> 2);
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MMXUW2(result) = SelectMmxWord(op, order >> 4);
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MMXUW3(result) = SelectMmxWord(op, order >> 6);
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MMXUW0(result) = op.mmx16u((order) & 0x3);
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MMXUW1(result) = op.mmx16u((order>>2) & 0x3);
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MMXUW2(result) = op.mmx16u((order>>4) & 0x3);
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MMXUW3(result) = op.mmx16u((order>>6) & 0x3);
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/* now write result back to destination */
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BX_WRITE_MMX_REG(i->nnn(), result);
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@ -770,22 +763,7 @@ void BX_CPU_C::PINSRW_PqEdIb(bxInstruction_c *i)
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read_virtual_word(i->seg(), RMAddr(i), &op2);
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}
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Bit8u count = i->Ib() & 0x3;
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switch(count) {
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case 0:
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MMXUW0(op1) = op2;
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break;
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case 1:
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MMXUW1(op1) = op2;
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break;
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case 2:
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MMXUW2(op1) = op2;
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break;
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case 3:
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MMXUW3(op1) = op2;
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break;
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}
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op1.xmm16u(i->Ib() & 0x3) = op2;
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/* now write result back to destination */
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BX_WRITE_MMX_REG(i->nnn(), op1);
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@ -802,8 +780,7 @@ void BX_CPU_C::PEXTRW_PqEdIb(bxInstruction_c *i)
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BX_CPU_THIS_PTR prepareMMX();
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BxPackedMmxRegister op = BX_READ_MMX_REG(i->rm());
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Bit8u count = i->Ib() & 0x3;
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Bit32u result = (Bit32u) SelectMmxWord(op, count);
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Bit32u result = (Bit32u) op.mmx16u(i->Ib() & 0x3);
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BX_WRITE_32BIT_REG(i->nnn(), result);
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#else
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@ -2526,7 +2526,7 @@ float_class_t floatx80_class(floatx80 a)
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int aSign = extractFloatx80Sign(a);
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if(aExp == 0x7fff) {
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if (aSig == 0)
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if (((Bit64u) (aSig<<1)) == 0)
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return (aSign) ? float_negative_inf : float_positive_inf;
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return float_NaN;
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@ -215,15 +215,15 @@ int float64_is_signaling_nan(float64);
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| Software IEC/IEEE floating-point types.
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*----------------------------------------------------------------------------*/
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#ifdef BIG_ENDIAN
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typedef struct {
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struct floatx80 { // do not allow 16-byte extension of the structure
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Bit16u exp;
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Bit64u fraction;
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} floatx80;
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} GCC_ATTRIBUTE((aligned(1), packed));
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#else
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typedef struct {
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struct floatx80 { // do not allow 16-byte extension of the structure
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Bit64u fraction;
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Bit16u exp;
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} floatx80;
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} GCC_ATTRIBUTE((aligned(1), packed));
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#endif
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/*----------------------------------------------------------------------------
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