Added P4 support to CPUID instruction
Extracted CPUIS instructions to separate file
This commit is contained in:
Stanislav Shwartsman
parent
27b8d78e2d
commit
789db2603e
@ -91,6 +91,7 @@ OBJS = \
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data_xfer16.o \
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data_xfer32.o \
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exception.o \
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cpuid.o \
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proc_ctrl.o \
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lazy_flags.o \
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stack_pro.o \
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@ -718,6 +719,20 @@ proc_ctrl.o: proc_ctrl.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
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../iodev/eth.h ../iodev/ne2k.h ../iodev/guest2host.h \
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../iodev/slowdown_timer.h ../iodev/extfpuirq.h \
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../instrument/stubs/instrument.h
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cpuid.o: cpuid.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
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../debug/debug.h ../bxversion.h ../gui/siminterface.h ../state_file.h \
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../cpu/cpu.h ../cpu/lazy_flags.h ../cpu/i387.h ../cpu/xmm.h \
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../memory/memory.h ../pc_system.h ../plugin.h ../extplugin.h \
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../gui/gui.h ../gui/textconfig.h ../gui/keymap.h ../iodev/iodev.h \
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../iodev/pci.h ../iodev/pci2isa.h ../iodev/pcivga.h ../iodev/vga.h \
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../iodev/ioapic.h ../iodev/biosdev.h ../iodev/cmos.h ../iodev/dma.h \
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../iodev/floppy.h ../iodev/harddrv.h ../iodev/cdrom.h \
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../iodev/vmware3.h ../iodev/keyboard.h ../iodev/parallel.h \
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../iodev/pic.h ../iodev/pit.h ../iodev/pit_wrap.h ../iodev/pit82c54.h \
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../iodev/virt_timer.h ../iodev/serial.h ../iodev/unmapped.h \
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../iodev/eth.h ../iodev/ne2k.h ../iodev/guest2host.h \
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../iodev/slowdown_timer.h ../iodev/extfpuirq.h \
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../instrument/stubs/instrument.h
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protect_ctrl.o: protect_ctrl.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
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../debug/debug.h ../bxversion.h ../gui/siminterface.h ../state_file.h \
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../cpu/cpu.h ../cpu/lazy_flags.h ../cpu/i387.h ../cpu/xmm.h \
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315
bochs/cpu/cpuid.cc
Executable file
315
bochs/cpu/cpuid.cc
Executable file
@ -0,0 +1,315 @@
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_X86_64==0
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// Make life easier for merging code.
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#define RAX EAX
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#define RBX EBX
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#define RCX ECX
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#define RDX EDX
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#endif
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/* Get CPU version information. */
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static Bit32u get_cpu_version_information()
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{
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Bit32u family = 0, model = 0, stepping = 0;
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Bit32u extended_model = 0;
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Bit32u extended_family = 0;
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/* ****** */
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/* i486 */
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/* ****** */
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#if BX_CPU_LEVEL == 4
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family = 4;
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#if BX_SUPPORT_FPU
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model = 1; // 486dx
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stepping = 3;
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#else
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model = 2; // 486sx
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stepping = 3;
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#endif
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/* **************** */
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/* i586 (Pentium) */
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/* **************** */
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#elif BX_CPU_LEVEL == 5
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family = 5;
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model = 1; // Pentium (60,66)
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stepping = 3;
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/* ****** */
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/* i686 */
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/* ****** */
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#elif BX_CPU_LEVEL == 6
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#if BX_SUPPORT_SSE >= 2 // Pentium 4 processor
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/*
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The model, family, and processor type for the first
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processor in the Intel Pentium 4 family is as follows:
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* Model-0000B
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* Family-1111B
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* Processor Type-00B (OEM)
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*/
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model = 0;
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family = 0x0F;
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stepping = 3;
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#if BX_SUPPORT_X86_64
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model = 2; // Hammer returns what?
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#endif
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#else // Pentium Pro/Pentium II/Pentium III processor
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family = 6;
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model = 8;
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stepping = 3;
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#endif
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#else
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BX_PANIC(("CPUID family ID not implemented for CPU LEVEL > 6"));
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#endif
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return (extended_family << 20) |
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(extended_model << 16) |
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(family << 8) |
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(model<<4) | stepping;
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}
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/* Get CPU extended feature flags. */
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static Bit32u get_extended_cpuid_features()
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{
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Bit32u features = 0; // start with none
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#if BX_SUPPORT_PNI
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features |= 0x01; // report PNI
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#endif
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return features;
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}
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/* Get CPU feature flags. Returned by CPUID functions 1 and 80000001. */
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static Bit32u get_std_cpuid_features()
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{
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Bit32u features = 0; // start with none
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// EAX: CPU Version Infromation
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// [3:0] Stepping ID
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// [7:4] Model: starts at 1
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// [11:8] Family: 4=486, 5=Pentium, 6=PPro, ...
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// [13:12] Type: 0=OEM, 1=overdrive, 2=dual cpu, 3=reserved
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// [31:14] Reserved
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// EBX:
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// [7:0] Brand ID
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// [15:8] CFLUSH cache line size (value*8 = cache line size in bytes)
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// [23:16] Number of logical processors in one physical processor
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// [31:24] Local Apic ID
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// ECX: Feature Flags::Extended
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// [0:0] PNI
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// [3:3] MONITOR/MWAIT
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// [7:7] Enchanced Intel Speedstep Technology
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// EDX: Feature Flags
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// [0:0] FPU on chip
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// [1:1] VME: Virtual-8086 Mode enhancements
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// [2:2] DE: Debug Extensions (I/O breakpoints)
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// [3:3] PSE: Page Size Extensions
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// [4:4] TSC: Time Stamp Counter
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// [5:5] MSR: RDMSR and WRMSR support
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// [6:6] PAE: Physical Address Extensions
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// [7:7] MCE: Machine Check Exception
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// [8:8] CXS: CMPXCHG8B instruction
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// [9:9] APIC: APIC on Chip
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// [10:10] Reserved
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// [11:11] SYSENTER/SYSEXIT support
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// [12:12] MTRR: Memory Type Range Reg
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// [13:13] PGE/PTE Global Bit
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// [14:14] MCA: Machine Check Architecture
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// [15:15] CMOV: Cond Mov/Cmp Instructions
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// [22:16] Reserved
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// [23:23] MMX Technology
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// [24] FXSR: FSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
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// [25] SSE: SSE Extensions
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// [26] SSE2: SSE2 Extensions
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// [28] Reserved
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// [29] TM: Therm Monitor
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// [31:30] Reserved
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#if BX_SUPPORT_FPU
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features |= 0x01;
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#endif
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#if (BX_CPU_LEVEL >= 5)
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features |= (1<< 8); // Support CMPXCHG8B instruction
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features |= (1<< 4); // implement TSC
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features |= (1<< 5); // support RDMSR/WRMSR
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#if BX_SUPPORT_MMX
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features |= (1<<23); // support MMX
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#endif
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#endif
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#if BX_CPU_LEVEL == 6
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features |= (1<<15); // Implement CMOV instructions.
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#if BX_SUPPORT_APIC
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features |= (1<< 9); // APIC on chip
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#endif
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#if BX_SUPPORT_SSE >= 1
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features |= (1<<24); // support FSAVE/FXRSTOR
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features |= (1<<25); // support SSE
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#endif
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#if BX_SUPPORT_SSE >= 2
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features |= (1<<26); // support SSE2
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#endif
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#endif
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#if BX_SUPPORT_4MEG_PAGES
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features |= (1<< 3); // Support Page-Size Extension (4M pages)
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#endif
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#if BX_SupportGlobalPages
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features |= (1<<13); // Support Global pages.
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#endif
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#if BX_SupportPAE
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features |= (1<< 6); // Support PAE.
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#endif
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#if BX_SUPPORT_SEP
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features |= (1<<11); // SYSENTER/SYSEXIT
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#endif
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return features;
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}
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void BX_CPU_C::CPUID(bxInstruction_c *i)
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{
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#if BX_SUPPORT_X86_64
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unsigned features;
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#endif
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invalidate_prefetch_q();
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#if BX_CPU_LEVEL >= 4
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switch (EAX) {
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case 0:
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// EAX: highest input value understood by CPUID
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#if BX_CPU_LEVEL <= 6
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RAX = 1; // 486 and Pentium processors
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#else
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RAX = 1; // for Pentium Pro, Pentium II, Pentium 4 processors
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// should be 2, still not implemented
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#endif
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// EBX: vendor ID string
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// EDX: vendor ID string
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// ECX: vendor ID string
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#if BX_SUPPORT_X86_64
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RBX = 0x68747541; // "Auth"
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RDX = 0x69746e65; // "enti"
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RCX = 0x444d4163; // "cAMD"
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#else
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RBX = 0x756e6547; // "Genu"
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RDX = 0x49656e69; // "ineI"
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RCX = 0x6c65746e; // "ntel"
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#endif
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break;
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case 1:
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RAX = get_cpu_version_information();
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RBX = 0; // still not implemented
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RCX = get_extended_cpuid_features ();
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RDX = get_std_cpuid_features ();
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break;
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#if 0
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#if BX_CPU_LEVEL >= 6
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case 2:
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RAX = 0; // cache and TLB information (still not implemented)
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RBX = 0; // cache and TLB information (still not implemented)
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RCX = 0; // cache and TLB information (still not implemented)
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RDX = 0; // cache and TLB information (still not implemented)
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#endif
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#endif
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// Here should be extended information for Pentum 4 processor
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// still not implemented ...
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#if BX_SUPPORT_X86_64
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// x86-64 functions
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case 0x80000000:
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// max function supported.
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RAX = 0x80000008;
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RBX = 0x68747541; // "Auth"
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RDX = 0x69746e65; // "enti"
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RCX = 0x444d4163; // "cAMD"
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break;
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case 0x80000001:
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// long mode supported.
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features = get_std_cpuid_features ();
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RAX = features;
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// Many of the bits in EDX are the same as EAX
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// [10:10] Reserved
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// [11:11] SYSCALL and SYSRET instructions
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// [18:19] Reserved
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// [20:20] No-Execute page protection
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// [21:21] Reserved
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// [22:22] AMD MMX Extensions
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// [25:28] Reserved
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// [29:29] Long Mode
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// [30:30] AMD 3DNow Extensions
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// [31:31] AMD 3DNow Intructions
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features = features & 0x0183F3FF;
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RDX = features | (1 << 29) | (1 << 11);
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RBX = 0;
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RCX = 0;
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RDX = 0; // Reserved, undefined
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break;
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case 0x80000008:
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// virtual & phys address size in low 2 bytes.
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RAX = 0x00003028;
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RBX = 0;
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RCX = 0;
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RDX = 0; // Reserved, undefined
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break;
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#endif // #if BX_SUPPORT_X86_64
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default:
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RAX = 0;
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RBX = 0;
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RCX = 0;
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RDX = 0; // Reserved, undefined
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break;
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}
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#else
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BX_PANIC(("CPUID: not available on < late 486"));
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#endif
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: proc_ctrl.cc,v 1.74 2003-08-29 21:20:52 sshwarts Exp $
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// $Id: proc_ctrl.cc,v 1.75 2003-09-26 15:32:41 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1334,213 +1334,6 @@ BX_PANIC(("LOADALL: handle CR0.val32"));
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BX_CPU_THIS_PTR idtr.base = (base_23_16 << 16) | base_15_0;
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BX_CPU_THIS_PTR idtr.limit = limit;
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#endif
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}
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/* Get CPU feature flags. Returned by CPUID functions 1 and 80000001. */
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static inline Bit32u
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get_std_cpuid_features()
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{
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Bit32u features;
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// EAX[3:0] Stepping ID
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// EAX[7:4] Model: starts at 1
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// EAX[11:8] Family: 4=486, 5=Pentium, 6=PPro
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// EAX[13:12] Type: 0=OEM,1=overdrive,2=dual cpu,3=reserved
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// EAX[31:14] Reserved
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// EBX: Reserved (0)
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// ECX: Feature Flags::Extended
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// [0:0] PNI
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// [3:3] MONITOR/MWAIT
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// [7:7] Enchanced Intel Speedstep Technology
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// EDX: Feature Flags
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// [0:0] FPU on chip
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// [1:1] VME: Virtual-8086 Mode enhancements
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// [2:2] DE: Debug Extensions (I/O breakpoints)
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// [3:3] PSE: Page Size Extensions
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// [4:4] TSC: Time Stamp Counter
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// [5:5] MSR: RDMSR and WRMSR support
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// [6:6] PAE: Physical Address Extensions
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// [7:7] MCE: Machine Check Exception
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// [8:8] CXS: CMPXCHG8B instruction
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// [9:9] APIC: APIC on Chip
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// [10:10] Reserved
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// [11:11] SYSENTER/SYSEXIT support
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// [12:12] MTRR: Memory Type Range Reg
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// [13:13] PGE/PTE Global Bit
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// [14:14] MCA: Machine Check Architecture
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// [15:15] CMOV: Cond Mov/Cmp Instructions
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// [22:16] Reserved
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// [23:23] MMX Technology
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// [24] FXSR: FSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
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// [25] SSE: SSE Extensions
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// [26] SSE2: SSE2 Extensions
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// [28] Reserved
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// [29] TM: Therm Monitor
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// [31:30] Reserved
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features = 0; // start with none
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# if BX_SUPPORT_FPU
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features |= 0x01;
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# endif
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#if (BX_CPU_LEVEL >= 5)
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features |= (1<<8); // Support CMPXCHG8B instruction
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features |= (1<<4); // implement TSC
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# if BX_SUPPORT_MMX
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features |= (1<<23); // support MMX
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# endif
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#endif
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#if BX_CPU_LEVEL == 6
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features |= (1<<15); // Implement CMOV instructions.
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# if BX_SUPPORT_APIC
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features |= (1<<9); // APIC on chip
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# endif
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# if BX_SUPPORT_SSE >= 1
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features |= (1<<24); // support FSAVE/FXRSTOR
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features |= (1<<25); // support SSE
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# endif
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# if BX_SUPPORT_SSE >= 2
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features |= (1<<26); // support SSE2
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# endif
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#endif
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#if BX_SUPPORT_4MEG_PAGES
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features |= (1<<3); // Support Page-Size Extension (4M pages)
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#endif
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#if BX_SupportGlobalPages
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features |= (1<<13); // Support Global pages.
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#endif
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#if BX_SupportPAE
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features |= (1<<6); // Support PAE.
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#endif
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#if BX_SUPPORT_X86_64
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features |= (1<<5); // AMD specific MSR's
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#endif
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#if BX_SUPPORT_SEP
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features |= (1<<11); // SYSENTER/SYSEXIT
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#endif
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return features;
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}
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void
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BX_CPU_C::CPUID(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL >= 4
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unsigned family, model, stepping;
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#if BX_SUPPORT_X86_64
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unsigned features;
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#endif
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#endif
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|
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invalidate_prefetch_q();
|
||||
|
||||
#if BX_CPU_LEVEL >= 4
|
||||
switch (EAX) {
|
||||
case 0:
|
||||
// EAX: highest input value understood by CPUID
|
||||
// EBX: vendor ID string
|
||||
// EDX: vendor ID string
|
||||
// ECX: vendor ID string
|
||||
RAX = 1; // 486 or pentium
|
||||
#if BX_SUPPORT_X86_64
|
||||
RBX = 0x68747541; // "Auth"
|
||||
RDX = 0x69746e65; // "enti"
|
||||
RCX = 0x444d4163; // "cAMD"
|
||||
#else
|
||||
RBX = 0x756e6547; // "Genu"
|
||||
RDX = 0x49656e69; // "ineI"
|
||||
RCX = 0x6c65746e; // "ntel"
|
||||
#endif
|
||||
break;
|
||||
|
||||
case 1:
|
||||
|
||||
#if BX_CPU_LEVEL == 4
|
||||
family = 4;
|
||||
# if BX_SUPPORT_FPU
|
||||
// 486dx
|
||||
model = 1;
|
||||
stepping = 3;
|
||||
# else
|
||||
// 486sx
|
||||
model = 2;
|
||||
stepping = 3;
|
||||
# endif
|
||||
|
||||
#elif BX_CPU_LEVEL == 5
|
||||
family = 5;
|
||||
model = 1; // Pentium (60,66)
|
||||
stepping = 3; // ???
|
||||
|
||||
#elif BX_CPU_LEVEL == 6
|
||||
family = 6;
|
||||
#if BX_SUPPORT_X86_64
|
||||
model = 2; // Hammer returns what?
|
||||
#else
|
||||
model = 1; // Pentium Pro
|
||||
#endif
|
||||
stepping = 3; // ???
|
||||
#else
|
||||
BX_PANIC(("CPUID: not implemented for > 6"));
|
||||
#endif
|
||||
|
||||
RAX = (family <<8) | (model<<4) | stepping;
|
||||
RBX = RCX = 0; // reserved
|
||||
#if BX_SUPPORT_PNI
|
||||
RCX = 1; // report PNI
|
||||
#endif
|
||||
RDX = get_std_cpuid_features ();
|
||||
break;
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
// x86-64 functions
|
||||
case 0x80000000:
|
||||
// max function supported.
|
||||
RAX = 0x80000008;
|
||||
RBX = 0x68747541; // "Auth"
|
||||
RDX = 0x69746e65; // "enti"
|
||||
RCX = 0x444d4163; // "cAMD"
|
||||
break;
|
||||
|
||||
case 0x80000001:
|
||||
// long mode supported.
|
||||
features = get_std_cpuid_features ();
|
||||
RAX = features;
|
||||
// Many of the bits in EDX are the same as EAX
|
||||
// [10:10] Reserved
|
||||
// [11:11] SYSCALL and SYSRET instructions
|
||||
// [18:19] Reserved
|
||||
// [20:20] No-Execute page protection
|
||||
// [21:21] Reserved
|
||||
// [22:22] AMD MMX Extensions
|
||||
// [25:28] Reserved
|
||||
// [29:29] Long Mode
|
||||
// [30:30] AMD 3DNow Extensions
|
||||
// [31:31] AMD 3DNow Intructions
|
||||
features = features & 0x0183F3FF;
|
||||
RDX = features | (1 << 29) | (1 << 11);
|
||||
RAX = RBX = RCX = 0;
|
||||
break;
|
||||
|
||||
case 0x80000008:
|
||||
// virtual & phys address size in low 2 bytes.
|
||||
RAX = 0x00003028;
|
||||
RBX = RCX = RDX = 0;
|
||||
break;
|
||||
#endif // #if BX_SUPPORT_X86_64
|
||||
|
||||
default:
|
||||
RAX = RBX = RCX = RDX = 0; // Reserved, undefined
|
||||
break;
|
||||
}
|
||||
#else
|
||||
BX_PANIC(("CPUID: not available on < late 486"));
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* misc/bximage.c
|
||||
* $Id: bxcommit.c,v 1.3 2003-06-12 13:33:16 cbothamy Exp $
|
||||
* $Id: bxcommit.c,v 1.4 2003-09-26 15:32:41 sshwarts Exp $
|
||||
*
|
||||
* Commits a redolog file in a flat file for bochs images.
|
||||
*
|
||||
@ -33,7 +33,7 @@
|
||||
#include "../iodev/harddrv.h"
|
||||
|
||||
char *EOF_ERR = "ERROR: End of input";
|
||||
char *rcsid = "$Id: bxcommit.c,v 1.3 2003-06-12 13:33:16 cbothamy Exp $";
|
||||
char *rcsid = "$Id: bxcommit.c,v 1.4 2003-09-26 15:32:41 sshwarts Exp $";
|
||||
char *divider = "========================================================================";
|
||||
|
||||
void myexit (int code)
|
||||
@ -352,7 +352,7 @@ int main()
|
||||
if (ask_string ("\nWhat is the flat image name?\n", "c.img", filename) < 0)
|
||||
fatal (EOF_ERR);
|
||||
|
||||
snprintf(tmplogname,256,"%s%s", filename,REDOLOG_EXTENSION);
|
||||
snprintf(tmplogname,256,"%s%s", filename, UNDOABLE_REDOLOG_EXTENSION);
|
||||
|
||||
if (ask_string ("\nWhat is the redolog name?\n", tmplogname, redologname) < 0)
|
||||
fatal (EOF_ERR);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user