Send #MF exception for MMX instructions if there is a pending FPU exception
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@ -152,12 +152,12 @@ typedef struct
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#ifdef BX_BIG_ENDIAN
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Bit16u aligment1, aligment2, aligment3;
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Bit16u exp; /* 4 bytes: FP register exponent,
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set to 0xffff by all MMX commands */
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set to 0xffff by all MMX instructions */
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BxPackedMmxRegister packed_mmx_register;
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#else
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BxPackedMmxRegister packed_mmx_register;
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Bit16u exp; /* 4 bytes: FP register exponent,
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set to 0xffff by all MMX commands */
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set to 0xffff by all MMX instructions */
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Bit16u aligment1, aligment2, aligment3;
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#endif
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} BxMmxRegister;
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@ -94,7 +94,7 @@ void BX_CPU_C::printMmxRegisters(void)
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{
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for(int i=0;i<8;i++) {
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BxPackedMmxRegister mm = BX_READ_MMX_REG(i);
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fprintf(stderr, "MM%d: %.16llx\n", i, MMXUQ(mm));
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fprintf(stderr, "MM%d: %lx%lx\n", i, MMXUD1(mm), MMXUD0(mm));
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}
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}
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@ -106,9 +106,13 @@ void BX_CPU_C::prepareMMX(void)
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if(BX_CPU_THIS_PTR cr0.em)
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exception(BX_UD_EXCEPTION, 0, 0);
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/* check SW_Summary bit for a pending FPU exceptions */
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if(FPU_SWD & 0x0080)
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exception(BX_MF_EXCEPTION, 0, 0);
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FPU_TWD = 0;
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FPU_TOS = 0; /* Each time an MMX instruction is */
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FPU_SWD &= 0xc7ff; /* executed, the TOS value is set to 000b */
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FPU_TOS = 0; /* reset FPU Top-Of-Stack */
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FPU_SWD &= 0xc7ff;
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}
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#endif
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@ -682,17 +686,8 @@ void BX_CPU_C::PCMPEQD_PqQq(bxInstruction_c *i)
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void BX_CPU_C::EMMS(bxInstruction_c *i)
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{
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#if BX_SUPPORT_MMX
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if(BX_CPU_THIS_PTR cr0.em)
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exception(BX_UD_EXCEPTION, 0, 0);
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if(BX_CPU_THIS_PTR cr0.ts)
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exception(BX_NM_EXCEPTION, 0, 0);
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FPU_TWD = 0xffffffff;
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FPU_TOS = 0; /* Each time an MMX instruction is */
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FPU_SWD &= 0xc7ff; /* executed, the TOS value is set to 000b */
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BX_CPU_THIS_PTR prepareMMX();
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FPU_TWD = 0xffffffff; // toDO: FPU_TWD should be 16bit
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#else
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BX_INFO(("EMMS: required MMX, use --enable-mmx option"));
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UndefinedOpcode(i);
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