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Fixed bug PSHUFW instruction

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This commit is contained in:
Stanislav Shwartsman 2002-11-15 17:02:06 +00:00
parent 1ef126611f
commit da8a2a71b1
2 changed files with 21 additions and 2 deletions
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2
bochs/cpu/mmx.cc
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@ -570,7 +570,7 @@ void BX_CPU_C::PSHUFW_PqQqIb(bxInstruction_c *i)
MMXUW0(result) = SelectMmxWord(op, order);
MMXUW1(result) = SelectMmxWord(op, order >> 2);
MMXUW2(result) = SelectMmxWord(op, order >> 4);
MMXUW3(result) = SelectMmxWord(op, order >> 5);
MMXUW3(result) = SelectMmxWord(op, order >> 6);
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), result);

21
bochs/cpu/sse2.cc
View File

@ -1090,12 +1090,31 @@ void BX_CPU_C::MOVDQU_VdqWdq(bxInstruction_c *i)
#endif
}
/* 66 0F 70 */
void BX_CPU_C::PSHUFD_VdqWdqIb(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 2
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("PSHUFD_VdqWdqIb: SSE2 instruction still not implemented"));
BxPackedXmmRegister op, result;
Bit16u order = i->Ib();
/* op is a register or memory reference */
if (i->modC0()) {
op = BX_READ_XMM_REG(i->rm());
}
else {
/* pointer, segment address pair */
readVirtualDQword(i->seg(), RMAddr(i), (Bit8u *) &op);
}
result.xmm32u(0) = op.xmm32u(order & 0x3);
result.xmm32u(1) = op.xmm32u((order >> 2) & 0x3);
result.xmm32u(2) = op.xmm32u((order >> 4) & 0x3);
result.xmm32u(3) = op.xmm32u((order >> 6) & 0x3);
/* now write result back to destination */
BX_WRITE_XMM_REG(i->nnn(), result);
#else
BX_INFO(("PSHUFD_VdqWdqIb: SSE2 not supported in current configuration"));
UndefinedOpcode(i);