From da8a2a71b11c093d4bd8595407ba1815b8dba665 Mon Sep 17 00:00:00 2001
From: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
Date: Fri, 15 Nov 2002 17:02:06 +0000
Subject: [PATCH] Fixed bug PSHUFW instruction

---
 bochs/cpu/mmx.cc  |  2 +-
 bochs/cpu/sse2.cc | 21 ++++++++++++++++++++-
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/bochs/cpu/mmx.cc b/bochs/cpu/mmx.cc
index dcf71d077..1eb3a8f7a 100644
--- a/bochs/cpu/mmx.cc
+++ b/bochs/cpu/mmx.cc
@@ -570,7 +570,7 @@ void BX_CPU_C::PSHUFW_PqQqIb(bxInstruction_c *i)
   MMXUW0(result) = SelectMmxWord(op, order);
   MMXUW1(result) = SelectMmxWord(op, order >> 2);
   MMXUW2(result) = SelectMmxWord(op, order >> 4);
-  MMXUW3(result) = SelectMmxWord(op, order >> 5);
+  MMXUW3(result) = SelectMmxWord(op, order >> 6);
 
   /* now write result back to destination */
   BX_WRITE_MMX_REG(i->nnn(), result);
diff --git a/bochs/cpu/sse2.cc b/bochs/cpu/sse2.cc
index e5d666747..a10fff04b 100644
--- a/bochs/cpu/sse2.cc
+++ b/bochs/cpu/sse2.cc
@@ -1090,12 +1090,31 @@ void BX_CPU_C::MOVDQU_VdqWdq(bxInstruction_c *i)
 #endif
 }
 
+/* 66 0F 70 */
 void BX_CPU_C::PSHUFD_VdqWdqIb(bxInstruction_c *i)
 {
 #if BX_SUPPORT_SSE >= 2
   BX_CPU_THIS_PTR prepareSSE();
 
-  BX_PANIC(("PSHUFD_VdqWdqIb: SSE2 instruction still not implemented"));
+  BxPackedXmmRegister op, result;
+  Bit16u order = i->Ib();
+
+  /* op is a register or memory reference */
+  if (i->modC0()) {
+    op = BX_READ_XMM_REG(i->rm());
+  }
+  else {
+    /* pointer, segment address pair */
+    readVirtualDQword(i->seg(), RMAddr(i), (Bit8u *) &op);
+  }
+
+  result.xmm32u(0) = op.xmm32u(order & 0x3);
+  result.xmm32u(1) = op.xmm32u((order >> 2) & 0x3);
+  result.xmm32u(2) = op.xmm32u((order >> 4) & 0x3);
+  result.xmm32u(3) = op.xmm32u((order >> 6) & 0x3);
+
+  /* now write result back to destination */
+  BX_WRITE_XMM_REG(i->nnn(), result);
 #else
   BX_INFO(("PSHUFD_VdqWdqIb: SSE2 not supported in current configuration"));
   UndefinedOpcode(i);