- apply another speedup patch from Conn Clark.
Notes from the author: Here is another one of my speed up patches. Unlike my previous speedups this one will help more platforms than just X86. It cleans up the Data Xfer instructions. Since the Data Xfer instructions are the most often executed instructions it gives a noticable boost in speed. The basic optimization technique was to eliminate intermediate variables and pass a pointer to the final destination or original source to the read_virtual_whatever and the write_virtual_whatever functions.
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: data_xfer16.cc,v 1.21 2003-03-21 13:34:24 sshwarts Exp $
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// $Id: data_xfer16.cc,v 1.22 2003-05-03 16:19:07 cbothamy Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -54,21 +54,13 @@ BX_CPU_C::XCHG_RXAX(bxInstruction_c *i)
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void
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BX_CPU_C::MOV_EEwGw(bxInstruction_c *i)
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{
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Bit16u op2_16;
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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write_virtual_word(i->seg(), RMAddr(i), &op2_16);
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write_virtual_word(i->seg(), RMAddr(i), &BX_READ_16BIT_REG(i->nnn()));
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}
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void
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BX_CPU_C::MOV_EGwGw(bxInstruction_c *i)
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{
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Bit16u op2_16;
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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BX_WRITE_16BIT_REG(i->rm(), op2_16);
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BX_WRITE_16BIT_REG(i->rm(), BX_READ_16BIT_REG(i->nnn()));
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}
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@ -76,20 +68,14 @@ BX_CPU_C::MOV_EGwGw(bxInstruction_c *i)
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BX_CPU_C::MOV_GwEGw(bxInstruction_c *i)
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{
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// 2nd modRM operand Ex, is known to be a general register Gw.
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Bit16u op2_16;
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op2_16 = BX_READ_16BIT_REG(i->rm());
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BX_WRITE_16BIT_REG(i->nnn(), op2_16);
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BX_READ_16BIT_REG(i->nnn()) = BX_READ_16BIT_REG(i->rm());
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}
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void
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BX_CPU_C::MOV_GwEEw(bxInstruction_c *i)
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{
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// 2nd modRM operand Ex, is known to be a memory operand, Ew.
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Bit16u op2_16;
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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BX_WRITE_16BIT_REG(i->nnn(), op2_16);
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read_virtual_word(i->seg(), RMAddr(i), &BX_READ_16BIT_REG(i->nnn()));
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}
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void
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@ -167,43 +153,34 @@ BX_CPU_C::LEA_GwM(bxInstruction_c *i)
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void
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BX_CPU_C::MOV_AXOw(bxInstruction_c *i)
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{
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Bit16u temp_16;
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bx_address addr;
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addr = i->Id();
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/* read from memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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read_virtual_word(i->seg(), addr, &temp_16);
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read_virtual_word(i->seg(), i->Id(), &AX);
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}
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else {
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read_virtual_word(BX_SEG_REG_DS, addr, &temp_16);
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read_virtual_word(BX_SEG_REG_DS, i->Id(), &AX);
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}
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/* write to register */
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AX = temp_16;
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}
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void
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BX_CPU_C::MOV_OwAX(bxInstruction_c *i)
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{
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Bit16u temp_16;
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bx_address addr;
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addr = i->Id();
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/* write AX to memory address */
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/* read from register */
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temp_16 = AX;
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/* write to memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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write_virtual_word(i->seg(), addr, &temp_16);
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write_virtual_word(i->seg(), i->Id(), &AX);
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}
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else {
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write_virtual_word(BX_SEG_REG_DS, addr, &temp_16);
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write_virtual_word(BX_SEG_REG_DS, i->Id(), &AX);
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}
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: data_xfer32.cc,v 1.21 2002-10-25 18:26:27 sshwarts Exp $
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// $Id: data_xfer32.cc,v 1.22 2003-05-03 16:19:07 cbothamy Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -63,21 +63,13 @@ BX_CPU_C::MOV_ERXId(bxInstruction_c *i)
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void
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BX_CPU_C::MOV_EEdGd(bxInstruction_c *i)
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{
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Bit32u op2_32;
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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write_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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write_virtual_dword(i->seg(), RMAddr(i), &BX_READ_32BIT_REG(i->nnn()));
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}
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void
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BX_CPU_C::MOV_EGdGd(bxInstruction_c *i)
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{
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Bit32u op2_32;
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
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BX_WRITE_32BIT_REGZ(i->rm(), BX_READ_32BIT_REG(i->nnn()));
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}
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@ -85,20 +77,14 @@ BX_CPU_C::MOV_EGdGd(bxInstruction_c *i)
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BX_CPU_C::MOV_GdEGd(bxInstruction_c *i)
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{
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// 2nd modRM operand Ex, is known to be a general register Gd.
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Bit32u op2_32;
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op2_32 = BX_READ_32BIT_REG(i->rm());
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BX_WRITE_32BIT_REGZ(i->nnn(), op2_32);
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BX_READ_32BIT_REG(i->nnn()) = BX_READ_32BIT_REG(i->rm());
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}
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void
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BX_CPU_C::MOV_GdEEd(bxInstruction_c *i)
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{
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// 2nd modRM operand Ex, is known to be a memory operand, Ed.
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Bit32u op2_32;
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read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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BX_WRITE_32BIT_REGZ(i->nnn(), op2_32);
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read_virtual_dword(i->seg(), RMAddr(i), &BX_READ_32BIT_REG(i->nnn()));
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}
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void
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@ -118,46 +104,36 @@ BX_CPU_C::LEA_GdM(bxInstruction_c *i)
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void
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BX_CPU_C::MOV_EAXOd(bxInstruction_c *i)
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{
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#if BX_SUPPORT_X86_64
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Bit32u temp_32;
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bx_address addr;
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addr = i->Id();
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/* read from memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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read_virtual_dword(i->seg(), addr, &temp_32);
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read_virtual_dword(i->seg(), i->Id(), &temp_32);
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}
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else {
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read_virtual_dword(BX_SEG_REG_DS, addr, &temp_32);
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read_virtual_dword(BX_SEG_REG_DS, i->Id(), &temp_32);
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}
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/* write to register */
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#if BX_SUPPORT_X86_64
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RAX = temp_32;
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#else
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EAX = temp_32;
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if (!BX_NULL_SEG_REG(i->seg())) {
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read_virtual_dword(i->seg(), i->Id(), &EAX);
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}
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else {
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read_virtual_dword(BX_SEG_REG_DS, i->Id(), &EAX);
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}
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#endif
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}
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void
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BX_CPU_C::MOV_OdEAX(bxInstruction_c *i)
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{
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Bit32u temp_32;
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bx_address addr;
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addr = i->Id();
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/* read from register */
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temp_32 = EAX;
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/* write to memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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write_virtual_dword(i->seg(), addr, &temp_32);
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write_virtual_dword(i->seg(), i->Id() , &EAX);
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}
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else {
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write_virtual_dword(BX_SEG_REG_DS, addr, &temp_32);
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write_virtual_dword(BX_SEG_REG_DS, i->Id(), &EAX);
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}
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}
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@ -323,17 +299,16 @@ BX_CPU_C::CMOV_GdEd(bxInstruction_c *i)
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BX_PANIC(("CMOV_GdEd: default case"));
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}
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if (i->modC0()) {
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op2_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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}
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if (condition) {
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BX_WRITE_32BIT_REGZ(i->nnn(), op2_32);
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}
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if (i->modC0()) {
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op2_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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}
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BX_WRITE_32BIT_REGZ(i->nnn(), op2_32);
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}
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#else
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BX_INFO(("cmov_gded called"));
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UndefinedOpcode(i);
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/////////////////////////////////////////////////////////////////////////
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// $Id: data_xfer8.cc,v 1.15 2003-04-26 10:02:02 cbothamy Exp $
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// $Id: data_xfer8.cc,v 1.16 2003-05-03 16:19:07 cbothamy Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -50,11 +50,8 @@ BX_CPU_C::MOV_RHIb(bxInstruction_c *i)
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void
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BX_CPU_C::MOV_EEbGb(bxInstruction_c *i)
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{
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Bit8u op2;
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op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
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write_virtual_byte(i->seg(), RMAddr(i), &op2);
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write_virtual_byte(i->seg(), RMAddr(i), &BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL()));
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}
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void
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@ -71,11 +68,7 @@ BX_CPU_C::MOV_EGbGb(bxInstruction_c *i)
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void
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BX_CPU_C::MOV_GbEEb(bxInstruction_c *i)
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{
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Bit8u op2;
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read_virtual_byte(i->seg(), RMAddr(i), &op2);
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BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op2);
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read_virtual_byte(i->seg(), RMAddr(i), &BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL()));
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}
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void
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void
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BX_CPU_C::MOV_ALOb(bxInstruction_c *i)
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{
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Bit8u temp_8;
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bx_address addr;
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addr = i->Id();
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/* read from memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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read_virtual_byte(i->seg(), addr, &temp_8);
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read_virtual_byte(i->seg(), i->Id(), &AL);
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}
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else {
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read_virtual_byte(BX_SEG_REG_DS, addr, &temp_8);
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read_virtual_byte(BX_SEG_REG_DS, i->Id(), &AL);
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}
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/* write to register */
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AL = temp_8;
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}
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void
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BX_CPU_C::MOV_ObAL(bxInstruction_c *i)
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{
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Bit8u temp_8;
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bx_address addr;
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addr = i->Id();
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/* read from register */
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temp_8 = AL;
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/* write to memory address */
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if (!BX_NULL_SEG_REG(i->seg())) {
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write_virtual_byte(i->seg(), addr, &temp_8);
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write_virtual_byte(i->seg(), i->Id(), &AL);
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}
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else {
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write_virtual_byte(BX_SEG_REG_DS, addr, &temp_8);
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write_virtual_byte(BX_SEG_REG_DS, i->Id(), &AL);
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}
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}
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@ -155,7 +129,6 @@ BX_CPU_C::MOV_EbIb(bxInstruction_c *i)
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BX_CPU_C::XLAT(bxInstruction_c *i)
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{
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Bit32u offset_32;
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Bit8u al;
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#if BX_CPU_LEVEL >= 3
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@ -169,12 +142,11 @@ BX_CPU_C::XLAT(bxInstruction_c *i)
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}
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if (!BX_NULL_SEG_REG(i->seg())) {
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read_virtual_byte(i->seg(), offset_32, &al);
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read_virtual_byte(i->seg(), offset_32, &AL);
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}
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else {
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read_virtual_byte(BX_SEG_REG_DS, offset_32, &al);
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read_virtual_byte(BX_SEG_REG_DS, offset_32, &AL);
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}
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AL = al;
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}
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void
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