Changes BX_PANIC to BX_INFO if Bochs behavour is exactly matches Intel docs
This commit is contained in:
Stanislav Shwartsman
parent
1e996cc329
commit
3084a41abf
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: data_xfer16.cc,v 1.23 2003-05-08 17:56:48 cbothamy Exp $
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// $Id: data_xfer16.cc,v 1.24 2003-10-04 20:48:13 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -155,7 +155,7 @@ BX_CPU_C::MOV_SwEw(bxInstruction_c *i)
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BX_CPU_C::LEA_GwM(bxInstruction_c *i)
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{
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if (i->modC0()) {
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BX_PANIC(("LEA_GvM: op2 is a register"));
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BX_INFO(("LEA_GvM: op2 is a register"));
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UndefinedOpcode(i);
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return;
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}
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@ -163,7 +163,6 @@ BX_CPU_C::LEA_GwM(bxInstruction_c *i)
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BX_WRITE_16BIT_REG(i->nnn(), (Bit16u) RMAddr(i));
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}
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void
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BX_CPU_C::MOV_AXOw(bxInstruction_c *i)
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{
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: data_xfer32.cc,v 1.23 2003-05-08 17:56:48 cbothamy Exp $
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// $Id: data_xfer32.cc,v 1.24 2003-10-04 20:48:13 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -105,7 +105,7 @@ BX_CPU_C::MOV_GdEEd(bxInstruction_c *i)
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BX_CPU_C::LEA_GdM(bxInstruction_c *i)
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{
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if (i->modC0()) {
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BX_PANIC(("LEA_GvM: op2 is a register"));
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BX_INFO(("LEA_GvM: op2 is a register"));
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UndefinedOpcode(i);
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return;
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: data_xfer64.cc,v 1.13 2002-11-19 05:47:43 bdenney Exp $
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// $Id: data_xfer64.cc,v 1.14 2003-10-04 20:48:13 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -95,7 +95,7 @@ BX_CPU_C::MOV_GqEq(bxInstruction_c *i)
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BX_CPU_C::LEA_GqM(bxInstruction_c *i)
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{
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if (i->modC0()) {
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BX_PANIC(("LEA_GvM: op2 is a register"));
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BX_INFO(("LEA_GvM: op2 is a register"));
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UndefinedOpcode(i);
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return;
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: protect_ctrl.cc,v 1.25 2003-10-04 20:22:24 sshwarts Exp $
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// $Id: protect_ctrl.cc,v 1.26 2003-10-04 20:48:13 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -716,7 +716,6 @@ BX_CPU_C::SGDT_Ms(bxInstruction_c *i)
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base_64 = BX_CPU_THIS_PTR gdtr.base;
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write_virtual_word(i->seg(), RMAddr(i), &limit_16);
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write_virtual_qword(i->seg(), RMAddr(i)+2, &base_64);
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}
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@ -730,7 +729,6 @@ BX_CPU_C::SGDT_Ms(bxInstruction_c *i)
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/* 32bit processors always write 32bits of base */
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#endif
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write_virtual_word(i->seg(), RMAddr(i), &limit_16);
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write_virtual_dword(i->seg(), RMAddr(i)+2, &base_32);
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}
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@ -764,7 +762,6 @@ BX_CPU_C::SIDT_Ms(bxInstruction_c *i)
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base_64 = BX_CPU_THIS_PTR idtr.base;
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write_virtual_word(i->seg(), RMAddr(i), &limit_16);
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write_virtual_qword(i->seg(), RMAddr(i)+2, &base_64);
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}
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@ -780,7 +777,6 @@ BX_CPU_C::SIDT_Ms(bxInstruction_c *i)
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#endif
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write_virtual_word(i->seg(), RMAddr(i), &limit_16);
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write_virtual_dword(i->seg(), RMAddr(i)+2, &base_32);
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}
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@ -794,22 +790,26 @@ BX_CPU_C::LGDT_Ms(bxInstruction_c *i)
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BX_PANIC(("LGDT_Ms: not supported on 8086!"));
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#else
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if (v8086_mode()) BX_PANIC(("protect_ctrl: v8086 mode unsupported"));
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if (v8086_mode()) {
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BX_INFO(("LGDT: not recognized in virtual-8086 mode"));
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exception(BX_GP_EXCEPTION, 0, 0);
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return;
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}
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invalidate_prefetch_q();
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if (protected_mode() && (CPL!=0)) {
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BX_PANIC(("LGDT: protected mode: CPL!=0"));
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if (!real_mode() && CPL!=0) {
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BX_INFO(("LGDT: CPL!=0 in protected mode"));
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exception(BX_GP_EXCEPTION, 0, 0);
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return;
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}
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}
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/* op1 is a register or memory reference */
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/* operand might be a register or memory reference */
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if (i->modC0()) {
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BX_PANIC(("LGDT generating exception 6"));
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BX_INFO(("LGDT: must be memory reference"));
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UndefinedOpcode(i);
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return;
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}
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}
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#if BX_CPU_LEVEL >= 3
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
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@ -817,7 +817,6 @@ BX_CPU_C::LGDT_Ms(bxInstruction_c *i)
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Bit64u base_64;
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read_virtual_word(i->seg(), RMAddr(i), &limit_16);
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read_virtual_qword(i->seg(), RMAddr(i) + 2, &base_64);
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BX_CPU_THIS_PTR gdtr.limit = limit_16;
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@ -842,13 +841,10 @@ BX_CPU_C::LGDT_Ms(bxInstruction_c *i)
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Bit8u base16_23;
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read_virtual_word(i->seg(), RMAddr(i), &limit_16);
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read_virtual_word(i->seg(), RMAddr(i) + 2, &base0_15);
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read_virtual_byte(i->seg(), RMAddr(i) + 4, &base16_23);
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/* ignore high 8 bits */
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BX_CPU_THIS_PTR gdtr.limit = limit_16;
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BX_CPU_THIS_PTR gdtr.base = (base16_23 << 16) | base0_15;
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}
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@ -864,26 +860,26 @@ BX_CPU_C::LIDT_Ms(bxInstruction_c *i)
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Bit16u limit_16;
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Bit32u base_32;
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if (v8086_mode()) BX_PANIC(("protect_ctrl: v8086 mode unsupported"));
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if (v8086_mode()) {
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BX_INFO(("LIDT: not recognized in virtual-8086 mode"));
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exception(BX_GP_EXCEPTION, 0, 0);
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return;
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}
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invalidate_prefetch_q();
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if (protected_mode()) {
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if (CPL != 0) {
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BX_PANIC(("LIDT(): CPL(%u) != 0", (unsigned) CPL));
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exception(BX_GP_EXCEPTION, 0, 0);
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return;
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}
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}
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if (!real_mode() && CPL!=0) {
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BX_INFO(("LIDT: CPL!=0 in protected mode"));
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exception(BX_GP_EXCEPTION, 0, 0);
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return;
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}
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/* op1 is a register or memory reference */
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/* operand might be a register or memory reference */
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if (i->modC0()) {
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/* undefined opcode exception */
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BX_PANIC(("LIDT generating exception 6"));
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BX_INFO(("LIDT: must be memory reference"));
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UndefinedOpcode(i);
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return;
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}
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}
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#if BX_CPU_LEVEL >= 3
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: soft_int.cc,v 1.17 2003-08-03 16:44:53 sshwarts Exp $
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// $Id: soft_int.cc,v 1.18 2003-10-04 20:48:13 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -39,7 +39,7 @@ BX_CPU_C::BOUND_GvMa(bxInstruction_c *i)
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if (i->modC0()) {
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/* undefined opcode exception */
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BX_PANIC(("bound: op2 must be mem ref"));
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BX_PANIC(("bound: op2 must be memory reference"));
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UndefinedOpcode(i);
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}
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