From 3084a41abf4633c5c25429acb13eb84eeb7602c1 Mon Sep 17 00:00:00 2001
From: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
Date: Sat, 4 Oct 2003 20:48:13 +0000
Subject: [PATCH] Changes BX_PANIC to BX_INFO if Bochs behavour is exactly
matches Intel docs
---
bochs/cpu/data_xfer16.cc | 5 ++--
bochs/cpu/data_xfer32.cc | 4 +--
bochs/cpu/data_xfer64.cc | 4 +--
bochs/cpu/protect_ctrl.cc | 54 ++++++++++++++++++---------------------
bochs/cpu/soft_int.cc | 4 +--
5 files changed, 33 insertions(+), 38 deletions(-)
diff --git a/bochs/cpu/data_xfer16.cc b/bochs/cpu/data_xfer16.cc
index 1834883b8..7dbf7b340 100644
--- a/bochs/cpu/data_xfer16.cc
+++ b/bochs/cpu/data_xfer16.cc
@@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
-// $Id: data_xfer16.cc,v 1.23 2003-05-08 17:56:48 cbothamy Exp $
+// $Id: data_xfer16.cc,v 1.24 2003-10-04 20:48:13 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@@ -155,7 +155,7 @@ BX_CPU_C::MOV_SwEw(bxInstruction_c *i)
BX_CPU_C::LEA_GwM(bxInstruction_c *i)
{
if (i->modC0()) {
- BX_PANIC(("LEA_GvM: op2 is a register"));
+ BX_INFO(("LEA_GvM: op2 is a register"));
UndefinedOpcode(i);
return;
}
@@ -163,7 +163,6 @@ BX_CPU_C::LEA_GwM(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->nnn(), (Bit16u) RMAddr(i));
}
-
void
BX_CPU_C::MOV_AXOw(bxInstruction_c *i)
{
diff --git a/bochs/cpu/data_xfer32.cc b/bochs/cpu/data_xfer32.cc
index 8300acecf..50bfd5143 100644
--- a/bochs/cpu/data_xfer32.cc
+++ b/bochs/cpu/data_xfer32.cc
@@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
-// $Id: data_xfer32.cc,v 1.23 2003-05-08 17:56:48 cbothamy Exp $
+// $Id: data_xfer32.cc,v 1.24 2003-10-04 20:48:13 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@@ -105,7 +105,7 @@ BX_CPU_C::MOV_GdEEd(bxInstruction_c *i)
BX_CPU_C::LEA_GdM(bxInstruction_c *i)
{
if (i->modC0()) {
- BX_PANIC(("LEA_GvM: op2 is a register"));
+ BX_INFO(("LEA_GvM: op2 is a register"));
UndefinedOpcode(i);
return;
}
diff --git a/bochs/cpu/data_xfer64.cc b/bochs/cpu/data_xfer64.cc
index 208df3f04..4aaf06076 100644
--- a/bochs/cpu/data_xfer64.cc
+++ b/bochs/cpu/data_xfer64.cc
@@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
-// $Id: data_xfer64.cc,v 1.13 2002-11-19 05:47:43 bdenney Exp $
+// $Id: data_xfer64.cc,v 1.14 2003-10-04 20:48:13 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@@ -95,7 +95,7 @@ BX_CPU_C::MOV_GqEq(bxInstruction_c *i)
BX_CPU_C::LEA_GqM(bxInstruction_c *i)
{
if (i->modC0()) {
- BX_PANIC(("LEA_GvM: op2 is a register"));
+ BX_INFO(("LEA_GvM: op2 is a register"));
UndefinedOpcode(i);
return;
}
diff --git a/bochs/cpu/protect_ctrl.cc b/bochs/cpu/protect_ctrl.cc
index 0b10dbfdf..cedcdbb11 100644
--- a/bochs/cpu/protect_ctrl.cc
+++ b/bochs/cpu/protect_ctrl.cc
@@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
-// $Id: protect_ctrl.cc,v 1.25 2003-10-04 20:22:24 sshwarts Exp $
+// $Id: protect_ctrl.cc,v 1.26 2003-10-04 20:48:13 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@@ -716,7 +716,6 @@ BX_CPU_C::SGDT_Ms(bxInstruction_c *i)
base_64 = BX_CPU_THIS_PTR gdtr.base;
write_virtual_word(i->seg(), RMAddr(i), &limit_16);
-
write_virtual_qword(i->seg(), RMAddr(i)+2, &base_64);
}
@@ -730,7 +729,6 @@ BX_CPU_C::SGDT_Ms(bxInstruction_c *i)
/* 32bit processors always write 32bits of base */
#endif
write_virtual_word(i->seg(), RMAddr(i), &limit_16);
-
write_virtual_dword(i->seg(), RMAddr(i)+2, &base_32);
}
@@ -764,7 +762,6 @@ BX_CPU_C::SIDT_Ms(bxInstruction_c *i)
base_64 = BX_CPU_THIS_PTR idtr.base;
write_virtual_word(i->seg(), RMAddr(i), &limit_16);
-
write_virtual_qword(i->seg(), RMAddr(i)+2, &base_64);
}
@@ -780,7 +777,6 @@ BX_CPU_C::SIDT_Ms(bxInstruction_c *i)
#endif
write_virtual_word(i->seg(), RMAddr(i), &limit_16);
-
write_virtual_dword(i->seg(), RMAddr(i)+2, &base_32);
}
@@ -794,22 +790,26 @@ BX_CPU_C::LGDT_Ms(bxInstruction_c *i)
BX_PANIC(("LGDT_Ms: not supported on 8086!"));
#else
- if (v8086_mode()) BX_PANIC(("protect_ctrl: v8086 mode unsupported"));
+ if (v8086_mode()) {
+ BX_INFO(("LGDT: not recognized in virtual-8086 mode"));
+ exception(BX_GP_EXCEPTION, 0, 0);
+ return;
+ }
invalidate_prefetch_q();
- if (protected_mode() && (CPL!=0)) {
- BX_PANIC(("LGDT: protected mode: CPL!=0"));
+ if (!real_mode() && CPL!=0) {
+ BX_INFO(("LGDT: CPL!=0 in protected mode"));
exception(BX_GP_EXCEPTION, 0, 0);
return;
- }
+ }
- /* op1 is a register or memory reference */
+ /* operand might be a register or memory reference */
if (i->modC0()) {
- BX_PANIC(("LGDT generating exception 6"));
+ BX_INFO(("LGDT: must be memory reference"));
UndefinedOpcode(i);
return;
- }
+ }
#if BX_CPU_LEVEL >= 3
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
@@ -817,7 +817,6 @@ BX_CPU_C::LGDT_Ms(bxInstruction_c *i)
Bit64u base_64;
read_virtual_word(i->seg(), RMAddr(i), &limit_16);
-
read_virtual_qword(i->seg(), RMAddr(i) + 2, &base_64);
BX_CPU_THIS_PTR gdtr.limit = limit_16;
@@ -842,13 +841,10 @@ BX_CPU_C::LGDT_Ms(bxInstruction_c *i)
Bit8u base16_23;
read_virtual_word(i->seg(), RMAddr(i), &limit_16);
-
read_virtual_word(i->seg(), RMAddr(i) + 2, &base0_15);
-
read_virtual_byte(i->seg(), RMAddr(i) + 4, &base16_23);
/* ignore high 8 bits */
-
BX_CPU_THIS_PTR gdtr.limit = limit_16;
BX_CPU_THIS_PTR gdtr.base = (base16_23 << 16) | base0_15;
}
@@ -864,26 +860,26 @@ BX_CPU_C::LIDT_Ms(bxInstruction_c *i)
Bit16u limit_16;
Bit32u base_32;
-
- if (v8086_mode()) BX_PANIC(("protect_ctrl: v8086 mode unsupported"));
+ if (v8086_mode()) {
+ BX_INFO(("LIDT: not recognized in virtual-8086 mode"));
+ exception(BX_GP_EXCEPTION, 0, 0);
+ return;
+ }
invalidate_prefetch_q();
- if (protected_mode()) {
- if (CPL != 0) {
- BX_PANIC(("LIDT(): CPL(%u) != 0", (unsigned) CPL));
- exception(BX_GP_EXCEPTION, 0, 0);
- return;
- }
- }
+ if (!real_mode() && CPL!=0) {
+ BX_INFO(("LIDT: CPL!=0 in protected mode"));
+ exception(BX_GP_EXCEPTION, 0, 0);
+ return;
+ }
- /* op1 is a register or memory reference */
+ /* operand might be a register or memory reference */
if (i->modC0()) {
- /* undefined opcode exception */
- BX_PANIC(("LIDT generating exception 6"));
+ BX_INFO(("LIDT: must be memory reference"));
UndefinedOpcode(i);
return;
- }
+ }
#if BX_CPU_LEVEL >= 3
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
diff --git a/bochs/cpu/soft_int.cc b/bochs/cpu/soft_int.cc
index 51bf05041..d7084f796 100644
--- a/bochs/cpu/soft_int.cc
+++ b/bochs/cpu/soft_int.cc
@@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
-// $Id: soft_int.cc,v 1.17 2003-08-03 16:44:53 sshwarts Exp $
+// $Id: soft_int.cc,v 1.18 2003-10-04 20:48:13 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@@ -39,7 +39,7 @@ BX_CPU_C::BOUND_GvMa(bxInstruction_c *i)
if (i->modC0()) {
/* undefined opcode exception */
- BX_PANIC(("bound: op2 must be mem ref"));
+ BX_PANIC(("bound: op2 must be memory reference"));
UndefinedOpcode(i);
}