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Leave aligment in floatx80 reg to compiler.

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CPU code no longer assume that floatx80 register is 16-byte aligned
This commit is contained in:
Stanislav Shwartsman 2004-07-02 20:24:47 +00:00
parent 8edad22893
commit cc61e5d5d5
4 changed files with 26 additions and 47 deletions
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3
bochs/cpu/3dnow.cc
View File

@ -24,8 +24,7 @@
#if BX_SUPPORT_3DNOW
static void prepare_softfloat_status_word
(float_status_t &status, int rounding_mode)
static void prepare_softfloat_status_word(float_status_t &status, int rounding_mode)
{
status.float_exception_flags = 0; // clear exceptions before execution
status.float_nan_handling_mode = float_first_operand_nan;

30
bochs/cpu/flag_ctrl.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: flag_ctrl.cc,v 1.15 2003-03-13 00:49:20 ptrumpet Exp $
// $Id: flag_ctrl.cc,v 1.16 2004-07-02 20:24:47 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
@ -158,9 +158,7 @@ BX_CPU_C::PUSHF_Fv(bxInstruction_c *i)
}
else
{
Bit16u flags16;
flags16 = read_flags();
Bit16u flags16 = read_flags();
write_virtual_word(BX_SEG_REG_SS, RSP-2, &flags16);
RSP -= 2;
}
@ -240,53 +238,49 @@ BX_CPU_C::POPF_Fv(bxInstruction_c *i)
// Protected-mode: VIP/VIF cleared, VM unaffected.
// Does this happen for 16 bit case? fixme!
flags32 &= ~( (1<<20) | (1<<19) ); // Clear VIP/VIF
}
}
else if (v8086_mode()) {
if (BX_CPU_THIS_PTR get_IOPL() < 3) {
exception(BX_GP_EXCEPTION, 0, 0);
return;
}
}
if (i->os32L()) {
pop_32(&flags32);
changeMask |= 0x240000; // ID,AC
}
}
else {
Bit16u flags16;
pop_16(&flags16);
flags32 = flags16;
}
}
// v8086-mode: VM,RF,IOPL,VIP,VIF are unaffected.
changeMask |= (1<<9); // IF
}
}
else { // Real-mode
if (i->os32L()) {
pop_32(&flags32);
changeMask |= 0x243200; // ID,AC,IOPL,IF
}
}
else { /* 16 bit opsize */
Bit16u flags16;
pop_16(&flags16);
flags32 = flags16;
changeMask |= 0x3200; // IOPL,IF
}
}
// Real-mode: VIP/VIF cleared, VM unaffected.
flags32 &= ~( (1<<20) | (1<<19) ); // Clear VIP/VIF
}
}
writeEFlags(flags32, changeMask);
}
void
BX_CPU_C::SALC(bxInstruction_c *i)
{
if ( get_CF() ) {
AL = 0xff;
}
}
else {
AL = 0x00;
}
}
}

15
bochs/cpu/sse_move.cc
View File

@ -145,8 +145,13 @@ void BX_CPU_C::FXSAVE(bxInstruction_c *i)
/* store i387 register file */
for(index=0; index < 8; index++)
{
writeVirtualDQwordAligned(i->seg(),
RMAddr(i)+index*16+32, (Bit8u *) &(BX_FPU_REG(index)));
const floatx80 &fp = BX_FPU_REG(index);
xmm.xmm64u(0) = fp.fraction;
xmm.xmm64u(1) = 0;
xmm.xmm16u(4) = fp.exp;
writeVirtualDQwordAligned(i->seg(), RMAddr(i)+index*16+32, (Bit8u *) &xmm);
}
#if BX_SUPPORT_SSE >= 1
@ -206,8 +211,8 @@ void BX_CPU_C::FXRSTOR(bxInstruction_c *i)
/* load i387 register file */
for(index=0; index < 8; index++)
{
readVirtualDQwordAligned(i->seg(),
RMAddr(i)+index*16+32, (Bit8u *) &(BX_FPU_REG(index)));
read_virtual_tword(i->seg(),
RMAddr(i)+index*16+32, &(BX_FPU_REG(index)));
}
/* FTW
@ -255,7 +260,7 @@ void BX_CPU_C::FXRSTOR(bxInstruction_c *i)
for(index = 0;index < 8; index++, twd <<= 2, tag_byte_mask <<= 1)
{
if(tag_byte & tag_byte_mask) {
floatx80 &fpu_reg = BX_FPU_REG(index);
const floatx80 &fpu_reg = BX_FPU_REG(index);
twd = FPU_tagof(fpu_reg);
}
else {

25
bochs/fpu/softfloat.h
View File

@ -256,35 +256,16 @@ int float64_is_signaling_nan(float64);
| Software IEC/IEEE floating-point types.
*----------------------------------------------------------------------------*/
// Endian Host byte order Guest (x86) byte order
// ======================================================
// Little FFFFFFFFEEAAAAAA FFFFFFFFEEAAAAAA
// Big AAAAAAEEFFFFFFFF FFFFFFFFEEAAAAAA
//
// Legend: F - fraction/mmx
// E - exponent
// A - alignment
#ifdef BX_BIG_ENDIAN
#if defined(__MWERKS__) && defined(macintosh)
#pragma options align=mac68k
#endif
struct floatx80 {
Bit32u align1;
Bit16u align2;
struct floatx80 { // leave alignment to compiler
Bit16u exp;
Bit64u fraction;
} GCC_ATTRIBUTE((aligned(16), packed));
#if defined(__MWERKS__) && defined(macintosh)
#pragma options align=reset
#endif
};
#else
struct floatx80 {
Bit64u fraction;
Bit16u exp;
Bit16u align1;
Bit32u align2;
} GCC_ATTRIBUTE((aligned(16), packed));
};
#endif
/*----------------------------------------------------------------------------