Commit Graph

1083 Commits

Author SHA1 Message Date
Aurelien Jarno
fc40787abc target-mips: implement unaligned loads using TCG
Load/store from helpers should be avoided as they are quite
inefficient. Rewrite unaligned loads instructions using TCG and
aligned loads. The number of actual loads operations to implement
an unaligned load instruction is reduced from up to 8 to 1.

Note: As we can't rely on shift by 32 or 64 undefined behaviour,
the code loads already shift by one constants.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 22:20:47 +01:00
Aurelien Jarno
18bba4dc78 target-mips: simplify load/store microMIPS helpers
load/store microMIPS helpers are reinventing the wheel. Call do_lw,
do_ll, do_sw and do_sl instead of using a macro calling the cpu_*
load/store functions.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 22:20:47 +01:00
Aurelien Jarno
3cee3050ce target-mips: optimize load operations
Only allocate t1 when needed.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 22:20:47 +01:00
Aurelien Jarno
2910c6cbaa target-mips: cleanup load/store operations
Load/store operations use macros for historical reasons. Now that there
is no point in keeping them, replace them by direct calls to qemu_ld/st.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 22:20:47 +01:00
Aurelien Jarno
5f7319cd84 target-mips: restore CPU state after an FPU exception
Rework *raise_exception*() functions so that they can be called from
other helpers, passing the return address as an argument.

Use do_raise_exception() function in update_fcr31() to correctly restore
the CPU state after an FPU exception.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 22:20:46 +01:00
Aurelien Jarno
05993cd05f target-mips: use softfloat constants when possible
softfloat already has a few constants defined, use them instead of
redefining them in target-mips.

Rename FLOAT_SNAN32 and FLOAT_SNAN64 to FP_TO_INT32_OVERFLOW and
FP_TO_INT64_OVERFLOW as even if they have the same value, they are
technically different (and defined differently in the MIPS ISA).

Remove the unused constants.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 22:20:46 +01:00
Aurelien Jarno
4cc2e5f989 target-mips: cleanup float to int conversion helpers
Instead of accessing the flags from the floating point control
register after updating it, read the softfloat flags.

This is just code cleanup and should not change the behaviour.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 22:20:46 +01:00
Aurelien Jarno
5dbe90bba7 target-mips: fix FPU exceptions
For each FPU instruction that can trigger an FPU exception, to call
call update_fcr31() after.

Remove the manual NaN assignment in case of float to float operation, as
softfloat is already taking care of that. However for float to int
operation, the value has to be changed to the MIPS one. In the cvtpw_ps
case, the two registers have to be handled separately to guarantee
a correct final value in both registers.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 22:20:46 +01:00
Aurelien Jarno
4a587b2ccb target-mips: keep softfloat exception set to 0 between instructions
Instead of clearing the softfloat exception flags before each floating
point instruction, reset them to 0 in update_fcr31() when an exception
is detected.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 22:20:46 +01:00
Aurelien Jarno
b3d6cd447d target-mips: use the softfloat floatXX_muladd functions
Use the new softfloat floatXX_muladd() functions to implement the madd,
msub, nmadd and nmsub instructions. At the same time replace the name of
the helpers by the name of the instruction, as the only reason for the
previous names was to keep the macros simple.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 22:20:45 +01:00
Aurelien Jarno
1e0e239a89 target-mips: do not save CPU state when using retranslation
When the CPU state after a possible retranslation is going to be handled
through code retranslation, we don't need to save the CPU state before.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 22:20:45 +01:00
Aurelien Jarno
4636401d99 target-mips: correctly restore btarget upon exception
When the CPU state is restored through retranslation after an exception,
btarget should also be restored.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 22:20:45 +01:00
Aurelien Jarno
40e3acc18f target-mips: remove #if defined(TARGET_MIPS64) in opcode enums
All switch() decoding instruction have a default entry, so it is possible
to have unused enum entries. Remove conditional definitions of MIPS64
opcode enums, as it only makes the code less readable.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 22:20:43 +01:00
Jia Liu
b30706dda7 target-mips: Change TODO file
Change DSP r1 & DSP r2 into microMIPS DSP encodings in TODO file.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 21:37:24 +01:00
Jia Liu
af13ae03f8 target-mips: Add ASE DSP processors
Add 74kf and mips64dspr2-generic-cpu model for test.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 21:37:20 +01:00
Jia Liu
b53371ed5d target-mips: Add ASE DSP accumulator instructions
Add MIPS ASE DSP Accumulator and DSPControl Access instructions.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 21:37:20 +01:00
Jia Liu
2669056024 target-mips: Add ASE DSP compare-pick instructions
Add MIPS ASE DSP Compare-Pick instructions.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 21:37:19 +01:00
Jia Liu
1cb6686cf9 target-mips: Add ASE DSP bit/manipulation instructions
Add MIPS ASE DSP Bit/Manipulation instructions.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 21:37:18 +01:00
Jia Liu
a22260ae38 target-mips: Add ASE DSP multiply instructions
Add MIPS ASE DSP Multiply instructions.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 21:37:18 +01:00
Jia Liu
77c5fa8b55 target-mips: Add ASE DSP GPR-based shift instructions
Add MIPS ASE DSP GPR-Based Shift instructions.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 21:37:17 +01:00
Jia Liu
461c08df75 target-mips: Add ASE DSP arithmetic instructions
Add MIPS ASE DSP Arithmetic instructions.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 21:37:16 +01:00
Jia Liu
9b1a1d68d0 target-mips: Add ASE DSP load instructions
Add MIPS ASE DSP Load instructions.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 21:33:41 +01:00
Jia Liu
e45a93e259 target-mips: Add ASE DSP branch instructions
Add MIPS ASE DSP Branch instructions.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 20:24:55 +01:00
Jia Liu
4133498f8e Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 20:24:52 +01:00
Jia Liu
853c3240c0 target-mips: Add ASE DSP resources access check
Add MIPS ASE DSP resources access check.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 20:24:06 +01:00
Jia Liu
235eb0158c target-mips: Add ASE DSP internal functions
Add internal functions using by MIPS ASE DSP instructions.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 20:24:05 +01:00
Andreas Färber
3993c6bddf cpus: Pass CPUState to [qemu_]cpu_has_work()
For target-mips also change the return type to bool.

Make include paths for cpu-qom.h consistent for alpha and unicore32.

Signed-off-by: Andreas Färber <afaerber@suse.de>
[AF: Updated new target-openrisc function accordingly]
Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
2012-10-31 04:11:37 +01:00
Richard Henderson
d73ee8a2b5 target-mips: Use TCG registers for the FPU.
With normal FP, this doesn't have much affect on the generated code,
because most of the FP operations are not CONST/PURE, and so we spill
registers in about the same frequency as the explicit load/stores.

But with Loongson multimedia instructions, which are all integral and
whose helpers are in fact CONST+PURE, this greatly improves the code.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-28 14:54:25 +01:00
Aurelien Jarno
95bf787e40 target-mips: rename helper flags
Rename helper flags to the new ones. This is purely a mechanical change,
it's possible to use better flags by looking at the helpers.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-28 14:54:24 +01:00
Avi Kivity
a8170e5e97 Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific).  Replace it with a finger-friendly,
standards conformant hwaddr.

Outstanding patchsets can be fixed up with the command

  git rebase -i --exec 'find -name "*.[ch]"
                        | xargs s/target_phys_addr_t/hwaddr/g' origin

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-10-23 08:58:25 -05:00
Andreas Färber
6f4d6b0908 target-mips: Pass MIPSCPU to mips_vpe_sleep()
Needed for moving halted field to CPUState.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:32:11 +02:00
Andreas Färber
c6679e9038 target-mips: Pass MIPSCPU to mips_tc_sleep()
Needed for changing mips_vpe_sleep() argument type to MIPSCPU.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:32:11 +02:00
Andreas Färber
b35d77d73c target-mips: Pass MIPSCPU to mips_vpe_is_wfi()
Needed for moving halted field to CPUState.
The variable name "c" is retained for MIPSCPU to leave "cpu" for CPUState.

Also change return type to bool while at it.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:32:11 +02:00
Andreas Färber
135dd63a19 target-mips: Pass MIPSCPU to mips_tc_wake()
Needed for changing mips_vpe_is_wfi() argument type to MIPSCPU.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:32:10 +02:00
Andreas Färber
81bad50ec4 target-mips: Clean up other_cpu in helper_{d,e}vpe()
Free the variable name "other_cpu" for later use for MIPSCPU.

Fix off-by-one indentation while at it.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:32:10 +02:00
Richard Henderson
fdefe51c28 Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,
add CPU_LOG_TB_OP_OPT to the condition that gates it.

This is useful for comparing optimization dumps, when the
pre-optimization dump is merely noise.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-27 21:38:50 +02:00
Richard Henderson
bd277fa196 target-mips: Implement Loongson Multimedia Instructions
Implements all of the COP2 instructions except for the S<cond>
family of comparisons.  The documentation is unclear for those.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-19 21:40:48 +02:00
Richard Henderson
fb7729e2d0 target-mips: Always evaluate debugging macro arguments
this will prevent some of the compilation errors with debugging
enabled from creeping back in.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-19 21:40:47 +02:00
Richard Henderson
9fa7748873 target-mips: Fix MIPS_DEBUG.
The macro uses the DisasContext.  Pass it around as needed.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-19 21:40:47 +02:00
Richard Henderson
e1050a7637 target-mips: Set opn in gen_ldst_multiple.
Used by MIPS_DEBUG, when enabled.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-19 21:40:47 +02:00
Blue Swirl
895c2d0435 target-mips: switch to AREG0 free mode
Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-15 17:51:13 +00:00
Maciej W. Rozycki
03e6e50177 MIPS/user: Fix reset CPU state initialization
This change updates the CPU reset sequence to use a common piece of code
that figures out CPU state flags, fixing the problem with MIPS_HFLAG_COP1X
not being set where applicable that causes floating-point MADD family
instructions (and other instructions from the MIPS IV FP subset) to trap.

 As compute_hflags is now shared between op_helper.c and translate.c, the
function is now moved to a common header.  There are no changes to this
function.

 The problem was seen with the 24Kf MIPS32r2 processor in user emulation.
The new approach prevents system and user emulation from diverging -- all
the hflags state is initialized in one place now.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-08 01:37:23 +02:00
Eric Johnson
36c6711bbe target-mips: allow microMIPS SWP and SDP to have RD equal to BASE
The microMIPS SWP and SDP instructions do not modify GPRs.  So their
behavior is well defined when RD equals BASE.  The MIPS Architecture
Verification Programs (AVPs) check that they work as expected.  This
is required for AVPs to pass.

Signed-off-by: Eric Johnson <ericj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27 22:18:02 +02:00
Eric Johnson
2e15497c5b target-mips: add privilege level check to several Cop0 instructions
The MIPS Architecture Verification Programs (AVPs) check privileged
instructions for the required privilege level.  These changes are needed
to pass the AVP suite.

Signed-off-by: Eric Johnson <ericj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27 22:17:59 +02:00
Richard Henderson
b316728836 mips-linux-user: Always support rdhwr.
The kernel will emulate this instruction if it's not supported
natively.  This insn is used for TLS, among other things, and
so is required by modern glibc.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Cc: Riku Voipio <riku.voipio@iki.fi>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27 12:17:40 +02:00
Richard Henderson
0516867450 target-mips: Streamline indexed cp1 memory addressing.
We've already eliminated both base and index being zero.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27 12:17:39 +02:00
Richard Sandiford
13d24f4972 Fix order of CVT.PS.S operands
The FS input to CVT.PS.S is the high half and FT is the low half.
tcg_gen_concat_i32_i64 takes the low half first, so the operands
were in the wrong order.

Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27 12:03:18 +02:00
Richard Sandiford
d22d728987 Fix operands of RECIP2.S and RECIP2.PS
Read the second input operand of RECIP2.S and RECIP2.PS from FT rather
than FD.  RECIP2.D is already correct.

Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27 12:03:17 +02:00
Stefan Weil
6fc97fafce target-mips: Fix some helper functions (VR54xx multiplication)
Commits b5dc7732e1 and
be24bb4f30 optimized the code
and removed the correct setting of t0. Fix this.

gcc-4.7 detected this bug because parameter arg1 was unused
but set in set_HIT0_LO and set_HI_LOT0.

Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-24 01:03:26 +02:00
Meador Inge
94159135cb target-mips: Enable access to required RDHWR hardware registers
While running in the usermode emulator all of the required*
MIPS32r2 RDHWR hardware registers should be accessible (the
Linux kernel enables access to these same registers).  Note
that these registers are still enabled when the MIPS ISA is
not release 2.  This is OK since the Linux kernel emulates
access to them when they are not available in hardware.

* There is also the ULR register which is only recommended
  for full release 2 compliance.  Incidentally, accessing
  this register in the current implementation works fine
  without flipping its access bit.

Signed-off-by: Meador Inge <meadori@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-23 17:21:05 +02:00
Nathan Froyd
f1cb0951c5 MIPS: Correct FCR0 initialization
This change addresses a problem where QEMU incorrectly traps on
floating-point MADD group instructions with SIGILL, at least while
emulating MIPS32r2 processors.  These instructions use the COP1X major
opcode and include ones like:

	madd.d	$f2,$f4,$f2,$f6

 Here's Nathan's original analysis of the problem:

"QEMU essentially does:

  d = find_cpu (cpu_string)	// get CPU definition
  fpu_init (env, d)		// initialize fpu state (init FCR0, basically)
  cpu_reset (env)

...and the cpu_reset call clears all interesting state that fpu_init
setup, then proceeds to reinitialize all the CP0 registers...but not
FCR0."

 I have verified this change with system emulation running the GDB test
suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated),
there were 55 progressions and no regressions.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-08-09 18:36:19 +00:00
Paolo Bonzini
fbe37ef3e1 build: move other target-*/ objects to nested Makefile.objs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-07 09:21:11 +02:00
Paolo Bonzini
9cdc8df314 build: move libobj-y variable to nested Makefile.objs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-07 07:19:23 +02:00
Paolo Bonzini
5e8861a036 build: move obj-TARGET-y variables to nested Makefile.objs
Also drop duplicate occurrence of device-hotplug.o.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-07 07:17:36 +02:00
Andreas Färber
b7e516ce04 Kill off cpu_state_reset()
In commit 1bba0dc932 cpu_reset()
was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()
that would operate on QOM objects.

All callers have been updated except for one in target-mips, so drop all
implementations except for the one in target-mips and move the
declaration there until MIPSCPU reset can be fully QOM'ified.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> (for mb + cris)
Acked-by: Alexander Graf <agraf@suse.de> (for ppc)
Acked-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-04 23:00:45 +02:00
Andreas Färber
30bf942d8c target-mips: Let cpu_mips_init() return MIPSCPU
Turn cpu_init macro into a static inline function returning CPUMIPSState
for backwards compatibility.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-04 23:00:43 +02:00
Andreas Färber
fca1be7cbc target-mips: Use cpu_reset() in do_interrupt()
Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-04 23:00:43 +02:00
Andreas Färber
3bd4122ef6 target-mips: Use cpu_reset() in cpu_mips_init()
Commit 0f71a7095d (target-mips: QOM'ify
CPU) hooked up cpu_state_reset() to CPUClass::reset(). Dropping the
introduction of subclasses for 1.1, due to mips_def_t the reset code
could not be QOM'ified yet, i.e. cpu_state_reset() will not forward to
CPUClass::reset().

Update cpu_mips_init() with cpu_reset() nontheless, indirectly calling
cpu_state_reset(), so that generic code can be converted to call
cpu_reset().

Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-04 23:00:43 +02:00
Richard Sandiford
d7f66b52de mips: Fix BC1ANY[24]F instructions
There's some dodgy application of De Morgan's law in the emulation
of the MIPS BC1ANY[24]F instructions: they end up branching only
if all CCs are false, rather than if one CC is.

Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests.

Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-05-19 15:51:44 +00:00
Andreas Färber
bed38e425f target-mips: Remove commented-out function declaration
There is no function cpu_mips_get_clock(), so drop it.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Stefan Weil <sw@weilnetz.de>
2012-05-12 14:17:52 +02:00
Stefan Weil
b3412b09e9 target-mips: Remove unused inline function
Function set_HILO is not needed anywhere.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
2012-05-03 07:04:48 +02:00
Blue Swirl
61d25e1548 Merge branch 'qom-cpu-rest.v1' of git://github.com/afaerber/qemu-cpu
* 'qom-cpu-rest.v1' of git://github.com/afaerber/qemu-cpu:
  Makefile: Simplify compilation of target-*/cpu.c
  target-mips: Start QOM'ifying CPU init
  target-mips: QOM'ify CPU
  target-m68k: Add QOM CPU subclasses
  target-m68k: Start QOM'ifying CPU init
  target-m68k: QOM'ify CPU reset
  target-m68k: QOM'ify CPU
  target-sh4: Start QOM'ifying CPU init
  target-sh4: QOM'ify CPU reset
  target-sh4: QOM'ify CPU
  MAINTAINERS: Downgrade target-mips and target-sh4 to Odd Fixes
  MAINTAINERS: Downgrade target-m68k to Odd Fixes
2012-05-01 09:27:53 +00:00
Andreas Färber
5b0c40f746 target-mips: Start QOM'ifying CPU init
Move code not dependent on mips_def_t from cpu_mips_init() into a
QOM initfn, as a start.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2012-04-30 11:32:13 +02:00
Andreas Färber
0f71a7095d target-mips: QOM'ify CPU
Embed CPUMIPSState as first member of QOM MIPSCPU.

Let CPUClass::reset() call cpu_state_reset() for now.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2012-04-30 11:32:13 +02:00
Andreas Färber
dda3c2ee33 target-mips: Move definition of uint_fast{8, 16}_t to osdep.h
osdep.h is included via qemu-common.h.

Prepares for use of [u]int_fast*_t types in softfloat code.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Ben Taylor <bentaylor.solx86@gmail.com>
Cc: Aurélien Jarno <aurelien@aurel32.net>
Cc: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Bernhard Walle <bernhard@bwalle.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-28 09:12:38 +00:00
Stefan Weil
b69e48a84d target-mips: Fix type cast for w64 (uintptr_t)
This changes nothing for other hosts.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
2012-04-15 21:25:17 +02:00
Blue Swirl
2050396801 Use uintptr_t for various op related functions
Use uintptr_t instead of void * or unsigned long in
several op related functions, env->mem_io_pc and
GETPC() macro.

Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14 14:23:37 +00:00
Stefan Weil
5cbdb3a34b Replace Qemu by QEMU in comments
The official spelling is QEMU.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
[blauwirbel@gmail.com: fixed comment style in hw/sun4m.c]
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-07 14:00:45 +00:00
Stefan Weil
6576b74b0b Replace Qemu by QEMU in internal documentation
The official spelling is QEMU.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-07 13:58:25 +00:00
Stefan Weil
59821ae802 target-mips: Add compiler attribute to some functions which don't return
helper_raise_exception_err does not return, nor do helper_raise_exception
and do_unaligned_access.

Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-24 13:02:43 +00:00
Andreas Färber
9349b4f9fd Rename CPUState -> CPUArchState
Scripted conversion:
  for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do
    sed -i "s/CPUState/CPUArchState/g" $file
  done

All occurrences of CPUArchState are expected to be replaced by QOM CPUState,
once all targets are QOM'ified and common fields have been extracted.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14 22:20:27 +01:00
Andreas Färber
7db13fae2c target-mips: Don't overuse CPUState
Scripted conversion:
  sed -i "s/CPUState/CPUMIPSState/g" target-mips/*.[hc]
  sed -i "s/#define CPUMIPSState/#define CPUState/" target-mips/cpu.h

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14 22:20:25 +01:00
Andreas Färber
1bba0dc932 Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).

Don't hide the parameter type behind explicit casts, use static
functions with strongly typed argument to indirect.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14 22:20:24 +01:00
Stefan Weil
93148aa5c3 Spelling fixes in comments (it's -> its)
* it's -> its (fixed for all files)
* dont -> don't (only fixed in a line which was touched by the previous fix)
* distrub -> disturb (fixed in the same line)

Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-03-08 15:22:11 +00:00
Stefan Weil
0056c093b6 target-mips: Clean includes
Remove some include statements which are not needed.

Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
2012-02-28 22:33:42 +01:00
Stefan Weil
e7d81004e4 Fix spelling in comments, documentation and messages
accidently->accidentally
annother->another
choosen->chosen
consideres->considers
decriptor->descriptor
developement->development
paramter->parameter
preceed->precede
preceeding->preceding
priviledge->privilege
propogation->propagation
substraction->subtraction
throught->through
upto->up to
usefull->useful

Fix also grammar in posix-aio-compat.c

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-12-14 11:09:44 +00:00
Dong Xu Wang
4abf79a428 fix spelling in target sub directory
Cc: Richard Henderson <rth@twiddle.net>
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Alexander Graf <agraf@suse.de>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-12-02 10:50:57 +00:00
Blue Swirl
bccd9ec5f0 softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture local
cpu_single_env hacks.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01 09:31:26 +00:00
Edgar E. Iglesias
344eecf699 mips: Support the MT TCStatus IXMT irq disable flag
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06 11:09:39 +02:00
Edgar E. Iglesias
f249412c74 mips: Add MT halting and waking of VPEs
+ some partial support for TC's.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06 11:09:39 +02:00
Edgar E. Iglesias
9e56e75624 mips: Initialize MT state at reset
Only TC0 on VPE0 is active after reset. All other VPEs and
TCs start in sleep.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06 11:09:39 +02:00
Edgar E. Iglesias
1dab005ae2 mips: Default to using one VPE and one TC.
Boards can override the setup if needed.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06 11:09:39 +02:00
Edgar E. Iglesias
ded4008881 mips: Enable VInt interrupt mode for the 34Kf
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06 11:09:38 +02:00
Edgar E. Iglesias
e428097341 mips: Correct VInt vector generation
1. The pending need to pass the Status IM gating.
2. The priority is from seven (highest prio) down to zero.
   QEMU was doing the opposite.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06 11:09:38 +02:00
Edgar E. Iglesias
bc45a67a22 mips: Correct IntCtl write mask for VInt
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06 11:09:38 +02:00
Edgar E. Iglesias
5a25ce9487 mips: Hook in more reg accesses via mttr/mftr
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06 11:09:38 +02:00
Edgar E. Iglesias
fe8dca8c3c mips: Synchronize CP0 TCSTatus, Status and EntryHi
These registers share some of their fields. Writes to these fields
should be visible through the corresponding mirror fields.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06 11:09:38 +02:00
Edgar E. Iglesias
b93bbdcd69 mips: Handle TC indexing of other VPEs
Introduce mips_cpu_map_tc() to map a global TC index into a VPE nr
and local tc index.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06 11:09:38 +02:00
Anthony Liguori
7267c0947d Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-08-20 23:01:08 -05:00
Blue Swirl
97b348e7d2 Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)
is not used in cpu_*_handle_mmu_fault() functions, remove them
and adjust callers.

Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-07 09:32:01 +00:00
Blue Swirl
3e4571724f exec.h cleanup
Move softmmu_exec.h include directives from target-*/exec.h to
target-*/op_helper.c. Move also various other stuff only used in
op_helper.c there.

Define global env in dyngen-exec.h.

For i386, move wrappers for segment and FPU helpers from user-exec.c
to op_helper.c. Implement raise_exception_err_env() to handle dynamic
CPUState. Move the function declarations to cpu.h since they can be
used outside of op_helper.c context.

LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and
env_to_regs().

ARM: make raise_exception() static.

Convert
#include "exec.h"
to
#include "cpu.h"
#include "dyngen-exec.h"
and remove now unused target-*/exec.h.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 09:41:14 +00:00
Blue Swirl
b14ef7c9ab Fix unassigned memory access handling
cea5f9a28f exposed bugs in unassigned memory
access handling. Fix them by always passing CPUState to the handlers.

Reported-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-20 21:28:08 +00:00
Blue Swirl
2b41f10e18 Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:35 +00:00
Blue Swirl
f081c76ccf Move cpu_has_work and cpu_pc_from_tb to cpu.h
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is
needed by later patches.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:31 +00:00
Blue Swirl
f3e270377a exec.h: fix coding style and change cpu_has_work to return bool
Before the next patch, fix coding style of the areas affected.

Change the type of the return value from cpu_has_work() and
qemu_cpu_has_work() to bool.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:26 +00:00
Blue Swirl
1162c041c1 cpu_loop_exit: avoid using AREG0
Make cpu_loop_exit() take a parameter for CPUState instead of relying
on global env.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:13 +00:00
Aurelien Jarno
99e43d366c target-mips: Fix warning caused by unused local variable
Fix compilation with gcc-4.6, based on a patch from Stefan
Weil <weil@mail.berlios.de>.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-15 01:00:20 +02:00
Anthony Liguori
711c21280b Merge remote-tracking branch 'stefanha/trivial-patches' into staging
Conflicts:
	cpu-all.h
2011-05-12 08:08:12 -05:00
Richard Henderson
ce0c6930cc target-mips: Do not check CPU_INTERRUPT_TIMER.
This bit is never set, therefore we should not read it either.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-05-08 16:55:23 +00:00
Stefan Weil
ff2712ba89 Fix typos in comments (interupt -> interrupt)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-05-08 10:02:17 +01:00
Stefan Weil
ebabb67a17 Fix typo in code and comments
Replace writeable -> writable

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-05-06 08:19:25 +01:00
Stefan Weil
618ba8e6a1 Remove unused function parameter from cpu_restore_state
The previous patch removed the need for parameter puc.
Is is now unused, so remove it.

Cc: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
2011-04-20 10:37:03 +02:00
Stefan Weil
e87b7cb0f0 Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commit
d2856f1ad4.
The only reason for parameter searched_pc was
a debug statement in target-i386/translate.c.

Parameter puc was needed by target-sparc until
commit d7da2a1040.

Remove searched_pc from the debug statement and remove both
parameters from the parameter list of gen_pc_load.

As the function name gen_pc_load was also misleading,
it is now called restore_state_to_opc. This new name
was suggested by Peter Maydell, thanks.

v2: Remove last parameter, too, and rename the function.

v3: Fix [] typo in target-arm/translate.c.
    Fix wrong SHA1 object name in commit message (copy+paste error).

Cc: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
2011-04-20 10:33:59 +02:00
Aurelien Jarno
6a385343e4 target-mips: clear softfpu exception state for comparison instructions
MIPS FPU instructions should start with a clean softfpu status. This
is done for the most instructions, but not for comparison ones.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17 20:32:15 +02:00
Aurelien Jarno
30a00bc142 target-mips: fix c.ps.* instructions
Contrary to cabs.ps.* instructions, c.ps.* should not compare the absolute
value of the operand, but directly the operands.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17 20:32:15 +02:00
Aurelien Jarno
353ebb7ac2 target-mips: don't hardcode softfloat exception bits
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17 20:32:15 +02:00
Aurelien Jarno
06a0e6b104 target-mips: simplify FP comparisons
As the softfloat comparison functions already test for NaN, there is no
need to always call the float*_unordered*() functions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17 20:32:15 +02:00
Aurelien Jarno
211315fb5e softfloat: rename float*_eq() into float*_eq_quiet()
float*_eq functions have a different semantics than other comparison
functions. Fix that by first renaming float*_quiet() into float*_eq_quiet().

Note that it is purely mechanical, and the behaviour should be unchanged.
That said it clearly highlight problems due to this different semantics,
they are fixed later in this patch series.

Cc: Alexander Graf <agraf@suse.de>
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17 20:32:14 +02:00
Aurelien Jarno
3a59938359 target-mips: use new float*_unordered*() functions
Use the new float*_unordered*() functions from softfloat instead of
redefining a private version.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17 20:32:14 +02:00
Stefan Weil
4b4a72e556 Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,
so the type casts of pointer to long should be replaced by
type casts of pointer to tcg_target_long (suggested by Blue Swirl).

These changes are needed for build environments where
sizeof(long) != sizeof(void *), especially for w64.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-10 00:45:16 +02:00
Stefan Weil
4ff9786c67 Fix trivial "endianness bugs"
Replace endianess -> endianness.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-03 21:42:57 +02:00
Paolo Bonzini
eda48c344f inline cpu_halted into sole caller
All implementations are now the same, and there is only one caller,
so inline the function there.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-03-13 14:44:21 +00:00
Chris Dearman
efd410373a [PATCH] [MIPS] Clear softfpu exception state for round, trunc, ceil and floor
MIPS FPU instructions should start with a clean softfpu status. This
is done for the arithmetic operations and cvt instructions, but not
for round, trunc, ceil and floor.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-09 19:45:24 +01:00
Aurelien Jarno
b835e919f0 target-mips: fix save_cpu_state() calls
The rule is:
- don't save PC if the exception is only triggered by softmmu.
- save PC if the exception can be triggered by an helper.

Fix a 64-bit kernel crash when loading modules.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-24 20:52:04 +01:00
Edgar E. Iglesias
5580722456 mips: Break TBs after mfc0_count
Break the TB after reading the count register. This makes it
possible to take timer interrupts immediately after a read of
a possibly expired timer.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-01-18 12:32:46 +01:00
Peter Maydell
185698715d softfloat: Rename float*_is_nan() functions to float*_is_quiet_nan()
The softfloat functions float*_is_nan() were badly misnamed,
because they return true only for quiet NaNs, not for all NaNs.
Rename them to float*_is_quiet_nan() to more accurately reflect
what they do.

This change was produced by:
 perl -p -i -e 's/_is_nan/_is_quiet_nan/g' $(git grep -l is_nan)
(with the results manually checked.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-02 11:15:25 +01:00
Aurelien Jarno
4cdc1cd137 target-mips: fix host CPU consumption when guest is idle
When the CPU is in wait state, do not wake-up if an interrupt can't be
taken. This avoid host CPU running at 100% if a device (e.g. timer) has
an interrupt line left enabled.

Also factorize code to check if interrupts are enabled in
cpu_mips_hw_interrupts_pending().

Based on a patch from Edgar E. Iglesias <edgar.iglesias@gmail.com>

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-12-27 00:58:06 +01:00
Nathan Froyd
9ed5726c04 target-mips: fix translation of MT instructions
The translation of dmt/emt/dvpe/evpe was doing the moral equivalent of:

  int x;
  ...		/* no initialization of x */
  x = f (x);

which confused later bits of TCG rather badly, leading to crashes.

Fix the helpers to only return results (those instructions have no
inputs), and fix the translation code accordingly.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-22 11:14:10 +01:00
Stefan Weil
9a78eead0c target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
* target-i386/helper.c
* target-mips/translate.c
* target-ppc/translate.c

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-30 08:01:59 +00:00
Blue Swirl
2abf314ddd mips: avoid write only variables
Compiling with GCC 4.6.0 20100925 produced a lot of warnings like:
/src/qemu/target-mips/translate.c: In function 'gen_ld':
/src/qemu/target-mips/translate.c:1039:17: error: variable 'opn' set but not used [-Werror=unused-but-set-variable]

Fix by adding a dummy cast so that the variable is not unused.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-13 18:43:21 +00:00
Blue Swirl
1c7242da85 MIPS: fix yield handling
The parameter for yield should be handled as a signed integer
for the comparisons to have any effect.

This also avoids a gcc warning with -Wtype-limits.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-09-18 05:53:15 +00:00
Edgar E. Iglesias
138afb024b mips: Add support for VInt and VEIC irq modes
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-08-06 12:21:16 +02:00
Hervé Poussineau
671b0f368b Correctly identify multiple cpus in SMP systems
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-31 17:14:52 +02:00
Hervé Poussineau
cf7c00d5c6 Remove unused constant
Remove unused constant MIPS_FCR0

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-31 17:14:51 +02:00
Aurelien Jarno
5dc5d9f055 mips: more fixes to the MIPS interrupt glue logic
Commit 36388314fe moved most of the
interrupt logic to cpu-exec.c. Remove the remaining useless code
and fix software interrupts.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Edgar E. Iglesias <edgar@axis.com>
Tested-by: Edgar E. Iglesias <edgar@axis.com>
2010-07-25 16:54:02 +02:00
Edgar E. Iglesias
36388314fe mips: Correct MIPS interrupt glue logic for icount
When hw interrupt pending bits in CP0_Cause are set, the CPU should
see the hw interrupt line as active. The CPU may or may not take the
interrupt based on internal state (global irq mask etc) but the glue
logic shouldn't care.

This fixes MIPS external hw interrupts in combination with -icount.

Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-07-24 13:40:05 +02:00
Aurelien Jarno
3fc00a7bde target-mips: fix xtlb exception for loongson
Loongson 2E and 2F use the same entry for xtlb and tlb exception, at
offset 0x000.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-17 16:13:12 +02:00
Aurelien Jarno
161f85e6b1 target-mips: add loongson 2E & 2F integer instructions
This patch adds support for loongson 2E & 2F instructions. They are the
same instructions, but differ by the opcode encoding.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-11 10:24:31 +02:00
Paolo Bonzini
a88790a14f remove exec-all.h inclusion from cpu.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 09:48:24 +03:00
Paolo Bonzini
10eb0cc03c move cpu_pc_from_tb to target-*/exec.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 09:48:12 +03:00
Paolo Bonzini
83dae09588 remove unused stuff from */exec.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 06:47:13 +00:00
Aurelien Jarno
afa88c3ae5 target-mips: add Loongson support prefetch
Loongson CPU uses a load to zero register for prefetch.
Emulate it as a NOP.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01 23:45:28 +02:00
Aurelien Jarno
5c13fdfd03 target-mips: split load and store
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01 07:48:17 +02:00
Aurelien Jarno
6fbab86925 target-mips: fix DINSU instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-30 20:00:31 +02:00
Aurelien Jarno
aa8f40090a target-mips: enable movn/movz on loongson 2E & 2F
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-29 23:26:34 +02:00
Huacai Chen
5bc6fba851 MIPS: Initial support of fulong mini pc (CPU definition)
Signed-off-by: Huacai Chen <zltjiangshi@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-29 23:07:52 +02:00
Stefan Weil
3308759844 target-mips: Fix compilation
TCGv t1 needs tcg_temp_free instead of tcg_temp_free_i32.

Cc: Nathan Froyd <froydnj@codesourcery.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 23:37:36 +02:00
Nathan Froyd
bbfa8f72e9 target-mips: add microMIPS exception handler support
Unlike MIPS16, microMIPS lets you choose the ISA mode for your exception
handlers.  The ISA mode is selectable via a user-writable CP0.Config3
flag.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:51 +02:00
Nathan Froyd
3c824109da target-mips: microMIPS ASE support
Add instruction decoding for the microMIPS ASE.  All we do is decode and
then forward to the existing gen_* routines.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:50 +02:00
Nathan Froyd
620e48f663 target-mips: mips16 cleanups
Change code handling mips16-specific branches to use ISA-neutral special
opcodes.  Since there are several places where the delay slot
requirements for microMIPS branches differ from mips16 branches, using
opcodes is easier than checking hflags, then checking mips16
vs. microMIPS.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:50 +02:00
Nathan Froyd
8153667c71 target-mips: refactor c{, abs}.cond.fmt insns
Move all knowledge about coprocessor-checking and register numbering
into the gen_cmp* helper functions.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:50 +02:00
Aurelien Jarno
e459440a89 target-mips: move FP FMT comments closer to the definitions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:50 +02:00
Nathan Froyd
bf4120adaa target-mips: define constants for magic numbers
Add FMT_* constants for the floating-point format field in opcodes and
tweak a few places to use them.  Add enums for various invocations of
FOP and tweak gen_farith and its lone caller accordingly.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:50 +02:00
Nathan Froyd
26ebe46848 target-mips: break out [ls][wd]c1 and rdhwr insn generation
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-08 19:15:08 +02:00
Richard Henderson
564856bb97 target-mips: Remove duplicate CPU log.
Logging for -d cpu is done in generic code.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-05 12:20:05 +02:00
Stefan Weil
2a5612e6a3 target-mips: Fix format specifiers for fpu_fprintf
In the previous patch which introduced fprintf_function to
allow parameter checking by gcc some compiler warnings
remained unfixed.

These warnings are fixed here.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-09 21:53:23 +02:00
Stefan Weil
a7200c9f98 target-mips: Fix one more format specifier for cpu_fprintf
env->bcond must be printed using TARGET_FMT_ld.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:46:57 +02:00
Paolo Bonzini
1a7ff92218 remove TARGET_* defines from translate-all.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:34:12 +02:00
Paul Brook
d4c430a80f Large page TLB flush
QEMU uses a fixed page size for the CPU TLB.  If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate
all entries covered by the large page.  However the address used to
invalidate the entry may not be present in the QEMU TLB, so we do not
know which regions to clear.

Implementing a full vaiable size TLB is hard and slow, so just keep a
simple address/mask pair to record which addresses may have been mapped by
large pages.  If the guest invalidates this region then flush the
whole TLB.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-17 02:44:41 +00:00
Aurelien Jarno
30724e758a target-mips: update address space definitions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 11:35:55 +01:00
Paul Brook
3c7b48b74c Target specific usermode cleanup
Disable various target specific code that is only relevant to system emulation.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:44:24 +00:00
Paul Brook
4fcc562bff Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:34:25 +00:00
Richard Henderson
5270589032 Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.

Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other
than Alpha.  This will be used for page_find_alloc, which is
supposed to be using virtual addresses in the first place.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2010-03-12 16:28:24 +00:00
Aurelien Jarno
deb4203dc9 target-mips: use newer logical ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-04 17:42:03 +01:00
Aurelien Jarno
e68dd28fd7 target-mips: use setcond when possible
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-02 23:16:56 +01:00
Nathan Froyd
3399e30f56 target-mips: fix ROTR and DROTR by zero
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23 19:47:25 +01:00
Nathan Froyd
c2c65dab45 target-mips: fix CpU exception for coprocessor 0
When we signal a CpU exception for coprocessor 0, we should indicate
that it's for coprocessor 0 instead of coprocessor 1.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23 19:47:24 +01:00
Aurelien Jarno
6462bfcded target-mips: remove useless sign extension
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23 19:47:24 +01:00
Aurelien Jarno
c36bbb28ad target-mips: don't call cpu_loop_exit() from helper.c
In helper.c AREG0 may not correspond do env, so it's not possible to
call cpu_loop_exit() here. Call it from op_helper.c instead.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06 17:23:33 +01:00
Paolo Bonzini
49a945a3c0 kill regs_to_env and env_to_regs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-19 16:31:02 -06:00
Stefan Weil
ab3aee26c4 target-mips: No MIPS16 support for 4Kc, 4KEc cores
Fix regression introduced by d19954f46d.

4Kc and 4KEc don't support MIPS16.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-17 00:28:58 +01:00
Stefan Weil
73642f5bdb target-mips: 4Kc, 4KEc cores do not support MIPS16
4Kc, 4KEc cores do not support MIPS16, so not only the
CP0_Config1 had to be fixed (see previous patch),
but also MIPS16 instructions must not be executed.

(Hint from Nathan Froyd, thanks).

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-16 18:20:19 +01:00
Nathan Froyd
91a7593526 target-mips: fix user-mode emulation startup
Running programs with the MIPS user-mode emulator fails during dynamic
loading, as floating-point instructions are not enabled in in
env->hflags.  Move the code for doing so from fpu_init to cpu_reset so
the MIPS_HFLAG_{FPU,F64} setting doesn't get clobbered by cpu_reset
setting env->hflags to MIPS_HFLAG_UM.

The same end can be achieved by swapping the ordering of fpu_init and
cpu_reset in cpu_mips_init, but it seemed better to consolidate the
CONFIG_USER_ONLY code into a single location.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 21:01:33 +01:00
Nathan Froyd
d19954f46d target-mips: set Config1.CA for MIPS16-aware CPUs
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:20 +01:00
Nathan Froyd
9da53be7ea target-mips: add copyright notice for mips16 work
Also cross off mips16 ASE in TODO.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:20 +01:00
Nathan Froyd
364d48314a target-mips: add mips16 instruction decoding
There's no good way to add this incrementally, so we do it all at once.
The only changes to shared code are in handle_delay_slot.  We need to
flip ISAMode when doing a jump-and-exchange.  We also need to set
ISAMode the low bit of the target address for jump-to-register.

Also, since we're now adding bits that can be in MIPS_HFLAG_BMASK_EXT,
make sure we use MIPS_HFLAG_BMASK_BASE in the places where we just want
basic information about a branch.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:20 +01:00
Nathan Froyd
6ea219d019 target-mips: add enums for MIPS16 opcodes
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:20 +01:00
Nathan Froyd
c960206137 target-mips: split out delay slot handling
Move delay slot handling to common code whose invocation can be
controlled from gen_intermediate_code_internal.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Nathan Froyd
662d748516 target-mips: add gen_base_offset_addr
This is a common pattern in existing code.  We'll also use it to
implement the mips16 SAVE/RESTORE instructions.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Nathan Froyd
7dca4ad050 target-mips: make gen_compute_branch 16/32-bit-aware
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Nathan Froyd
ea63e2c358 target-mips: move ROTR and ROTRV inside gen_shift_{imm, }
It's easier to implement mips16 shift instructions if we're not
examining the opcode inside gen_shift_{imm,}.  So move ROTR and ROTRV
and do the special-case handling of SRL and SRLV inside decode_opc.
Likewise for their 64-bit counterparts.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Nathan Froyd
32188a03da target-mips: change interrupt bits to be mips16-aware
We need to stash the operating mode into the low bit of the error PC and
restore it on return from interrupts.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Nathan Froyd
79ef2c4cdb target-mips: add new HFLAGs for JALX and 16/32-bit delay slots
We create separate masks for the "basic" branch hflags and the
"extended" branch hflags and define MIPS_HFLAG_BMASK as the logical or
of those two.  This is done to avoid churning the codebase in lots of
different places.

We also make the execution mode an hflag under MIPS_HFLAG_TMASK

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Aurelien Jarno
e7139c440c target-mips: use physical address in lladdr
Currently the ll/sc instructions use the virtual address in both
user and system mode. Use the physical address insteead in system
mode.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30 16:18:28 +01:00
Aurelien Jarno
25b91e32e0 target-mips: add a function to do virtual -> physical translations
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30 16:10:04 +01:00
Aurelien Jarno
1147e18994 target-mips: split code raising MMU exception in a separate function
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30 16:10:00 +01:00
Aurelien Jarno
0ae430454c target-mips: factorize load/store code in op_helper.c
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30 16:06:25 +01:00
Aurelien Jarno
60c9af07aa target-mips: fix physical address type in MMU functions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22 14:37:04 +01:00
Aurelien Jarno
2a6e32dd46 target-mips: make CP0_LLAddr register CPU dependent
Depending on the CPU, CP0_LLAddr is either read-only or read-write,
and the returned value can be shifted by a variable amount of bits.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
2009-11-22 14:12:19 +01:00
Aurelien Jarno
5499b6ffac target-mips: rename CP0_LLAddr into lladdr
The variable CP0_LLAddr represent the full lladdr, not the actual
register value, which is only part of this value and depends on the
CPU.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22 14:12:13 +01:00
Aurelien Jarno
31e3104fdb target-mips: fix indentation
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-14 13:10:00 +01:00
Blue Swirl
51cc2e783a mips: fix cpu_reset memory leak
Remove cpu_mips_register()
- move mmu_init(), fpu_init() and mvp_init() into cpu_mips_init()
- move the other parts in cpu_mips_init()

Reported-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-14 02:25:52 +01:00
Anthony Liguori
c227f0995e Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b72.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01 16:12:16 -05:00
malc
99a0949b72 Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <av1474@comtv.ru>
2009-10-01 22:45:02 +04:00
Aurelien Jarno
941694d09a target-mips: make sure constants are in the second argument
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-30 23:12:51 +02:00
Stefan Weil
a0d700e43b mips: Fix spelling in comment
inofficial -> unofficial

Thanks to Blue Swirl.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-30 19:07:15 +00:00
Michael S. Tsirkin
58caed6dda target-mips: unmatched brackets in if 0
Fix unmatched braket in commented out code

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-30 18:45:50 +00:00
Aurelien Jarno
618b0fe9ab target-mips: log instructions start in TCG code
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-28 13:03:30 +02:00
Aurelien Jarno
d42320c26a target-mips: remove MAX_OP_PER_INSTR workaround
Now that MAX_OP_PER_INSTR has been increased to a safer value, removed
the target-mips specific workaround.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-23 09:25:03 +02:00
Blue Swirl
6f4fc3679c Add 'static' to please Sparse
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-21 18:39:26 +00:00
Nathan Froyd
7b270ef2a3 target-mips: fix single-stepping
Single-stepping branches on MIPS didn't work right, because the
generation of EXCP_DEBUG happened after the generation of the code to
exit the current TB.  That is, given the code:

    bne v0,v1,target
    nop
    ...
  target:
    addu v0,v0,v1
  1:

when you single-stepped through the NOP, execution wouldn't actually
halt until you reached the label `1'.

This patch corrects that and also changes single-stepping so that a
branch and its delay slot are executed as one instruction for the
purposes of single-stepping.  This behavior is comparable to what other
MIPS tools (e.g. MIPSsim with MDI) do.  GDB avoids placing breakpoints
in branch delay slots, so this change doesn't break anything on the GDB
side.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-14 19:34:12 +02:00
Blue Swirl
72cf2d4f0e Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc923584,
f40d753718,
96555a96d7 and
3990d09adf but the fixes were fragile.

Solution: Avoid the conflict entirely by renaming the functions and the
file. Revert the previous hacks.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 07:36:22 +00:00
Nathan Froyd
fa31af0e63 target-mips: fix conditional moves off fp condition codes
Conditional moves off fp condition codes were using the result of
get_fp_bit to isolate and test the relevant condition code.  However,
get_fp_bit returns the bit number of the condition code, not a
bitmask.  (Compare the use of get_fp_bit in gen_compute_branch1, for
instance.)

Fixed by shifting a bitmask into place using the result of get_fp_bit in
the relevant functions (gen_mov{ci,cf_s,cf_d,cf_ps}).

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-08-25 18:05:27 +02:00
Nathan Froyd
0b5c1ce846 cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with a
few minor variations.  This patch sets up appropriate defaults for a
generic handle_cpu_signal and provides overrides for particular targets
that did things differently.  Fixing things like the persistent (XXX:
use sigsetjmp) should now become somewhat easier.

Previous comments on this patch suggest that the "activate soft MMU for
this block" comments refer to defunct functionality.  I have removed
such blocks for the appropriate targets in this patch.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-24 08:21:42 -05:00
Juan Quintela
e2542fe2bc rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:21 -05:00
Juan Quintela
dfe5fff3ea change HOST_SOLARIS to CONFIG_SOLARIS{_VERSION}
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:16 -05:00
Blue Swirl
8167ee8839 Update to a hopefully more future proof FSF address
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16 20:47:01 +00:00
Aurelien Jarno
344b983d9b target-mips: remove useless code in gen_st_cond()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-12 15:09:01 +02:00
Paul Brook
feeb3b6a7a Fix MIPS SC
Fix botched merge of op_ldst_sc calls to match actual implementation.
Thanks to Aurelien Jarno for diagnosing this.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-12 13:11:25 +01:00
Paul Brook
590bc601d8 MIPS atomic instructions
Implement MIPS ll/sc instructions using atomic compare+exchange.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-09 17:45:17 +01:00
Paul Brook
ff867ddcbd MIPS usermode TLS register
Implement cpu_set_tls for MIPS.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-09 15:07:57 +01:00
Nathan Froyd
98070ce00f target-mips: fix MADD and MSUB/MSUBU instructions
MADD was not correctly writing to HI.

MSUB/MSUBU are specified as `HI||LO - product', not `product - HI||LO'.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-03 03:28:20 +02:00
Blue Swirl
95bed64367 Fix a warning: uint_fast8_t is not 8 bits on OpenBSD/Sparc64
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-13 15:09:38 +00:00
Anthony Liguori
f80f9ec9a6 Convert machine registration to use module init functions
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-21 08:47:55 -05:00
Paul Brook
1ad2134f91 Hardware convenience library
The only target dependency for most hardware is sizeof(target_phys_addr_t).
Build these files into a convenience library, and use that instead of
building for every target.

Remove and poison various target specific macros to avoid bogus target
dependencies creeping back in.

Big/Little endian is not handled because devices should not know or care
about this to start with.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-19 16:17:58 +01:00
Paul Brook
5561650587 Include assert.h from qemu-common.h
Include assert.h from qemu-common.h and remove other direct uses.
cpu-all.h still need to include it because of the dyngen-exec.h hacks

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-13 20:54:26 +01:00
Blue Swirl
001faf3269 Replace gcc variadic macro extension with C99 version
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-13 17:53:17 +00:00
Aurelien Jarno
6bb72b184d target-mips: proper sign extension for 'SUBU rd, zero, rt'
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-05-04 10:05:21 +02:00
Aurelien Jarno
88cbb9804b target-mips: fix comments about SUB/DSUB
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-05-04 10:05:15 +02:00
aliguori
0bf46a40a1 qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-24 18:03:41 +00:00
aliguori
6a4955a813 qemu: per-arch cpu_has_work (Marcelo Tosatti)
Blue Swirl: fix Sparc32 breakage

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7238 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-24 18:03:20 +00:00
pbrook
df357f0e62 Enable access to SYNCI_Step register in usermode emulation.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7191 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-20 23:55:57 +00:00
aurel32
8c0ab41f4a Revert "target-mips: fix call to check_*() functions"
This reverts commit r7127, r7132 is a better fix for that.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7133 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-17 13:17:26 +00:00
aurel32
aefbc83e95 target-mips: simplify exception generation
There is no need to exit the tb after a call to helper_raise_exception
as it already calls cpu_loop_exit().

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7132 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-17 13:11:42 +00:00
aurel32
a6035857db target-mips: fix revision r7126
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7128 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16 12:57:50 +00:00
aurel32
007ac6faed target-mips: fix call to check_*() functions
check_*() functions may in fine call generate_exception(), which ends
by a call to tcg_gen_exit_tb(). As a consequence, we have to make sure
that no TCG temp variables are crossing a check_*() function.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7127 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16 11:51:19 +00:00
aurel32
585c88d5af target-mips: optimize gen_flt3_ldst()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7126 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16 11:51:11 +00:00
aurel32
c407df8156 target-mips: optimize gen_flt_ldst()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7125 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16 11:51:03 +00:00
pbrook
8e0f950d89 Stop translation after a syscall instruciton.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7124 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16 10:56:43 +00:00
aurel32
f2c94b926c target-mips: mark zero register as unused.
Suggested by Stuart Brady.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7107 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-15 14:42:00 +00:00
aurel32
d9bea11484 target-mips: variable names consistency
Use a consistent naming of arguments and TCG variables across the whole
file, the same as in tcg/tcg-op.h:
- arg1, arg2, ... for arguments
- t0, t1, t2, ... for variables

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7106 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-15 14:41:44 +00:00
aurel32
867abc7e50 target-mips: fix commits 7040 and 7042
CPU state should also be saved for helpers that in fine call
cpu_unlink_tb(). Reported by Stefan Weil.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7096 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-13 08:53:12 +00:00
aurel32
30a3848b77 target-mips: fix commit 7046
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7095 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-12 08:32:45 +00:00
aurel32
bb928dbef2 target-mips: don't map zero register as a TCG global
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7094 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-11 18:43:20 +00:00
aurel32
d66c7132d2 target-mips: optimize gen_ldst()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7093 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-11 18:42:55 +00:00
aurel32
324d9e3204 target-mips: optimize gen_arith_imm()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7092 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-11 18:42:17 +00:00
aurel32
52a0e9ebf1 target-mips: fix commit r7076
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7078 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-10 21:56:32 +00:00
aurel32
11f94258ac target-mips: optimize gen_movcf_d()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7077 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-10 21:42:18 +00:00
aurel32
a4e8338de8 target-mips: optimize a few tcg_temp_free()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7076 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-10 21:41:53 +00:00
aurel32
c9297f4d1d target-mips: optimize gen_farith()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7046 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-08 21:48:27 +00:00
aurel32
c905fdacb4 target-mips: optimize gen_flt3_arith()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7045 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-08 21:48:18 +00:00
aurel32
4e2474d677 target-mips: optimize gen_flt3_ldst()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7044 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-08 21:48:10 +00:00
aurel32
460f00c4e1 target-mips: optimize gen_arith()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7043 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-08 21:48:02 +00:00
aurel32
35fbce2c41 target-mips: optimize decode_opc()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7042 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-08 21:47:55 +00:00
aurel32
72c3a3ee4d target-mips: optimize gen_cp1()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7041 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-08 21:47:44 +00:00
aurel32
1fc7bf6ee8 target-mips: optimize gen_cp0()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7040 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-08 21:47:35 +00:00
aurel32
e7a6965b5a target-mips: use the TCG_CALL_PURE and TCG_CALL_CONST for some helpers
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7009 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-06 12:34:07 +00:00
aurel32
1b530a6dfc Add new command line option -singlestep for tcg single stepping.
This replaces a compile time option for some targets and adds
this feature to targets which did not have a compile time option.

Add monitor command to enable or disable single step mode.

Modify monitor command "info status" to display single step mode.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7004 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-05 20:08:59 +00:00
aurel32
cbc37b28b3 target-mips: optimize gen_movcf_*()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6957 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 15:45:02 +00:00
aurel32
af58f9ca43 target-mips: optimize gen_movci()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6956 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 15:44:50 +00:00
aurel32
d94536f417 target-mips: optimize gen_compute_branch1()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6955 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 15:44:34 +00:00
aurel32
6d0662746b target-mips: don't map FP registers as TCG global variables
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6950 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 15:39:08 +00:00
aurel32
0c0ed03b40 target-mips: fix divu instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6949 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 15:36:47 +00:00
aurel32
41db460791 target-mips: optimize write to env->hflags
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6941 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 01:28:29 +00:00
aurel32
d45f89f4e4 target-mips: optimize gen_muldiv()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6940 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 01:19:31 +00:00
aurel32
f129981a6a target-mips: optimize gen_HILO()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6938 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 01:19:12 +00:00
aurel32
cdc0faa66a target-mips: optimize gen_trap()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6937 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 01:19:02 +00:00
aurel32
1ba74fb8f1 target-mips: optimize gen_compute_branch()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6936 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 01:18:52 +00:00
aurel32
92e9044304 target-mips: don't mix result and arguments in gen_op_*
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6935 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 01:18:43 +00:00
aurel32
3a55fa4796 target-mips: gen_bshfl()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6934 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 01:18:34 +00:00
aurel32
f157bfe11a target-mips: optimize gen_mul_vr54xx()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6933 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 01:18:24 +00:00
aurel32
20e1fb525a target-mips: optimize gen_cl()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6932 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 01:18:16 +00:00
aurel32
f364515c83 target-mips: fix FPU in 64-bit mode
TCG does not allow the same memory location to be aliased in two
different global registers, fpu_fpr32 and fpu_fpr64.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6915 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-28 22:22:50 +00:00
aurel32
41e0c70159 target-mips: implement FPU Flush-To-Zero mode
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6914 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-28 22:22:40 +00:00
aurel32
a3fe901337 target-mips: use nor instead of or + not
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6801 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-10 09:03:18 +00:00
aurel32
a1f6684d65 target-mips: optimize mflo and mfhi
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6794 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-09 18:50:43 +00:00
aurel32
d5575a38b6 target-mips: remove dead code
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6774 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-08 00:06:10 +00:00
aurel32
c01fccd2de target-mips: rename helpers from do_ to helper_
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6773 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-08 00:06:01 +00:00
pbrook
c276471991 The _exit syscall is used for both thread termination in NPTL applications,
and process termination in legacy applications.  Try to guess which we want
based on the presence of multiple threads.

Also implement locking when modifying the CPU list.


Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6735 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 15:24:59 +00:00
aliguori
0d0266a53b targets: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05 22:06:11 +00:00
aliguori
eca1bdf415 Log reset events (Jan Kiszka)
Original idea&code by Kevin Wolf, split-up in two patches and added more
archs.

This patch introduces a flag to log CPU resets. Useful for tracing
unexpected resets (such as those triggered by x86 triple faults).

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6452 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-26 19:54:31 +00:00
aliguori
8fec2b8c45 global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &
X) qemu_log()' statement.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6340 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 22:36:53 +00:00
aliguori
93fcfe39a0 Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevel
global variables to use the new qemu_log*() macros.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6338 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 22:34:14 +00:00
aliguori
d12d51d5ba Clean up debugging code #ifdefs (Eduardo Habkost)
Use macros to avoid #ifdefs on debugging code.

This patch doesn't try to merge logging macros from different files,
but just unify the debugging code #ifdefs onto a macro on each file. A
further cleanup can unify the debugging macros on a common header, later

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6332 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 21:48:06 +00:00
aurel32
e9203484cb target-mips: optimize some gpr accesses
Optimize gpr accesses when it is known at translation time that gpr != 0.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6307 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-14 19:40:46 +00:00
aurel32
6958549d4f target-mips: fix indentation
Remove all tabs from target-mips/*

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6306 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-14 19:40:36 +00:00
aurel32
932e71cd57 target-mips: get rid of tests on env->user_mode_only
Replace runtime checks on env->user_mode_only by compile time
checks on CONFIG_USER_ONLY.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6276 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-12 21:33:13 +00:00
aurel32
fad6cb1a56 Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:05:52 +00:00
malc
b1503cda1e Use the ARRAY_SIZE() macro where appropriate.
Change from v1:
  Avoid changing the existing coding style in certain files.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-22 20:33:55 +00:00
ths
33a84765e3 A first attempt on supporting snapshots for the MIPS target.
Signed-off-by: Thiemo Seufer <ths@networkno.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6112 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-20 19:44:31 +00:00
ths
f9480ffc14 Fix remaining compiler warnings for mips targets.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6111 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-20 19:42:14 +00:00
blueswir1
1d6198c3b0 Remove unnecessary trailing newlines
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13 09:32:43 +00:00
aurel32
cd5158ea69 MIPS: remove a few warnings
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5944 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 23:26:24 +00:00
aurel32
2cbd949d7a Common cpu_loop_exit prototype
All archs use the same cpu_loop_exit, so move the prototype in a common
header. i386 was carrying a __hidden attribute, but that was empty for
this arch anyway.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5820 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:23:09 +00:00
aliguori
c0ce998e94 Use sys-queue.h for break/watchpoint managment (Jan Kiszka)
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying the
code and also fixing a use after release issue in
cpu_break/watchpoint_remove_all.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5799 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-25 22:13:57 +00:00
aliguori
a1d1bb3101 Refactor and enhance break/watchpoint API (Jan Kiszka)
This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow the
succeeding enhancements this series comes with.

First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switching
to dynamically allocated data structures that are kept in linked lists.
This also allows to return a stable reference to the related objects,
required for later introduced x86 debug register support.

Breakpoints and watchpoints are stored with their full information set
and an additional flag field that makes them easily extensible for use
beyond pure guest debugging.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5738 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 20:07:32 +00:00
aliguori
6b9175478e Refactor translation block CPU state handling (Jan Kiszka)
This patch refactors the way the CPU state is handled that is associated
with a TB. The basic motivation is to move more arch specific code out
of generic files. Specifically the long #ifdef clutter in tb_find_fast()
has to be overcome in order to avoid duplicating it for the gdb
watchpoint fixes (patch "Restore pc on watchpoint hits").

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5736 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 19:46:41 +00:00
aliguori
622ed3605b Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)
as macros should be avoided when possible.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 19:36:03 +00:00
pbrook
a7812ae412 TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 14:43:54 +00:00
aurel32
da80682b42 target-mips: avoid tcg internal error in mfc0/dmfc0
Set t0 to 0 for unimplemented mfc0/dmfc0 instructions. This fixes a tcg
internal error while booting mips linux.

Noticed by Julia Longtin.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5723 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-15 12:12:08 +00:00
aurel32
de9a95f022 Revert commits 5685 to 5688 committed by mistake
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5691 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 13:41:01 +00:00
aurel32
1c58b16694 Don't stop translation for mtc0 compare
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5686 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 13:30:37 +00:00
aurel32
a6e92a658b target-mips: gen_compute_branch1()
Optimize code generation in gen_compute_branch1():
- Directly use I32 variables instead of converting values from _tl to
  _i32 and back to _tl.
- Write the result directly to bcond instead of passing by a local
  variable.
- Temp variables are valid up to and *including* the brcond instruction.
  Use them instead of temp local variables.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5684 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 11:50:51 +00:00
aurel32
9bf3eb2ca5 target-mips: optimize movc*()
Optimize code generation in gen_movc*():
- Temp variables are valid up to and *including* the brcond instruction.
  Use them instead of temp local variables.
- Avoid using temporary variables to transfer values.
- Access fpu_fcr31 directly in gen_movcf_ps().

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5683 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 11:50:43 +00:00
aurel32
2a0ab99899 target-mips: optimize gen_farith()
Optimize code generation in gen_farith():
- Temp variables are valid up to and *including* the brcond instruction.
  Use them instead of temp local variables.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5682 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 11:50:33 +00:00
aurel32
b10fa3c906 target-mips: optimize gen_muldiv()
Optimize code generation in gen_muldiv():
- Don't do sign extension when the value is already guaranteed to be
  sign extended (otherwise, results are marked as UNPREDICTABLE).
- Access the LO, HI registers directly instead of writting them through
  a temporary variable.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5681 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 11:50:25 +00:00
aurel32
507563e85d target-mips: optimize gen_arith()/gen_arith_imm()
Optimize code generation in gen_arith()/gen_arith_imm():
- Don't do sign extension when the value is already guaranteed to be
  sign extended (otherwise, results are marked as UNPREDICTABLE).
- When the value is sign extended, compare the value to 0 instead of
  testing bit 31/63.
- Temp variables are valid up to and *including* the brcond instruction.
  Use them instead of temp local variables.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5680 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 11:50:17 +00:00
aurel32
49bcf33cc7 target-mips: convert bit shuffle ops to TCG
Bit shuffle operations can be written with very few TCG instructions
(between 5 and 8), so it is worth converting them to TCG.

This code also move all bit shuffle generation code to a separate
function in order to have a cleaner exception code path, that is it
doesn't store back the TCG register to the target register after the
exception, as the TCG register doesn't exist anymore.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5679 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 11:47:06 +00:00
aurel32
505ad7c2ff target-mips: convert bitfield ops to TCG
Bitfield operations can be written with very few TCG instructions
(between 2 and 5), so it is worth converting them to TCG.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5678 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 11:46:58 +00:00
aurel32
2623c1ecfc target-mips: optimize gen_op_addr_add() (2/2)
Instead of dynamically generating different code depending on the UX
flag, add a new flag in ctx->flags to generate different code.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5677 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 11:39:33 +00:00
aurel32
d144d1d9e5 target-mips: optimize gen_op_addr_add() (1/2)
The user mode can be tested at translation time using ctx->hflags.
This simplifies gen_op_addr_add().

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5676 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 11:36:52 +00:00
aurel32
1eb75d4a36 target-mips: optimize gen_save_pc()
We obviously don't need to use a temporary variable to write PC.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5675 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 11:36:04 +00:00
aurel32
add69063e8 target-mips: fix mft* helpers/call
This patch attempts to fix mft* helpers and the associated TCG calls.
mft* helpers do not take a register in argument, however:
- some helpers are called with an argument while they do not take one.
- some helpers are declared with an argument they don't use.

Acked-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5674 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 11:34:39 +00:00
aurel32
c24135ffcc target-mips: fix temporary variable freeing in op_ldst_##insn()
Move tcg_temp_free() out of the conditional part to make sure
the TCG temporary variable is freed in all cases.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Thiemo Seufer <ths@networkno.de>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5673 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 11:34:30 +00:00
aurel32
e00fcff710 target-mips: use the new rotr/rotri instructions
Acked-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5622 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-04 19:13:47 +00:00
blueswir1
e18231a3ff Show size for unassigned accesses (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5436 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-06 18:46:28 +00:00
ths
cb2c9921f8 Use concet TCG instructions in the MIPS target.
Signed-off-by: Thiemo Seufer <ths@networkno.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5303 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-22 21:54:00 +00:00
ths
9c67ef0cb5 Fix Xcontext fill, by Here Poussineau.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5284 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-21 21:21:26 +00:00
pbrook
36aa55dcd9 Add concat_i32_i64 op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-21 13:48:32 +00:00
ths
4b2eb8d275 Use TCG registers for most CPU register accesses.
Signed-off-by: Thiemo Seufer <ths@networkno.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5253 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18 11:59:03 +00:00
ths
f01be15458 Move the active FPU registers into env again, and use more TCG registers
to access them.

Signed-off-by: Thiemo Seufer <ths@networkno.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5252 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18 11:57:27 +00:00
aurel32
bbc0d79cb7 MIPS: Fix tlbwi/tlbwr
In CP0 Index register, bit 31 means 'Probe Failure', while lowest bits
contain the TLB index.

In tlbwi and tlbwr instructions, this Probe Failure bit must be ignored
when reading the TLB index.

Attached patch fixes it.

(Hervé Poussineau)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5215 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-14 17:09:56 +00:00
aurel32
75973fa1ee MIPS: remove empty cpu_mips_irqctrl_init()
cpu_mips_irqctrl_init() function in hw/mips_timer.c is empty.
Attached patch removes it, and its callers.

(Hervé Poussineau)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5214 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-14 16:38:57 +00:00
aurel32
929a62a0d7 target-mips: fix warning
Attached patch fixes a warning in cpu_mips_find_by_name().
'name' is a string, so it should be declared as char*, not unsigned char*.

(Hervé Poussineau)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5213 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-14 16:28:26 +00:00
aurel32
2fdbad255e TCG fixes for target-mips
This patch fixes TCG errors reported on the MIPS target when TCG_DEBUG
is enabled.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Thiemo Seufer <ths@networkno.de>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5164 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05 14:19:17 +00:00
ths
f8a6ec5817 Build fix for gcc-3.3.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5139 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 17:39:45 +00:00
blueswir1
79383c9c08 Fix some warnings that would be generated by gcc -Wredundant-decls
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30 09:51:20 +00:00
aurel32
492b239197 MIPS: don't free TCG temporary variable twice
In gen_dmtc0 function, TCG temporary variable t0 is freed at the end of
the function. Variable is freed again in the gen_dmtc0 caller.
I removed the free in gen_dmtc0, to do like in gen_dmfc0, gen_mfc0,
gen_mtc0.

(Hervé Poussineau)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5075 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-23 17:22:19 +00:00
ths
0fd70f8f20 Delete unused variable.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4981 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-01 17:14:35 +00:00
ths
c904ef0e7c Use plain standard inline.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4929 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-23 16:16:31 +00:00
ths
0eaef5aa01 Less hardcoding of TARGET_USER_ONLY.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4928 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-23 16:14:22 +00:00
ths
8706c3824f A bunch of minor code improvements in the MIPS target.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4921 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-21 21:38:04 +00:00
ths
3d5be8709b Fix logging output for MIPS HI, LO registers, by Stefan Weil.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4916 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-21 07:46:03 +00:00
ths
50366fe93a Fix compiler warning, by Stefan Weil.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4915 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-20 19:13:19 +00:00
ths
920c608ef3 Simplify conditional FP moves.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4913 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-20 18:48:42 +00:00
ths
2cfc5f17d3 Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-18 18:01:29 +00:00
ths
b6d96beda3 Use temporary registers for the MIPS FPU emulation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4861 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-09 11:05:10 +00:00
ths
c7e8a937b7 Fix typo in comment.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4852 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-05 21:54:32 +00:00
ths
63742cf887 Change MIPS machine default to Malta.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4851 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-05 21:51:47 +00:00
pbrook
9656f324d2 Move interrupt_request and user_mode_only to common cpu state.
Save and restore env->interrupt_request and env->halted.



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-01 20:01:19 +00:00
ths
356265ae4a Static'ify some functions, and use standard inline in translate.c.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4813 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-01 16:37:52 +00:00
ths
ea334207a3 Delete duplicate code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4811 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-01 08:45:45 +00:00
ths
bf20dc076b Spelling fixes, spotted by Stuart Brady.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4809 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-30 17:22:19 +00:00
pbrook
b3c7724cbc Move CPU save/load registration to common code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-30 16:31:04 +00:00
ths
d077b6f759 Make bcond and btarget TCG registers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4805 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-30 11:30:34 +00:00
ths
d26968ecd8 Remove unnecessary helper arguments, and fix some typos.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4802 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-29 14:53:11 +00:00
pbrook
dd5d6fe913 Add missing file. Fix spelling errors.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4800 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-29 10:43:16 +00:00
pbrook
2e70f6efa8 Add instruction counter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-29 01:03:05 +00:00
ths
2796188e56 Avoid unused input arguments which triggered tcg errors. Spotted by
Stefan Weil.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4795 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-27 10:03:42 +00:00
ths
b5dc7732e1 More efficient target register / TC accesses.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4794 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-27 10:02:35 +00:00
ths
ebbd0ffddd Clarify some TODO items.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4789 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-24 22:04:41 +00:00
ths
1a3fd9c3da Remove remaining uses of T0 in the MIPS target.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4788 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-24 21:58:35 +00:00
ths
e1bf387ec8 T1 is now dead.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4787 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-24 20:13:20 +00:00
ths
7872368461 Reduce use of fixed registers a bit more.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4786 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-24 20:12:33 +00:00
ths
6c5c1e2057 Use temporaries instead of fixed registers for some instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4784 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-24 15:12:27 +00:00
ths
be24bb4f30 Pass T0/T1 explicitly to helper functions, and clean up a few dyngen
leftovers.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4780 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-23 12:57:09 +00:00
ths
3f05d3dc14 Delete obsolete file.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4762 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-20 15:29:38 +00:00
ths
b6a8c26b60 Delete obsolete file.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4761 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-20 15:21:28 +00:00
ths
3fafcb48f9 Delete obsolete prototypes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4760 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-20 15:20:35 +00:00
ths
c8c2227e91 Convert unaligned load/store to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4759 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-20 15:12:14 +00:00
ths
92af06d216 Convert vr54xx multiply instructions to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4756 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-20 14:35:19 +00:00
ths
caa88be0f5 Remove now-dead code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4754 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-19 18:38:40 +00:00
ths
a16336e479 Convert remaining MIPS FP instructions to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4753 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-19 18:35:02 +00:00
ths
214c465f86 Switch the standard multiplication instructions to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4740 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-12 12:43:29 +00:00
ths
2b0233abfb Switch bitfield instructions and assorted special ops to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4739 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-12 12:42:35 +00:00
ths
200ae688b2 TCGify the simplest FP instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4737 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-12 03:17:06 +00:00
ths
08ba79632f TCGify a few more instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4736 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-12 03:15:13 +00:00
ths
2681b45add Update TODO list.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4735 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-11 20:58:36 +00:00
ths
5d0fc900d3 Call most FP helpers without deroute through op.c
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4734 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-11 15:27:54 +00:00
ths
0d1d0094d7 Delete obsolete file.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4733 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-11 13:24:47 +00:00
ths
aa0bf00b65 Switch most MIPS FP load/stores to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4732 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-11 13:02:57 +00:00
ths
faf7aaa918 Avoid gen_opc_buf overflow.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4731 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-11 12:26:29 +00:00
ths
9843a0d2c6 Free some more temporaries.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-11 10:40:33 +00:00
ths
764dfc3fa0 Move FP TNs to cpu env.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4728 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-11 10:39:48 +00:00
ths
2c2435bdd4 Fix data type mixup, spotted by malc.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4724 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-10 01:18:32 +00:00
ths
f1aa63203d Switch remaining CP0 instructions to TCG or helper functions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4708 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-09 07:13:38 +00:00
ths
7dd9e556e3 Register helper functions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4700 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-08 07:42:23 +00:00
ths
c239529e7f Free constant temporaries.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4670 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-05 08:38:44 +00:00
ths
4f57689a8d Explicitly free temporaries.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4667 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-04 17:37:03 +00:00
ths
29cf4b7516 Remove the temporaries cache of the MIPS target.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4666 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-04 17:36:02 +00:00
ths
b6ce8f0aea Fix pointer calculation for MIPS64 targets.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4665 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-04 17:34:54 +00:00
ths
0fead1259a Delete duplicate code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4656 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-04 04:21:01 +00:00
ths
f5b78d4fea Fix type mismatch.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4652 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-02 09:35:46 +00:00
ths
a569557f52 Fix argument order.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4651 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-02 08:24:41 +00:00
ths
619dfca13a Proper sign extensions for 32-bit divisions, spotted by Richard Sandiford.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4650 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-02 07:15:18 +00:00
pbrook
f8ed7070ea Fix typo.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-30 17:54:15 +00:00
pbrook
6e68e076e7 Move clone() register setup to target specific code. Handle fork-like clone.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-30 17:22:15 +00:00
ths
a4a99d71b2 Fix for 32-bit MIPS.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4622 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-30 00:12:52 +00:00
ths
90cb786c41 Avoid qemu SIGFPE for MIPS DIV, by Richard Sandiford.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4621 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-29 18:29:05 +00:00
ths
9b686843a0 Fix truncate/extend reversal in MIPS DIV{, U} handling, by Richard Sandiford.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4620 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-29 18:28:07 +00:00
ths
84774e8ea3 Fix modulus result from MIPS DDIV & avoid overflowing division,
by Richard Sandiford.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4619 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-29 18:23:31 +00:00
bellard
9133e39b84 Push common interrupt variables to cpu-defs.h (Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-29 10:08:06 +00:00
bellard
ce5232c5c2 moved halted field to CPU_COMMON
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-28 17:14:10 +00:00
ths
893f986502 Honour current_tc for MIPS M{T,F}{HI,LO}, by Richard Sandiford.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4604 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-28 13:37:19 +00:00
pbrook
9b7b85d260 Fix off-by-one unwinding error.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-25 00:36:06 +00:00
ths
e6bb7d7efd Fix mov[tf].ps handling for MIPS, by Richard Sandiford.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4563 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-24 19:46:23 +00:00
ths
2784847001 Un-break MIPS conditional moves, by Richard Sandiford.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4562 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-24 19:06:07 +00:00
pbrook
cb63669a54 Fix ARM conditional branch bug.
Add tcg_gen_brcondi.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4552 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-24 02:22:00 +00:00
ths
f0b3f3ae5d Swithc some MIPS CP0 accesses to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4546 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-23 18:10:51 +00:00
ths
e214b9bb55 Switch MIPS movf/movt to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4545 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-23 18:06:27 +00:00
ths
95af5ce5e2 Fix build failure for MIPS64 targets on 64-bit hosts.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4536 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-23 01:31:57 +00:00
ths
42388c4ba7 Delete dead code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4535 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-22 20:42:15 +00:00
ths
8e9ade681b Switch MIPS branch handling to TCG, and clean out pointless wrapper
functions/macros.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4533 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-22 17:46:10 +00:00
ths
30898801ad Switch MIPS clo/clz and the condition tests to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4507 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-21 02:04:15 +00:00
ths
20c4c97c9b Switch MIPS movn/movz to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4506 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-21 02:02:39 +00:00
ths
4eecc06ed0 Add file left out from previous commit.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4497 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-18 23:39:23 +00:00
ths
48d38ca52b Switch most MIPS logical and arithmetic instructions to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4496 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-18 22:50:49 +00:00
ths
8c99506cfb Fix local register cache handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4495 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-18 22:15:12 +00:00
bellard
a607922c75 fixed do_restore_state()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4413 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-10 15:42:17 +00:00
ths
1ffc346f95 Be more economical with local temporaries.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4384 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-07 18:18:09 +00:00
ths
bec19c0932 Mention missing CPU save/restore.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4381 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-07 15:39:12 +00:00
ths
cdf5cf540b Delete redundant prototype.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4379 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-07 15:29:58 +00:00
ths
58565070ee Delete more obsolete dyngen ops.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4372 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-07 13:47:01 +00:00
ths
6a2d4d49f9 Delete obsolete MIPS dyngen ops.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4370 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-07 09:56:06 +00:00
ths
aaa9128a02 Convert some MIPS load/store instructions to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4369 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-06 21:40:48 +00:00
ths
36271893ab Enable 64-bit FPU only for NewABI. Spotted by Vince Weaver.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4368 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-06 20:48:02 +00:00
ths
958fb4a92c Use TCG for MIPS GPR moves.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4356 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-06 10:57:59 +00:00
ths
b7ef7bf225 Fix MIPS64 branches. Funny how this survived testing.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4355 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-06 10:03:16 +00:00
aurel32
4586f9e9a1 Really really revert commit r4343
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4348 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-05 21:42:19 +00:00
aurel32
e34d2d62a3 Really revert commit r4343
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4347 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-05 21:35:09 +00:00
aurel32
d478990a52 Don't stop translation for mtc0 compare
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4343 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-05 21:27:01 +00:00
aurel32
8dd3dca351 remove target ifdefs from vl.c
(Glauber Costa)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4327 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-04 13:11:44 +00:00
ths
3945462805 Simplify mips branch handling. Retire T2 from use. Use TCG for branches.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4320 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-04 08:16:10 +00:00
ths
5b2808bfc0 Fix MIPS MT GPR accesses, thanks Stefan Weil.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4307 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-03 11:06:59 +00:00
aurel32
d2856f1ad4 Factorize code in translate.c
(Glauber Costa)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-28 00:32:32 +00:00
aurel32
ca10f86763 Remove osdep.c/qemu-img code duplication
(Kevin Wolf)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-11 21:35:42 +00:00
ths
53715e48b0 Fix infinite loop when invalidating TLB, by Herve Poussineau.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4136 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-29 21:43:23 +00:00
ths
d0dc7dc327 Make MIPS MT implementation more cache friendly.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3981 c046a42c-6fe2-441c-8c8c-71466251a162
2008-02-12 21:01:26 +00:00
bellard
57fec1fee9 use the TCG code generator
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
2008-02-01 10:50:11 +00:00
ths
a139a3ad23 Fix typo which broke MIPS32R2 64-bit FPU support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3902 c046a42c-6fe2-441c-8c8c-71466251a162
2008-01-09 12:03:22 +00:00
ths
6b5435d77c Fix broken absoluteness check for cabs.d.*.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3900 c046a42c-6fe2-441c-8c8c-71466251a162
2008-01-08 18:11:08 +00:00
ths
b67bfe8d9f Handle some more exception types.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3886 c046a42c-6fe2-441c-8c8c-71466251a162
2008-01-04 17:52:57 +00:00
ths
9a5d878f6e Fix exception debug output.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3885 c046a42c-6fe2-441c-8c8c-71466251a162
2008-01-03 21:26:23 +00:00
ths
b8aa4598e2 MIPS COP1X (and related) instructions, by Richard Sandiford.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3877 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-30 15:36:58 +00:00
ths
ea4b07f762 Set FCR0.F64 for MIPS64R2-generic, by Richard Sandiford.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3865 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-28 12:35:05 +00:00
ths
14e51cc7a4 De-cruft exception definitions, and implement nicer debug output.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3861 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-26 19:34:03 +00:00
ths
e9c71dd1c1 Support for VR5432, and some of its special instructions. Original patch
by Dirk Behme.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3859 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-25 20:46:56 +00:00
ths
29fe0e3490 5K and 20K are Release 1 CPUs.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3858 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-25 17:32:46 +00:00
ths
306ab3e86a Avoid host FPE for overflowing division on MIPS, by Richard Sandiford.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3856 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-25 03:18:19 +00:00
ths
6d35524c40 Improved PABITS handling, and config register fixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3855 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-25 03:13:56 +00:00
ths
b352fa43ea Update debug code to match new accumulator register layout.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3853 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-24 16:24:42 +00:00
ths
a1daafd8df Fix CCRes value for 20Kc.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3849 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-24 14:33:57 +00:00
ths
0300e3faf6 MIPS TODO: mention unimplemented system controllers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3830 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-17 03:53:42 +00:00
ths
bbbe9b8822 Update MIPS TODO. The mipsnet failure is caused by a kernel bug.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3829 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-17 03:50:28 +00:00
ths
01ba98161f Handle cpu_model in copy_cpu(), by Kirill A. Shutemov.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3778 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-09 02:22:57 +00:00
ths
dab6322b86 Larger physical address space for 32-bit MIPS.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3765 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-02 07:14:17 +00:00
ths
ae2dbf7fb0 Micro-optimize back-to-back store-load sequences.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3743 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-26 09:01:34 +00:00
ths
185f07621f Optimize the conventional move operation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3720 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-22 15:10:21 +00:00
ths
67d6abff60 Fix off-by-one address checks in MIPS64 MMU, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3718 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-22 00:34:36 +00:00
ths
8d162c2b68 Add older 4Km variants.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3708 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-19 16:10:33 +00:00
pbrook
f090c9d4ad Add strict checking mode for softfp code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3688 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-18 14:33:24 +00:00
ths
c6d6dd7c74 Fix MIPS64 R2 instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3686 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-18 03:36:07 +00:00
ths
8c89395eeb Use a valid PRid.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3685 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-18 03:19:58 +00:00
pbrook
5747c0733d Fix int/float inconsistencies.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3672 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17 14:53:06 +00:00
ths
3e4587d5d1 Introduce 4KEm configuration with fixed MMU mapping. Delete bogus INSN_DSP
flags.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3637 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-14 03:11:17 +00:00
bellard
aaed909a49 added cpu_model parameter to cpu_init()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-10 15:15:54 +00:00
ths
8f6f6026f1 Use FORCE_RET, scrap RETURN which was implemented in target-specific code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3560 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-09 23:09:41 +00:00
ths
7df526e317 Move kernel loader parameters from the cpu state to being board specific.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3557 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-09 17:52:11 +00:00
ths
d26bc2118e Clean out the N32 macros from target-mips, and introduce MIPS ABI specific
defines for linux-user.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3556 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-08 18:05:37 +00:00
ths
855cea8c92 Formatting fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3554 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-08 16:44:01 +00:00
ths
273af66025 Adjust s390 addresses (the MSB is defined as "to be ignored").
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3486 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-29 14:39:49 +00:00
ths
d2123ead89 Preliminary MIPS64R2 mode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3479 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-29 09:38:43 +00:00
ths
6276c76758 Fix logic bug which broke TLBL/TLBS handling somewhat.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3478 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-29 02:57:19 +00:00
ths
1b6fd0bc55 Restrict CP0_PerfCnt to legal values.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3476 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-29 00:49:32 +00:00
ths
623a930ec3 Implement missing MIPS supervisor mode bits.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3472 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-28 19:45:05 +00:00
ths
05f778c8bd Add sharable clz/clo inline functions and use them for the mips target.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3455 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-27 13:05:54 +00:00
ths
5592a750b9 The other half of the mul64 rework. Sorry for the breakage, I committed
an incomplete version of what I tested.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3454 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-26 22:35:02 +00:00
ths
9f77c1cdcf Remove bogus instruction decode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3433 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-24 00:52:07 +00:00
ths
6ad3872210 Force proper sign extension for mfc0/mfhc0 on MIPS64.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3432 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-24 00:10:32 +00:00
ths
60445285a8 Fix writable length of the index register.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3431 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-23 23:58:21 +00:00