qemu/target-mips
Nathan Froyd 364d48314a target-mips: add mips16 instruction decoding
There's no good way to add this incrementally, so we do it all at once.
The only changes to shared code are in handle_delay_slot.  We need to
flip ISAMode when doing a jump-and-exchange.  We also need to set
ISAMode the low bit of the target address for jump-to-register.

Also, since we're now adding bits that can be in MIPS_HFLAG_BMASK_EXT,
make sure we use MIPS_HFLAG_BMASK_BASE in the places where we just want
basic information about a branch.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:20 +01:00
..
cpu.h target-mips: add new HFLAGs for JALX and 16/32-bit delay slots 2009-12-13 20:20:19 +01:00
exec.h qemu: per-arch cpu_has_work (Marcelo Tosatti) 2009-04-24 18:03:20 +00:00
helper.c target-mips: change interrupt bits to be mips16-aware 2009-12-13 20:20:19 +01:00
helper.h target-mips: use physical address in lladdr 2009-11-30 16:18:28 +01:00
machine.c target-mips: rename CP0_LLAddr into lladdr 2009-11-22 14:12:13 +01:00
mips-defs.h Hardware convenience library 2009-05-19 16:17:58 +01:00
op_helper.c target-mips: change interrupt bits to be mips16-aware 2009-12-13 20:20:19 +01:00
TODO Move the active FPU registers into env again, and use more TCG registers 2008-09-18 11:57:27 +00:00
translate_init.c target-mips: make CP0_LLAddr register CPU dependent 2009-11-22 14:12:19 +01:00
translate.c target-mips: add mips16 instruction decoding 2009-12-13 20:20:20 +01:00