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target-mips: rename CP0_LLAddr into lladdr

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The variable CP0_LLAddr represent the full lladdr, not the actual
register value, which is only part of this value and depends on the
CPU.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2009-11-22 13:08:14 +01:00
parent dd4239d657
commit 5499b6ffac
5 changed files with 18 additions and 18 deletions
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4
linux-user/main.c
View File

@ -1849,7 +1849,7 @@ static int do_store_exclusive(CPUMIPSState *env)
int reg;
int d;
addr = env->CP0_LLAddr;
addr = env->lladdr;
page_addr = addr & TARGET_PAGE_MASK;
start_exclusive();
mmap_lock();
@ -1879,7 +1879,7 @@ static int do_store_exclusive(CPUMIPSState *env)
}
}
}
env->CP0_LLAddr = -1;
env->lladdr = -1;
if (!segv) {
env->active_tc.PC += 4;
}

2
target-mips/cpu.h
View File

@ -372,7 +372,7 @@ struct CPUMIPSState {
int32_t CP0_Config6;
int32_t CP0_Config7;
/* XXX: Maybe make LLAddr per-TC? */
target_ulong CP0_LLAddr;
target_ulong lladdr;
target_ulong llval;
target_ulong llnewval;
target_ulong llreg;

4
target-mips/machine.c
View File

@ -127,7 +127,7 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_sbe32s(f, &env->CP0_Config3);
qemu_put_sbe32s(f, &env->CP0_Config6);
qemu_put_sbe32s(f, &env->CP0_Config7);
qemu_put_betls(f, &env->CP0_LLAddr);
qemu_put_betls(f, &env->lladdr);
for(i = 0; i < 8; i++)
qemu_put_betls(f, &env->CP0_WatchLo[i]);
for(i = 0; i < 8; i++)
@ -279,7 +279,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_sbe32s(f, &env->CP0_Config3);
qemu_get_sbe32s(f, &env->CP0_Config6);
qemu_get_sbe32s(f, &env->CP0_Config7);
qemu_get_betls(f, &env->CP0_LLAddr);
qemu_get_betls(f, &env->lladdr);
for(i = 0; i < 8; i++)
qemu_get_betls(f, &env->CP0_WatchLo[i]);
for(i = 0; i < 8; i++)

14
target-mips/op_helper.c
View File

@ -730,7 +730,7 @@ target_ulong helper_mftc0_status(void)
target_ulong helper_mfc0_lladdr (void)
{
return (int32_t)env->CP0_LLAddr >> 4;
return (int32_t)env->lladdr >> 4;
}
target_ulong helper_mfc0_watchlo (uint32_t sel)
@ -795,7 +795,7 @@ target_ulong helper_dmfc0_tcschefback (void)
target_ulong helper_dmfc0_lladdr (void)
{
return env->CP0_LLAddr >> 4;
return env->lladdr >> 4;
}
target_ulong helper_dmfc0_watchlo (uint32_t sel)
@ -959,7 +959,7 @@ void helper_mtc0_tcrestart (target_ulong arg1)
{
env->active_tc.PC = arg1;
env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
env->CP0_LLAddr = 0ULL;
env->lladdr = 0ULL;
/* MIPS16 not implemented. */
}
@ -970,12 +970,12 @@ void helper_mttc0_tcrestart (target_ulong arg1)
if (other_tc == env->current_tc) {
env->active_tc.PC = arg1;
env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
env->CP0_LLAddr = 0ULL;
env->lladdr = 0ULL;
/* MIPS16 not implemented. */
} else {
env->tcs[other_tc].PC = arg1;
env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
env->CP0_LLAddr = 0ULL;
env->lladdr = 0ULL;
/* MIPS16 not implemented. */
}
}
@ -1702,7 +1702,7 @@ void helper_eret (void)
}
compute_hflags(env);
debug_post_eret();
env->CP0_LLAddr = 1;
env->lladdr = 1;
}
void helper_deret (void)
@ -1712,7 +1712,7 @@ void helper_deret (void)
env->hflags &= MIPS_HFLAG_DM;
compute_hflags(env);
debug_post_eret();
env->CP0_LLAddr = 1;
env->lladdr = 1;
}
#endif /* !CONFIG_USER_ONLY */

12
target-mips/translate.c
View File

@ -918,7 +918,7 @@ static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
TCGv t0 = tcg_temp_new(); \
tcg_gen_mov_tl(t0, arg1); \
tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \
tcg_temp_free(t0); \
}
@ -941,7 +941,7 @@ static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ct
tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
generate_exception(ctx, EXCP_AdES); \
gen_set_label(l1); \
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \
@ -967,7 +967,7 @@ static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ct
tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
generate_exception(ctx, EXCP_AdES); \
gen_set_label(l1); \
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, llval)); \
tcg_gen_qemu_##ldname(t1, arg2, ctx->mem_idx); \
@ -8501,8 +8501,8 @@ cpu_mips_check_sign_extensions (CPUState *env, FILE *f,
if (!SIGN_EXT_P(env->CP0_EPC))
cpu_fprintf(f, "BROKEN: EPC=0x" TARGET_FMT_lx "\n", env->CP0_EPC);
if (!SIGN_EXT_P(env->CP0_LLAddr))
cpu_fprintf(f, "BROKEN: LLAddr=0x" TARGET_FMT_lx "\n", env->CP0_LLAddr);
if (!SIGN_EXT_P(env->lladdr))
cpu_fprintf(f, "BROKEN: LLAddr=0x" TARGET_FMT_lx "\n", env->lladdr);
}
#endif
@ -8526,7 +8526,7 @@ void cpu_dump_state (CPUState *env, FILE *f,
cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n",
env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
env->CP0_Config0, env->CP0_Config1, env->lladdr);
if (env->hflags & MIPS_HFLAG_FPU)
fpu_dump_state(env, f, cpu_fprintf, flags);
#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)