Move CPU save/load registration to common code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
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6913ba5680
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b3c7724cbc
5
exec.c
5
exec.c
@ -37,6 +37,7 @@
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#include "exec-all.h"
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#include "qemu-common.h"
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#include "tcg.h"
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#include "hw/hw.h"
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#if defined(CONFIG_USER_ONLY)
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#include <qemu.h>
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#endif
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@ -457,6 +458,10 @@ void cpu_exec_init(CPUState *env)
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env->cpu_index = cpu_index;
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env->nb_watchpoints = 0;
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*penv = env;
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#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
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register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
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cpu_save, cpu_load, env);
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#endif
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}
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static inline void invalidate_page_bitmap(PageDesc *p)
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@ -67,7 +67,6 @@ void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size,
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cpu_model = "crisv32";
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}
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env = cpu_init(cpu_model);
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register_savevm("cpu", 0, 1, cpu_save, cpu_load, env);
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qemu_register_reset(main_cpu_reset, env);
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/* allocate RAM */
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@ -146,7 +146,6 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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qemu_register_reset(main_cpu_reset, env);
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/* allocate RAM */
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@ -802,7 +802,6 @@ void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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qemu_register_reset(main_cpu_reset, env);
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/* allocate RAM */
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@ -129,7 +129,6 @@ mips_mipssim_init (ram_addr_t ram_size, int vga_ram_size,
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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qemu_register_reset(main_cpu_reset, env);
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/* Allocate RAM. */
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@ -175,7 +175,6 @@ void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size,
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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qemu_register_reset(main_cpu_reset, env);
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/* allocate RAM */
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1
hw/pc.c
1
hw/pc.c
@ -764,7 +764,6 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
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/* XXX: enable it in all cases */
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env->cpuid_features |= CPUID_APIC;
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}
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register_savevm("cpu", i, 5, cpu_save, cpu_load, env);
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qemu_register_reset(main_cpu_reset, env);
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if (pci_enabled) {
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apic_init(env);
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@ -56,7 +56,6 @@ CPUState *ppc4xx_init (const unsigned char *cpu_model,
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ppc_dcr_init(env, NULL, NULL);
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/* Register qemu callbacks */
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qemu_register_reset(&cpu_ppc_reset, env);
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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return env;
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}
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@ -103,7 +103,6 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
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env->osi_call = vga_osi_call;
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#endif
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qemu_register_reset(&cpu_ppc_reset, env);
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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envs[i] = env;
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}
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if (env->nip < 0xFFF80000) {
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@ -143,7 +143,6 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
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cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
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env->osi_call = vga_osi_call;
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qemu_register_reset(&cpu_ppc_reset, env);
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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envs[i] = env;
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}
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if (env->nip < 0xFFF80000) {
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@ -580,7 +580,6 @@ static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
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cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
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}
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qemu_register_reset(&cpu_ppc_reset, env);
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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envs[i] = env;
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}
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@ -2046,9 +2046,6 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load,
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s->env);
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s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
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/* SDRAM & Internal Memory Storage */
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@ -2173,9 +2170,6 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load,
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s->env);
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s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
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/* SDRAM & Internal Memory Storage */
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@ -426,7 +426,6 @@ static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
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qemu_register_reset(secondary_cpu_reset, env);
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env->halted = 1;
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}
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register_savevm("cpu", i, 4, cpu_save, cpu_load, env);
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cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
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env->prom_addr = hwdef->slavio_base;
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}
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@ -601,7 +600,6 @@ static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
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cpu_sparc_set_id(env, 0);
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qemu_register_reset(main_cpu_reset, env);
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register_savevm("cpu", 0, 4, cpu_save, cpu_load, env);
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cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
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env->prom_addr = hwdef->slavio_base;
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@ -1413,7 +1411,6 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
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qemu_register_reset(secondary_cpu_reset, env);
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env->halted = 1;
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}
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register_savevm("cpu", i, 4, cpu_save, cpu_load, env);
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cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
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env->prom_addr = hwdef->slavio_base;
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}
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@ -282,7 +282,6 @@ static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
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bh = qemu_bh_new(hstick_irq, env);
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env->hstick = ptimer_init(bh);
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ptimer_set_period(env->hstick, 1ULL);
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register_savevm("cpu", 0, 4, cpu_save, cpu_load, env);
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qemu_register_reset(main_cpu_reset, env);
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main_cpu_reset(env);
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@ -132,4 +132,8 @@ typedef struct SerialState SerialState;
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typedef struct IRQState *qemu_irq;
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struct pcmcia_card_s;
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/* CPU save/load. */
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void cpu_save(QEMUFile *f, void *opaque);
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int cpu_load(QEMUFile *f, void *opaque, int version_id);
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#endif
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3
sysemu.h
3
sysemu.h
@ -41,9 +41,6 @@ void qemu_system_powerdown(void);
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#endif
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void qemu_system_reset(void);
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void cpu_save(QEMUFile *f, void *opaque);
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int cpu_load(QEMUFile *f, void *opaque, int version_id);
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void do_savevm(const char *name);
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void do_loadvm(const char *name);
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void do_delvm(const char *name);
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@ -397,7 +397,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
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#define cpu_signal_handler cpu_arm_signal_handler
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#define cpu_list arm_cpu_list
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#define ARM_CPU_SAVE_VERSION 1
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#define CPU_SAVE_VERSION 1
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
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@ -120,7 +120,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
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CPUARMState *env = (CPUARMState *)opaque;
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int i;
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if (version_id != ARM_CPU_SAVE_VERSION)
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if (version_id != CPU_SAVE_VERSION)
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return -EINVAL;
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for (i = 0; i < 16; i++) {
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@ -210,6 +210,8 @@ enum {
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#define cpu_gen_code cpu_cris_gen_code
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#define cpu_signal_handler cpu_cris_signal_handler
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#define CPU_SAVE_VERSION 1
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _user
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@ -726,6 +726,8 @@ static inline int cpu_get_time_fast(void)
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#define cpu_signal_handler cpu_x86_signal_handler
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#define cpu_list x86_cpu_list
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#define CPU_SAVE_VERSION 5
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _user
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@ -489,6 +489,8 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
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#define cpu_signal_handler cpu_mips_signal_handler
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#define cpu_list mips_cpu_list
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#define CPU_SAVE_VERSION 3
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/* MMU modes definitions. We carefully match the indices with our
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hflags layout. */
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#define MMU_MODE0_SUFFIX _kernel
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@ -813,6 +813,8 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
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#define cpu_signal_handler cpu_ppc_signal_handler
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#define cpu_list ppc_cpu_list
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#define CPU_SAVE_VERSION 3
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _user
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#define MMU_MODE1_SUFFIX _kernel
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@ -388,6 +388,8 @@ void cpu_check_irqs(CPUSPARCState *env);
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#define cpu_signal_handler cpu_sparc_signal_handler
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#define cpu_list sparc_cpu_list
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#define CPU_SAVE_VERSION 4
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _user
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#define MMU_MODE1_SUFFIX _kernel
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