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Remove unused is_softmmu parameter from cpu_handle_mmu_fault

Browse Source 
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)
is not used in cpu_*_handle_mmu_fault() functions, remove them
and adjust callers.

Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2011-08-01 16:12:17 +00:00
parent 548f66db33
commit 97b348e7d2
39 changed files with 59 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target-alpha/cpu.h
View File

@ -426,7 +426,7 @@ int cpu_alpha_exec(CPUAlphaState *s);
int cpu_alpha_signal_handler(int host_signum, void *pinfo,
void *puc);
int cpu_alpha_handle_mmu_fault (CPUState *env, uint64_t address, int rw,
int mmu_idx, int is_softmmu);
int mmu_idx);
#define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
void do_interrupt (CPUState *env);

4
target-alpha/helper.c
View File

@ -160,7 +160,7 @@ void cpu_alpha_store_fpcr (CPUState *env, uint64_t val)
#if defined(CONFIG_USER_ONLY)
int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
env->exception_index = EXCP_MMFAULT;
env->trap_arg0 = address;
@ -316,7 +316,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
}
int cpu_alpha_handle_mmu_fault(CPUState *env, target_ulong addr, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
target_ulong phys;
int prot, fail;

2
target-alpha/op_helper.c
View File

@ -1344,7 +1344,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
generated code */
saved_env = env;
env = cpu_single_env;
ret = cpu_alpha_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ret = cpu_alpha_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret != 0)) {
do_restore_state(retaddr);
/* Exception index and error code are already set */

2
target-arm/cpu.h
View File

@ -244,7 +244,7 @@ uint32_t do_arm_semihosting(CPUARMState *env);
int cpu_arm_signal_handler(int host_signum, void *pinfo,
void *puc);
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
int mmu_idx, int is_softmuu);
int mmu_idx);
#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)

4
target-arm/helper.c
View File

@ -542,7 +542,7 @@ void do_interrupt (CPUState *env)
}
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
if (rw == 2) {
env->exception_index = EXCP_PREFETCH_ABORT;
@ -1254,7 +1254,7 @@ static inline int get_phys_addr(CPUState *env, uint32_t address,
}
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
int access_type, int mmu_idx, int is_softmmu)
int access_type, int mmu_idx)
{
uint32_t phys_addr;
target_ulong page_size;

2
target-arm/op_helper.c
View File

@ -86,7 +86,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
generated code */
saved_env = env;
env = cpu_single_env;
ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */

2
target-cris/cpu.h
View File

@ -226,7 +226,7 @@ static inline int cpu_mmu_index (CPUState *env)
}
int cpu_cris_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu);
int mmu_idx);
#define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
#if defined(CONFIG_USER_ONLY)

11
target-cris/helper.c
View File

@ -47,7 +47,7 @@ void do_interrupt (CPUState *env)
}
int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
env->exception_index = 0xaa;
env->pregs[PR_EDA] = address;
@ -68,7 +68,7 @@ static void cris_shift_ccs(CPUState *env)
}
int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
struct cris_mmu_result res;
int prot, miss;
@ -104,10 +104,9 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
r = 0;
}
if (r > 0)
D_LOG("%s returns %d irqreq=%x addr=%x"
" phy=%x ismmu=%d vec=%x pc=%x\n",
__func__, r, env->interrupt_request,
address, res.phy, is_softmmu, res.bf_vec, env->pc);
D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n",
__func__, r, env->interrupt_request, address, res.phy,
res.bf_vec, env->pc);
return r;
}

2
target-cris/op_helper.c
View File

@ -70,7 +70,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__,
env->pc, env->debug1, retaddr);
ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */

2
target-i386/cpu.h
View File

@ -889,7 +889,7 @@ void host_cpuid(uint32_t function, uint32_t count,
/* helper.c */
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
int is_write, int mmu_idx, int is_softmmu);
int is_write, int mmu_idx);
#define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
void cpu_x86_set_a20(CPUX86State *env, int a20_state);

4
target-i386/helper.c
View File

@ -546,7 +546,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
#if defined(CONFIG_USER_ONLY)
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
int is_write, int mmu_idx, int is_softmmu)
int is_write, int mmu_idx)
{
/* user mode only emulation */
is_write &= 1;
@ -573,7 +573,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
1 = generate PF fault
*/
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
int is_write1, int mmu_idx, int is_softmmu)
int is_write1, int mmu_idx)
{
uint64_t ptep, pte;
target_ulong pde_addr, pte_addr;

2
target-i386/op_helper.c
View File

@ -5009,7 +5009,7 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
saved_env = env;
env = cpu_single_env;
ret = cpu_x86_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ret = cpu_x86_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (ret) {
if (retaddr) {
/* now we have a real cpu fault */

2
target-lm32/cpu.h
View File

@ -205,7 +205,7 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value);
#define CPU_SAVE_VERSION 1
int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu);
int mmu_idx);
#define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
#if defined(CONFIG_USER_ONLY)

2
target-lm32/helper.c
View File

@ -26,7 +26,7 @@
#include "host-utils.h"
int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
int prot;

2
target-lm32/op_helper.c
View File

@ -87,7 +87,7 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
saved_env = env;
env = cpu_single_env;
ret = cpu_lm32_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ret = cpu_lm32_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */

2
target-m68k/cpu.h
View File

@ -231,7 +231,7 @@ static inline int cpu_mmu_index (CPUState *env)
}
int cpu_m68k_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu);
int mmu_idx);
#define cpu_handle_mmu_fault cpu_m68k_handle_mmu_fault
#if defined(CONFIG_USER_ONLY)

4
target-m68k/helper.c
View File

@ -344,7 +344,7 @@ void m68k_switch_sp(CPUM68KState *env)
#if defined(CONFIG_USER_ONLY)
int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
env->exception_index = EXCP_ACCESS;
env->mmu.ar = address;
@ -362,7 +362,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
}
int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
int prot;

2
target-m68k/op_helper.c
View File

@ -66,7 +66,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
generated code */
saved_env = env;
env = cpu_single_env;
ret = cpu_m68k_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ret = cpu_m68k_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */

2
target-microblaze/cpu.h
View File

@ -309,7 +309,7 @@ static inline int cpu_mmu_index (CPUState *env)
}
int cpu_mb_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu);
int mmu_idx);
#define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
#if defined(CONFIG_USER_ONLY)

4
target-microblaze/helper.c
View File

@ -37,7 +37,7 @@ void do_interrupt (CPUState *env)
}
int cpu_mb_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
env->exception_index = 0xaa;
cpu_dump_state(env, stderr, fprintf, 0);
@ -47,7 +47,7 @@ int cpu_mb_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
#else /* !CONFIG_USER_ONLY */
int cpu_mb_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
unsigned int hit;
unsigned int mmu_available;

2
target-microblaze/op_helper.c
View File

@ -54,7 +54,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
saved_env = env;
env = cpu_single_env;
ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */

2
target-mips/cpu.h
View File

@ -636,7 +636,7 @@ void cpu_mips_soft_irq(CPUState *env, int irq, int level);
/* helper.c */
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu);
int mmu_idx);
#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
void do_interrupt (CPUState *env);
#if !defined(CONFIG_USER_ONLY)

6
target-mips/helper.c
View File

@ -266,7 +266,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
#endif
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
#if !defined(CONFIG_USER_ONLY)
target_phys_addr_t physical;
@ -278,8 +278,8 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
#if 0
log_cpu_state(env, 0);
#endif
qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n",
__func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu);
qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d\n",
__func__, env->active_tc.PC, address, rw, mmu_idx);
rw &= 1;

2
target-mips/op_helper.c
View File

@ -2017,7 +2017,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
generated code */
saved_env = env;
env = cpu_single_env;
ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (ret) {
if (retaddr) {
/* now we have a real cpu fault */

2
target-ppc/cpu.h
View File

@ -1022,7 +1022,7 @@ void cpu_ppc_close (CPUPPCState *s);
int cpu_ppc_signal_handler (int host_signum, void *pinfo,
void *puc);
int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu);
int mmu_idx);
#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
#if !defined(CONFIG_USER_ONLY)
int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,

4
target-ppc/helper.c
View File

@ -78,7 +78,7 @@ void (*cpu_ppc_hypercall)(CPUState *);
#if defined(CONFIG_USER_ONLY)
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
int exception, error_code;
@ -1658,7 +1658,7 @@ static void booke206_update_mas_tlb_miss(CPUState *env, target_ulong address,
/* Perform address translation */
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
mmu_ctx_t ctx;
int access_type;

2
target-ppc/op_helper.c
View File

@ -3725,7 +3725,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
generated code */
saved_env = env;
env = cpu_single_env;
ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret != 0)) {
if (likely(retaddr)) {
/* now we have a real cpu fault */

2
target-s390x/cpu.h
View File

@ -280,7 +280,7 @@ void do_interrupt (CPUState *env);
int cpu_s390x_signal_handler(int host_signum, void *pinfo,
void *puc);
int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
int mmu_idx, int is_softmuu);
int mmu_idx);
#define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault

12
target-s390x/helper.c
View File

@ -110,10 +110,10 @@ void do_interrupt (CPUState *env)
}
int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
/* fprintf(stderr,"%s: address 0x%lx rw %d mmu_idx %d is_softmmu %d\n",
__FUNCTION__, address, rw, mmu_idx, is_softmmu); */
/* fprintf(stderr,"%s: address 0x%lx rw %d mmu_idx %d\n",
__FUNCTION__, address, rw, mmu_idx); */
env->exception_index = EXCP_ADDR;
env->__excp_addr = address; /* FIXME: find out how this works on a real machine */
return 1;
@ -394,14 +394,14 @@ out:
}
int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong _vaddr, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
uint64_t asc = env->psw.mask & PSW_MASK_ASC;
target_ulong vaddr, raddr;
int prot;
DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d is_softmmu %d\n",
__FUNCTION__, _vaddr, rw, mmu_idx, is_softmmu);
DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
__FUNCTION__, _vaddr, rw, mmu_idx);
_vaddr &= TARGET_PAGE_MASK;
vaddr = _vaddr;

2
target-s390x/op_helper.c
View File

@ -63,7 +63,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
generated code */
saved_env = env;
env = cpu_single_env;
ret = cpu_s390x_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ret = cpu_s390x_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret != 0)) {
if (likely(retaddr)) {
/* now we have a real cpu fault */

2
target-sh4/cpu.h
View File

@ -194,7 +194,7 @@ int cpu_sh4_exec(CPUSH4State * s);
int cpu_sh4_signal_handler(int host_signum, void *pinfo,
void *puc);
int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
int mmu_idx, int is_softmmu);
int mmu_idx);
#define cpu_handle_mmu_fault cpu_sh4_handle_mmu_fault
void do_interrupt(CPUSH4State * env);

4
target-sh4/helper.c
View File

@ -34,7 +34,7 @@ void do_interrupt (CPUState *env)
}
int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
env->tea = address;
env->exception_index = -1;
@ -440,7 +440,7 @@ static int get_physical_address(CPUState * env, target_ulong * physical,
}
int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
target_ulong physical;
int prot, ret, access_type;

2
target-sh4/op_helper.c
View File

@ -64,7 +64,7 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
generated code */
saved_env = env;
env = cpu_single_env;
ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (ret) {
/* now we have a real cpu fault */
cpu_restore_state_from_retaddr(retaddr);

2
target-sparc/cpu.h
View File

@ -490,7 +490,7 @@ CPUSPARCState *cpu_sparc_init(const char *cpu_model);
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
int mmu_idx, int is_softmmu);
int mmu_idx);
#define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env);

6
target-sparc/helper.c
View File

@ -42,7 +42,7 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
#if defined(CONFIG_USER_ONLY)
int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
if (rw & 2)
env1->exception_index = TT_TFAULT;
@ -212,7 +212,7 @@ static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
/* Perform address translation */
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
target_phys_addr_t paddr;
target_ulong vaddr;
@ -638,7 +638,7 @@ static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
/* Perform address translation */
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
target_ulong virt_addr, vaddr;
target_phys_addr_t paddr;

2
target-sparc/op_helper.c
View File

@ -4237,7 +4237,7 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
saved_env = env;
env = cpu_single_env;
ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (ret) {
cpu_restore_state2(retaddr);
cpu_loop_exit(env);

2
target-unicore32/cpu.h
View File

@ -130,7 +130,7 @@ CPUState *uc32_cpu_init(const char *cpu_model);
int uc32_cpu_exec(CPUState *s);
int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmuu);
int mmu_idx);
#define CPU_SAVE_VERSION 2

2
target-unicore32/helper.c
View File

@ -104,7 +104,7 @@ void do_interrupt(CPUState *env)
}
int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
int mmu_idx)
{
env->exception_index = UC32_EXCP_TRAP;
env->cp0.c4_faultaddr = address;

2
user-exec.c
View File

@ -102,7 +102,7 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
}
/* see if it is an MMU fault */
ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX);
if (ret < 0) {
return 0; /* not an MMU fault */
}