mirror of https://gitlab.com/qemu-project/qemu
target-mips: move ROTR and ROTRV inside gen_shift_{imm, }
It's easier to implement mips16 shift instructions if we're not
examining the opcode inside gen_shift_{imm,}. So move ROTR and ROTRV
and do the special-case handling of SRL and SRLV inside decode_opc.
Likewise for their 64-bit counterparts.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Nathan Froyd
Aurelien Jarno
parent
32188a03da
commit
ea63e2c358
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@ -128,18 +128,23 @@ enum {
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/* SSNOP is SLL r0, r0, 1 */
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/* EHB is SLL r0, r0, 3 */
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OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */
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OPC_ROTR = OPC_SRL | (1 << 21),
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OPC_SRA = 0x03 | OPC_SPECIAL,
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OPC_SLLV = 0x04 | OPC_SPECIAL,
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OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */
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OPC_ROTRV = OPC_SRLV | (1 << 6),
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OPC_SRAV = 0x07 | OPC_SPECIAL,
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OPC_DSLLV = 0x14 | OPC_SPECIAL,
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OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */
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OPC_DROTRV = OPC_DSRLV | (1 << 6),
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OPC_DSRAV = 0x17 | OPC_SPECIAL,
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OPC_DSLL = 0x38 | OPC_SPECIAL,
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OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */
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OPC_DROTR = OPC_DSRL | (1 << 21),
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OPC_DSRA = 0x3B | OPC_SPECIAL,
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OPC_DSLL32 = 0x3C | OPC_SPECIAL,
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OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */
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OPC_DROTR32 = OPC_DSRL32 | (1 << 21),
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OPC_DSRA32 = 0x3F | OPC_SPECIAL,
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/* Multiplication / division */
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OPC_MULT = 0x18 | OPC_SPECIAL,
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@ -1431,43 +1436,24 @@ static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
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opn = "sra";
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break;
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case OPC_SRL:
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switch ((ctx->opcode >> 21) & 0x1f) {
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case 0:
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if (uimm != 0) {
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tcg_gen_ext32u_tl(t0, t0);
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tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
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} else {
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tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
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}
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opn = "srl";
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break;
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case 1:
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/* rotr is decoded as srl on non-R2 CPUs */
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if (env->insn_flags & ISA_MIPS32R2) {
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if (uimm != 0) {
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TCGv_i32 t1 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t1, t0);
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tcg_gen_rotri_i32(t1, t1, uimm);
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tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
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tcg_temp_free_i32(t1);
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}
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opn = "rotr";
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} else {
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if (uimm != 0) {
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tcg_gen_ext32u_tl(t0, t0);
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tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
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} else {
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tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
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}
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opn = "srl";
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}
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break;
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default:
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MIPS_INVAL("invalid srl flag");
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generate_exception(ctx, EXCP_RI);
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break;
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if (uimm != 0) {
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tcg_gen_ext32u_tl(t0, t0);
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tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
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} else {
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tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
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}
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opn = "srl";
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break;
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case OPC_ROTR:
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if (uimm != 0) {
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TCGv_i32 t1 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t1, t0);
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tcg_gen_rotri_i32(t1, t1, uimm);
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tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
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tcg_temp_free_i32(t1);
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}
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opn = "rotr";
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break;
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#if defined(TARGET_MIPS64)
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case OPC_DSLL:
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@ -1479,28 +1465,14 @@ static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
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opn = "dsra";
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break;
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case OPC_DSRL:
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switch ((ctx->opcode >> 21) & 0x1f) {
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case 0:
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tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
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opn = "dsrl";
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break;
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case 1:
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/* drotr is decoded as dsrl on non-R2 CPUs */
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if (env->insn_flags & ISA_MIPS32R2) {
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if (uimm != 0) {
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tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm);
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}
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opn = "drotr";
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} else {
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tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
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opn = "dsrl";
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}
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break;
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default:
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MIPS_INVAL("invalid dsrl flag");
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generate_exception(ctx, EXCP_RI);
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break;
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tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
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opn = "dsrl";
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break;
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case OPC_DROTR:
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if (uimm != 0) {
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tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm);
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}
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opn = "drotr";
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break;
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case OPC_DSLL32:
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tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32);
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@ -1511,26 +1483,12 @@ static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
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opn = "dsra32";
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break;
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case OPC_DSRL32:
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switch ((ctx->opcode >> 21) & 0x1f) {
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case 0:
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tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32);
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opn = "dsrl32";
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break;
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case 1:
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/* drotr32 is decoded as dsrl32 on non-R2 CPUs */
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if (env->insn_flags & ISA_MIPS32R2) {
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tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32);
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opn = "drotr32";
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} else {
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tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32);
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opn = "dsrl32";
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}
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break;
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default:
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MIPS_INVAL("invalid dsrl32 flag");
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generate_exception(ctx, EXCP_RI);
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break;
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}
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tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32);
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opn = "dsrl32";
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break;
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case OPC_DROTR32:
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tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32);
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opn = "drotr32";
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break;
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#endif
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}
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@ -1879,40 +1837,25 @@ static void gen_shift (CPUState *env, DisasContext *ctx, uint32_t opc,
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opn = "srav";
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break;
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case OPC_SRLV:
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switch ((ctx->opcode >> 6) & 0x1f) {
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case 0:
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tcg_gen_ext32u_tl(t1, t1);
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tcg_gen_andi_tl(t0, t0, 0x1f);
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tcg_gen_shr_tl(t0, t1, t0);
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tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
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opn = "srlv";
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break;
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case 1:
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/* rotrv is decoded as srlv on non-R2 CPUs */
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if (env->insn_flags & ISA_MIPS32R2) {
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TCGv_i32 t2 = tcg_temp_new_i32();
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TCGv_i32 t3 = tcg_temp_new_i32();
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tcg_gen_ext32u_tl(t1, t1);
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tcg_gen_andi_tl(t0, t0, 0x1f);
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tcg_gen_shr_tl(t0, t1, t0);
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tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
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opn = "srlv";
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break;
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case OPC_ROTRV:
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{
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TCGv_i32 t2 = tcg_temp_new_i32();
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TCGv_i32 t3 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t2, t0);
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tcg_gen_trunc_tl_i32(t3, t1);
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tcg_gen_andi_i32(t2, t2, 0x1f);
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tcg_gen_rotr_i32(t2, t3, t2);
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tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
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tcg_temp_free_i32(t2);
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tcg_temp_free_i32(t3);
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opn = "rotrv";
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} else {
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tcg_gen_ext32u_tl(t1, t1);
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tcg_gen_andi_tl(t0, t0, 0x1f);
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tcg_gen_shr_tl(t0, t1, t0);
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tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
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opn = "srlv";
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}
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break;
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default:
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MIPS_INVAL("invalid srlv flag");
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generate_exception(ctx, EXCP_RI);
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break;
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tcg_gen_trunc_tl_i32(t2, t0);
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tcg_gen_trunc_tl_i32(t3, t1);
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tcg_gen_andi_i32(t2, t2, 0x1f);
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tcg_gen_rotr_i32(t2, t3, t2);
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tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
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tcg_temp_free_i32(t2);
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tcg_temp_free_i32(t3);
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opn = "rotrv";
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}
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break;
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#if defined(TARGET_MIPS64)
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@ -1927,29 +1870,14 @@ static void gen_shift (CPUState *env, DisasContext *ctx, uint32_t opc,
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opn = "dsrav";
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break;
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case OPC_DSRLV:
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switch ((ctx->opcode >> 6) & 0x1f) {
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case 0:
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tcg_gen_andi_tl(t0, t0, 0x3f);
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tcg_gen_shr_tl(cpu_gpr[rd], t1, t0);
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opn = "dsrlv";
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break;
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case 1:
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/* drotrv is decoded as dsrlv on non-R2 CPUs */
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if (env->insn_flags & ISA_MIPS32R2) {
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tcg_gen_andi_tl(t0, t0, 0x3f);
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tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0);
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opn = "drotrv";
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} else {
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tcg_gen_andi_tl(t0, t0, 0x3f);
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tcg_gen_shr_tl(t0, t1, t0);
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opn = "dsrlv";
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}
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break;
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default:
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MIPS_INVAL("invalid dsrlv flag");
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generate_exception(ctx, EXCP_RI);
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break;
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}
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tcg_gen_andi_tl(t0, t0, 0x3f);
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tcg_gen_shr_tl(cpu_gpr[rd], t1, t0);
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opn = "dsrlv";
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break;
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case OPC_DROTRV:
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tcg_gen_andi_tl(t0, t0, 0x3f);
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tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0);
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opn = "drotrv";
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break;
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#endif
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}
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@ -7661,9 +7589,24 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
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switch (op1) {
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case OPC_SLL: /* Shift with immediate */
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case OPC_SRA:
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case OPC_SRL:
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gen_shift_imm(env, ctx, op1, rd, rt, sa);
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break;
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case OPC_SRL:
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switch ((ctx->opcode >> 21) & 0x1f) {
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case 1:
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/* rotr is decoded as srl on non-R2 CPUs */
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if (env->insn_flags & ISA_MIPS32R2) {
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op1 = OPC_ROTR;
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}
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/* Fallthrough */
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case 0:
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gen_shift_imm(env, ctx, op1, rd, rt, sa);
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break;
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default:
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generate_exception(ctx, EXCP_RI);
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break;
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}
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break;
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case OPC_MOVN: /* Conditional move */
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case OPC_MOVZ:
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check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
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@ -7673,10 +7616,25 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
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gen_arith(env, ctx, op1, rd, rs, rt);
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break;
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case OPC_SLLV: /* Shifts */
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case OPC_SRLV:
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case OPC_SRAV:
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gen_shift(env, ctx, op1, rd, rs, rt);
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break;
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case OPC_SRLV:
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switch ((ctx->opcode >> 6) & 0x1f) {
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case 1:
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/* rotrv is decoded as srlv on non-R2 CPUs */
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if (env->insn_flags & ISA_MIPS32R2) {
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op1 = OPC_ROTRV;
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}
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/* Fallthrough */
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case 0:
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gen_shift(env, ctx, op1, rd, rs, rt);
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break;
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default:
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generate_exception(ctx, EXCP_RI);
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break;
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}
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break;
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case OPC_SLT: /* Set on less than */
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case OPC_SLTU:
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gen_slt(env, op1, rd, rs, rt);
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@ -7754,14 +7712,48 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
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/* MIPS64 specific opcodes */
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case OPC_DSLL:
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case OPC_DSRA:
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case OPC_DSRL:
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case OPC_DSLL32:
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case OPC_DSRA32:
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case OPC_DSRL32:
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check_insn(env, ctx, ISA_MIPS3);
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check_mips_64(ctx);
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gen_shift_imm(env, ctx, op1, rd, rt, sa);
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break;
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case OPC_DSRL:
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switch ((ctx->opcode >> 21) & 0x1f) {
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case 1:
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/* drotr is decoded as dsrl on non-R2 CPUs */
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if (env->insn_flags & ISA_MIPS32R2) {
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op1 = OPC_DROTR;
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}
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/* Fallthrough */
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case 0:
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check_insn(env, ctx, ISA_MIPS3);
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check_mips_64(ctx);
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gen_shift_imm(env, ctx, op1, rd, rt, sa);
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break;
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default:
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generate_exception(ctx, EXCP_RI);
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break;
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}
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break;
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case OPC_DSRL32:
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switch ((ctx->opcode >> 21) & 0x1f) {
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case 1:
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/* drotr32 is decoded as dsrl32 on non-R2 CPUs */
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if (env->insn_flags & ISA_MIPS32R2) {
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op1 = OPC_DROTR32;
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}
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/* Fallthrough */
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case 0:
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check_insn(env, ctx, ISA_MIPS3);
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check_mips_64(ctx);
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gen_shift_imm(env, ctx, op1, rd, rt, sa);
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break;
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default:
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generate_exception(ctx, EXCP_RI);
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break;
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}
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break;
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case OPC_DADD ... OPC_DSUBU:
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check_insn(env, ctx, ISA_MIPS3);
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check_mips_64(ctx);
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@ -7769,11 +7761,28 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
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break;
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case OPC_DSLLV:
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case OPC_DSRAV:
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case OPC_DSRLV:
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check_insn(env, ctx, ISA_MIPS3);
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check_mips_64(ctx);
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gen_shift(env, ctx, op1, rd, rs, rt);
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break;
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case OPC_DSRLV:
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switch ((ctx->opcode >> 6) & 0x1f) {
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case 1:
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/* drotrv is decoded as dsrlv on non-R2 CPUs */
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if (env->insn_flags & ISA_MIPS32R2) {
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op1 = OPC_DROTRV;
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}
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/* Fallthrough */
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case 0:
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check_insn(env, ctx, ISA_MIPS3);
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check_mips_64(ctx);
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gen_shift(env, ctx, op1, rd, rs, rt);
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break;
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default:
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generate_exception(ctx, EXCP_RI);
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break;
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}
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break;
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case OPC_DMULT ... OPC_DDIVU:
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check_insn(env, ctx, ISA_MIPS3);
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check_mips_64(ctx);
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