qemu/target-mips
Nathan Froyd 7b270ef2a3 target-mips: fix single-stepping
Single-stepping branches on MIPS didn't work right, because the
generation of EXCP_DEBUG happened after the generation of the code to
exit the current TB.  That is, given the code:

    bne v0,v1,target
    nop
    ...
  target:
    addu v0,v0,v1
  1:

when you single-stepped through the NOP, execution wouldn't actually
halt until you reached the label `1'.

This patch corrects that and also changes single-stepping so that a
branch and its delay slot are executed as one instruction for the
purposes of single-stepping.  This behavior is comparable to what other
MIPS tools (e.g. MIPSsim with MDI) do.  GDB avoids placing breakpoints
in branch delay slots, so this change doesn't break anything on the GDB
side.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-14 19:34:12 +02:00
..
cpu.h cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal 2009-08-24 08:21:42 -05:00
exec.h qemu: per-arch cpu_has_work (Marcelo Tosatti) 2009-04-24 18:03:20 +00:00
helper.c Update to a hopefully more future proof FSF address 2009-07-16 20:47:01 +00:00
helper.h target-mips: use the TCG_CALL_PURE and TCG_CALL_CONST for some helpers 2009-04-06 12:34:07 +00:00
machine.c Fix a warning: uint_fast8_t is not 8 bits on OpenBSD/Sparc64 2009-06-13 15:09:38 +00:00
mips-defs.h Hardware convenience library 2009-05-19 16:17:58 +01:00
op_helper.c Update to a hopefully more future proof FSF address 2009-07-16 20:47:01 +00:00
TODO Move the active FPU registers into env again, and use more TCG registers 2008-09-18 11:57:27 +00:00
translate_init.c Update to a hopefully more future proof FSF address 2009-07-16 20:47:01 +00:00
translate.c target-mips: fix single-stepping 2009-09-14 19:34:12 +02:00