Add concat_i32_i64 op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
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pbrook
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436d124b7d
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36aa55dcd9
@ -1447,10 +1447,7 @@ static void gen_iwmmxt_movl_T0_T1_wRn(int rn)
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static void gen_iwmmxt_movl_wRn_T0_T1(int rn)
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{
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tcg_gen_extu_i32_i64(cpu_V0, cpu_T[0]);
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tcg_gen_extu_i32_i64(cpu_V1, cpu_T[0]);
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tcg_gen_shli_i64(cpu_V1, cpu_V1, 32);
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tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
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tcg_gen_concat_i32_i64(cpu_V0, cpu_T[0], cpu_T[1]);
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iwmmxt_store_reg(cpu_V0, rn);
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}
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@ -4663,14 +4660,11 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
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} else {
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tmp = neon_load_reg(rm + pass, 0);
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gen_neon_shift_narrow(size, tmp, tmp2, q, u);
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tcg_gen_extu_i32_i64(cpu_V0, tmp);
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tmp3 = neon_load_reg(rm + pass, 1);
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gen_neon_shift_narrow(size, tmp3, tmp2, q, u);
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tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
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dead_tmp(tmp);
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tmp = neon_load_reg(rm + pass, 1);
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gen_neon_shift_narrow(size, tmp, tmp2, q, u);
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tcg_gen_extu_i32_i64(cpu_V1, tmp);
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dead_tmp(tmp);
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tcg_gen_shli_i64(cpu_V1, cpu_V1, 32);
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tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
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dead_tmp(tmp3);
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}
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tmp = new_tmp();
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if (op == 8 && !u) {
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@ -5600,7 +5594,7 @@ static void gen_addq_lo(DisasContext *s, TCGv val, int rlow)
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TCGv tmp;
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TCGv tmp2;
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/* Load 64-bit value rd:rn. */
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/* Load value and extend to 64 bits. */
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tmp = tcg_temp_new(TCG_TYPE_I64);
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tmp2 = load_reg(s, rlow);
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tcg_gen_extu_i32_i64(tmp, tmp2);
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@ -5612,19 +5606,16 @@ static void gen_addq_lo(DisasContext *s, TCGv val, int rlow)
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static void gen_addq(DisasContext *s, TCGv val, int rlow, int rhigh)
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{
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TCGv tmp;
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TCGv tmp2;
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TCGv tmpl;
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TCGv tmph;
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/* Load 64-bit value rd:rn. */
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tmpl = load_reg(s, rlow);
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tmph = load_reg(s, rhigh);
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tmp = tcg_temp_new(TCG_TYPE_I64);
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tmp2 = load_reg(s, rhigh);
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tcg_gen_extu_i32_i64(tmp, tmp2);
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dead_tmp(tmp2);
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tcg_gen_shli_i64(tmp, tmp, 32);
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tcg_gen_add_i64(val, val, tmp);
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tmp2 = load_reg(s, rlow);
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tcg_gen_extu_i32_i64(tmp, tmp2);
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dead_tmp(tmp2);
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tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
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dead_tmp(tmpl);
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dead_tmp(tmph);
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tcg_gen_add_i64(val, val, tmp);
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}
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@ -693,13 +693,7 @@ static inline void gen_load_fpr64 (DisasContext *ctx, TCGv t, int reg)
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if (ctx->hflags & MIPS_HFLAG_F64)
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tcg_gen_mov_i64(t, fpu_fpr64[reg]);
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else {
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TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
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tcg_gen_extu_i32_i64(t, fpu_fpr32[reg | 1]);
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tcg_gen_shli_i64(t, t, 32);
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tcg_gen_extu_i32_i64(r_tmp2, fpu_fpr32[reg & ~1]);
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tcg_gen_or_i64(t, t, r_tmp2);
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tcg_temp_free(r_tmp2);
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tcg_gen_concat_i32_i64(t, fpu_fpr32[reg & ~1], fpu_fpr32[reg | 1]);
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}
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}
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@ -6546,22 +6540,17 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
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case FOP(38, 16):
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check_cp1_64bitmode(ctx);
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{
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TCGv fp64_0 = tcg_temp_new(TCG_TYPE_I64);
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TCGv fp64_1 = tcg_temp_new(TCG_TYPE_I64);
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TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
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TCGv fp32_0 = tcg_temp_new(TCG_TYPE_I32);
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TCGv fp32_1 = tcg_temp_new(TCG_TYPE_I32);
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gen_load_fpr32(fp32_0, fs);
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gen_load_fpr32(fp32_1, ft);
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tcg_gen_extu_i32_i64(fp64_0, fp32_0);
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tcg_gen_extu_i32_i64(fp64_1, fp32_1);
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tcg_temp_free(fp32_0);
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tcg_gen_concat_i32_i64(fp64, fp32_0, fp32_1);
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tcg_temp_free(fp32_1);
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tcg_gen_shli_i64(fp64_1, fp64_1, 32);
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tcg_gen_or_i64(fp64_0, fp64_0, fp64_1);
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tcg_temp_free(fp64_1);
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gen_store_fpr64(ctx, fp64_0, fd);
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tcg_temp_free(fp64_0);
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tcg_temp_free(fp32_0);
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gen_store_fpr64(ctx, fp64, fd);
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tcg_temp_free(fp64);
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}
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opn = "cvt.ps.s";
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break;
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@ -5300,12 +5300,7 @@ static always_inline void gen_load_gpr64(TCGv t, int reg) {
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#if defined(TARGET_PPC64)
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tcg_gen_mov_i64(t, cpu_gpr[reg]);
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#else
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tcg_gen_extu_i32_i64(t, cpu_gprh[reg]);
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tcg_gen_shli_i64(t, t, 32);
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TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64);
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tcg_gen_extu_i32_i64(tmp, cpu_gpr[reg]);
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tcg_gen_or_i64(t, t, tmp);
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tcg_temp_free(tmp);
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tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
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#endif
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}
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@ -400,15 +400,12 @@ static inline void gen_load_fpr32(TCGv t, int reg)
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static inline void gen_load_fpr64(TCGv t, int reg)
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{
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TCGv tmp1 = tcg_temp_new(TCG_TYPE_I32);
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TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64);
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TCGv tmp2 = tcg_temp_new(TCG_TYPE_I32);
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tcg_gen_ld_i32(tmp1, cpu_env, offsetof(CPUState, fregs[reg]));
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tcg_gen_extu_i32_i64(t, tmp1);
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tcg_gen_shli_i64(t, t, 32);
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tcg_gen_ld_i32(tmp1, cpu_env, offsetof(CPUState, fregs[reg + 1]));
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tcg_gen_extu_i32_i64(tmp2, tmp1);
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tcg_gen_ld_i32(tmp2, cpu_env, offsetof(CPUState, fregs[reg + 1]));
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tcg_gen_concat_i32_i64(t, tmp2, tmp1);
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tcg_temp_free(tmp1);
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tcg_gen_or_i64(t, t, tmp2);
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tcg_temp_free(tmp2);
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}
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@ -265,6 +265,10 @@ Convert t1 (32 bit) to t0 (64 bit) and does zero extension
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* trunc_i64_i32 t0, t1
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Truncate t1 (64 bit) to t0 (32 bit)
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* concat_i32_i64 t0, t1, t2
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Construct t0 (64-bit) taking the low half from t1 (32 bit) and the high half
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from t2 (32 bit).
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********* Load/Store
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* ld_i32/i64 t0, t1, offset
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17
tcg/tcg-op.h
17
tcg/tcg-op.h
@ -1395,6 +1395,23 @@ static inline void tcg_gen_discard_i64(TCGv arg)
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}
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#endif
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static inline void tcg_gen_concat_i32_i64(TCGv dest, TCGv low, TCGv high)
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{
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#if TCG_TARGET_REG_BITS == 32
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tcg_gen_mov_i32(dest, low);
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tcg_gen_mov_i32(TCGV_HIGH(dest), high);
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#else
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TCGv tmp = tcg_temp_new (TCG_TYPE_I64);
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/* This extension is only needed for type correctness.
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We may be able to do better given target specific information. */
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tcg_gen_extu_i32_i64(tmp, high);
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tcg_gen_shli_i64(tmp, tmp, 32);
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tcg_gen_extu_i32_i64(dest, low);
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tcg_gen_or_i64(dest, dest, tmp);
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tcg_temp_free(tmp);
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#endif
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}
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/***************************************/
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/* QEMU specific operations. Their type depend on the QEMU CPU
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type. */
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