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3913 Commits

Author SHA1 Message Date
Shwartsman
672c93c7c4 reduce code duplication using new CPUID methods 2023-10-07 01:02:39 +03:00
Shwartsman
5fc6302b1b add one more CPUID method for future use + fix compilation after prev commit 2023-10-07 00:10:18 +03:00
Shwartsman
f50419429d Fix code duplication for CPUID ECX leaf 0x1, implement with common function for all CPUs 2023-10-06 22:53:30 +03:00
Dreg
86eff7597d
add iodebug support for all rings complement #64 (#66) 
This PR is for "I/O Interface to Bochs Debugger" from ring3 (port range:
**0x8A00 - 0x8A01**)

PR #64 was for E9 HACK (port **0xE9**)

By enabling the iodebug's 'all_rings' option, you can utilize the port
I/O Interface to Bochs Debugger from ring3. This PR allows the code
running inside Bochs (ring3) to monitor memory ranges, trace individual
instructions, and observe register values during execution.


https://bochs.sourceforge.io/doc/docbook/development/debugger-advanced.html

IMO very useful for:

- user-mode sandbox (ex Cuckoo)
- malware analysis
- API/SYSCALL hook/monitor from ring3
- automation + instrumentation from user mode code
...

A complement for PR #64

**This PR is 100% backward compatibility**

![IODEBUG ALL
RINGS](https://github.com/bochs-emu/Bochs/assets/9882181/6308ad0f-c189-43f3-a92b-dccde3542ad6)

btw, @stlintel I'm not certain about:
- if misc is the ideal location for this.. should I create a new
iodebug-option for this?
- should I remove the #if in 'new bx_param_bool_c'?
- the new .bochsrc entry makes sense for you?
 2023-08-27 18:34:01 +02:00
Dreg
da43cc4580
add port e9 hack support for all rings (#64) 
By enabling the 'all_rings' option, you can utilize the port e9 hack
from ring3

IMO very useful for:
- user-mode sandbox (ex Cuckoo)
- malware analysis
- API/SYSCALL logger with a simple hook from ring3
- automation + instrumentation from user mode code
- ...

So yes, from this PR a user-mode-sandbox can display on the console of
the system running Bochs anything that is written to 0xE9 port


![porte9hackallrings](https://github.com/bochs-emu/Bochs/assets/9882181/ddbca3fa-729b-4a3e-95ad-078e44c7a17a)

**This PR is 100% backward compatibility**

btw, @stlintel I'm not certain if **bochs/config.cc** is the ideal
location to define **bool port_e9_hack_all_rings** (unmapped io/dev is
better?)
 2023-08-26 18:37:55 +03:00
Stanislav Shwartsman
253882589d extend cpuid enums with new bits announced in Intel SDM 2023-08-20 20:30:01 +03:00
Stanislav Shwartsman
1dcae848d7 change nullptr to NULL to help some old hosts not supporting C++ standard 2023-08-20 19:40:08 +03:00
Stanislav Shwartsman
6481d24e06 Another cleaner way to implemented fix by rei141 
from Fixes in VM Entry Checks for Guest Segment Registers #51

Correction in checks for Code Segment (CS):
Previously, the DPL of CS was incorrectly compared with its own RPL.
According to Intel SDM, Vol. 3C, Chapter 27.3.1.2, for non-conforming code segments (type 9 or 11), the DPL of CS should be equal to the DPL of SS.
And for conforming code segments (type 13 or 15), the DPL of CS cannot be greater than the DPL of SS.

This way VMCS is not accessed multiple times which is important for some usages
 2023-08-20 19:33:37 +03:00
Stanislav Shwartsman
58c047c6d6 Merge part of PR by rei141 
Fixes in VM Entry Checks for Guest Segment Registers #51

Correction in Type range checks for DS, ES, FS, GS:
The original code erroneously applied the check for types less than 11, excluding types equal to 11.
This is not in accordance with Intel SDM, Vol. 3C, Chapter 27.3.1.2, which states that the check should include types equal to or less than 11.
This fix corrects this by including types equal to or less than 11 in the check.
 2023-08-20 18:52:53 +03:00
Dreg
244033e234
improvement of the magic breakpoints fix #55 (#58) 2023-08-20 18:21:16 +03:00
disba1ancer
c11006ad51 Fixed instruction pointer truncation in gdbstub 2023-05-25 00:00:24 +03:00
Shwartsman
bd51ec5f83 fixed SF #1456 Bochs does not handle NMI blocking correctly when running virtual machines 2023-04-08 08:36:28 +03:00
Stanislav Shwartsman
e2f4eff91a fixed compilation of instrumentation examples with debugger OFF 2023-04-06 22:18:01 +03:00
Julien Freche
29f3e4a455 cpudb: extend strings that are too small 2023-02-22 12:03:02 -08:00
quirck
bee4cefb9e Check breakpoints before icount guard 2022-11-13 22:24:37 +03:00
Stanislav Shwartsman
7562731dca a little coding style unification 2022-10-08 20:35:36 +03:00
Stanislav Shwartsman
0e4524f38f Implemented CMPccXADD instructions 2022-10-08 20:04:22 +03:00
Stanislav Shwartsman
aa84121ede changes (c) date 2022-10-02 23:26:57 +03:00
Stanislav Shwartsman
c47b5ff5cb extract IFMA52 code to separate file 2022-10-02 23:24:00 +03:00
Stanislav Shwartsman
63ed447717 fixed compilation 2022-10-02 23:09:41 +03:00
Stanislav Shwartsman
4aed72e0ef fix issue with AVX IFMA when EVEX is not compiled in 2022-10-02 23:07:05 +03:00
Stanislav Shwartsman
a56144833a add support for AVX encoded VNNI INT8 extensions 2022-10-02 23:00:46 +03:00
Stanislav Shwartsman
3a20495db8 implemented WRMSRNS extension - Non Serializing version of WRMSR opcode 2022-10-02 22:16:02 +03:00
Stanislav Shwartsman
9f76eaacea implemented AVX IFMA instructions 2022-10-02 22:08:20 +03:00
Stanislav Shwartsman
d1737638ec add CPUID definitions disclosed in recent Intel SDM 2022-10-01 14:11:45 +03:00
Stanislav Shwartsman
b75fcc4535 updates to cpuid.h with most recent CPUID bit definitions 2022-08-26 22:31:23 +03:00
Stanislav Shwartsman
1e4f1624c8 remove trailing whitespace from source files 2022-08-23 21:46:04 +03:00
Satoshi Tanda
30ef7f4842
Fix dbg_xlate_linear2phy for NPT (#30) 2022-08-22 07:20:47 +03:00
Stanislav Shwartsman
fac15a7d03 updates to MTF code: 
if VMEntry delivered an event of event happen right after VMEntry - MTF becomes pending immediatelly
 2022-08-16 21:37:36 +03:00
Stanislav Shwartsman
b946570838 implemented VMX Monitor Trap Flag handling 2022-08-16 21:17:05 +03:00
Stanislav Shwartsman
180c1f09d5 fixed compilation 2022-08-14 21:18:25 +03:00
Stanislav Shwartsman
c9d8413422 allow TLB caching of SPP paging writes 
it is possible that SPP-protected subpage block is allowing write but all others are not.
the TLB entry cannot be cached as writeOK based on SPP subblock check
 2022-08-14 21:09:18 +03:00
Stanislav Shwartsman
97a2cdd85f update VMEXIT reasons according to published docs 
update list of trap-like VMEXITs
 2022-08-13 23:25:10 +03:00
Stanislav Shwartsman
df849619be more SPP limitations 2022-07-31 22:07:16 +03:00
Stanislav Shwartsman
f052c0f5b2 - VMX: Implemented missing SPP Misconfiguration condition (odd bits of SPP PTE entry are reserved) 
- VMX: Fix SPP walk and VMCS access memory type to WB (match memory type listed in IA32_VMX_BASIC MSR)
 2022-07-31 19:57:38 +03:00
Stanislav Shwartsman
13aa25919a Revert "do not ignore MSR=0 even if ignore_bad_msrs is set" 
MSR=0 is valid MSR (used for Machine Check Architecture)

This reverts commit cf03c00ef0.
 2022-07-31 18:47:13 +03:00
Stanislav Shwartsman
4d227d15fb remove instrument.h from bochs.h so it won't be included everywhere 
include it only where required
move PHY_ADDRESS reserved bits consts to cpu.h
 2022-07-30 22:35:43 +03:00
Stanislav Shwartsman
cf03c00ef0 do not ignore MSR=0 even if ignore_bad_msrs is set 2022-07-30 19:53:10 +03:00
Stanislav Shwartsman
d576eaa7c1 list in debug CR4 more already published bits (UINTR) 
fix debug print of XCR0
 2022-07-30 19:15:32 +03:00
Stanislav Shwartsman
3f65841714
use boolean constants true/false instead of 0/1 (#26) 
* use boolean constants true/false instead of 0/1

* fix code comment

Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2022-07-30 18:38:22 +03:00
Stanislav Shwartsman
0f9aec0e1a Merge branch 'master' of https://github.com/stlintel/Bochs 2022-07-30 15:43:25 +03:00
Stanislav Shwartsman
2093c2b1a3 allow 'Save guest MSR_PERF_GLOBAL_CTRL on VMEXIT' VMX control 
at least fake it
 2022-07-30 15:43:09 +03:00
Stanislav Shwartsman
f44f4ae753
MBE (Mode Based Execution Control) emulation (#22) 
* MBE (Mode Based Execution Control) emulation
 2022-07-30 15:26:47 +03:00
Stanislav Shwartsman
fb09790846 dos2unix to all files 2022-07-30 14:31:16 +03:00
Stanislav Shwartsman
8afd14972e
convert many consts from #define to enum or const variables (#23) 2022-07-27 23:20:47 +03:00
Stanislav Shwartsman
94503e7a0b
cpu/vmx definitions (#20) 
* update vmx.h with recently published definition
* update actions after conflicts
 2022-07-27 20:51:25 +03:00
Stanislav Shwartsman
430ba44b0e
Create hc-cpp.yml (#19) 
* Create hc-cpp.yml

* update actions

* update actions

* update actions

* update actions

* update actions

* fix format string for VMX preemption timer dbg message
Fix compilation with BX_HAVE_XRANDR_H = 0: XRRQueryExtension is not available

* update actions

* add .conf.everything to testing

Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2022-07-27 01:26:55 +03:00
Satoshi Tanda
88f881c6d5
Fix that the INIT signal remains pending even after delivery of VM-exit/#VMEXIT(INIT) (#16) 
* Clear pending INIT signal

When the INIT signal is translated into corresponding VM-exit/#VMEXIT,
the signal should no longer be marked as pending. Otherwise, the signal
would be (incorrectly) delivered again.

* Remove trailing space and fix an incorrect indent
 2022-07-24 07:14:01 +03:00
Satoshi Tanda
0ae5e67894
Fix that the blocking by SMI bit maybe set when a VM-exit ends outside SMM (#15) 
* Fix that the blocking by SMI bit is set

The blocking by SMI bit of the guest interruptibility state VMCS should
not be set unless the VM-exit ends in SMM. This only happens under the
dual-monitor treatment, which is not implemented in Bochs.

* Remove trailing whitespaces
 2022-07-23 19:36:31 +03:00
Stanislav Shwartsman
a8ef631a39
define and mention newly disclosed CPUID bits (#7) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2022-07-17 18:45:36 +03:00
ughoavgfhw
b8f38eb8d3 Fix two bugs around monitor/mwait 
MONITOR relies on tickle_read_virtual to set the physical address, but it was
only doing so on TLB miss. So a MONITOR with a TLB hit would arm the most
recently accessed address instead of the requested one.

TLB invalidations disarmed the monitoring range, but didn't wake a CPU that
had already MWAIT-ed. Any instruction that invalidated TLB entries on other
CPUs could have caused an MWAIT-ing CPU to never wake.
 2022-07-13 21:51:15 -05:00
Volker Ruppert
3e333a0d79 Removed APIC timer handles from save/restore list. They are set by the 
constructor and should not be modified. Timer activation after restore is not
necessary.
 2021-09-12 15:13:20 +00:00
Volker Ruppert
26914d0058 MWAIT timer fixes (to be completed). 
- Fixed MWAIT timer activation.
- A timer handle should not appear in the save/restore list.
- TODO: Activate MWAIT timer after restore if necessary.
 2021-09-10 16:54:54 +00:00
Volker Ruppert
52b0000db7 Applied two patches from Debian. 
- Apply standard flags from environment everywhere (SF patch #546).
- Allow overriding ld and objcopy for building bios on non-x86 platforms.
 2021-09-10 15:33:22 +00:00
Volker Ruppert
4c32ca7b16 Fixed some MSVC warnings in the cpu code (unsafe use of bool type). 2021-07-27 19:18:34 +00:00
Volker Ruppert
452201a231 Fixed two compiler warnings in the cpu code. 2021-07-27 15:36:11 +00:00
Stanislav Shwartsman
1455788fe4 remove cpudb.h from some Makefile dependencies. it should be only in cpu/init.cc and config.cc 2021-07-25 18:21:41 +00:00
Stanislav Shwartsman
021f3794fa remove cpudb.h from some Makefile dependencies. TODO: it should be only in cpu/init.cc and config.cc 2021-07-25 18:08:54 +00:00
Stanislav Shwartsman
2cb9bb4e44 remove cpudb.h from some Makefile dependencies. TODO: it should be only in cpu/init.cc and config.cc 2021-07-25 18:06:31 +00:00
Stanislav Shwartsman
7129b1d7c5 fixed number of arguments for BX_INFO 2021-07-25 18:02:36 +00:00
Stanislav Shwartsman
da21b16d7f remove cpudb.h from bochs.h 2021-07-25 18:01:28 +00:00
Stanislav Shwartsman
7b2bb50722 fixed VMX exit qualification info for INVEPT/INVVPID/INVPCID instructions 2021-07-23 10:13:48 +00:00
Stanislav Shwartsman
0cba8b66c9 more robust handling of SVM VMCB host ptr 2021-07-23 09:30:17 +00:00
Stanislav Shwartsman
daaab792b6 added SVM vmcbptr to save/restore image 2021-07-23 08:06:58 +00:00
Stanislav Shwartsman
01e785f479 minor tab2space 2021-07-03 19:00:41 +00:00
Stanislav Shwartsman
25ad0b804a VMX: fixed exit qualification info for VMREAD/VMWRITE instructions 2021-07-03 14:31:14 +00:00
Stanislav Shwartsman
097c8f13b9 minor coding style modifications 2021-05-25 06:27:49 +00:00
Stanislav Shwartsman
e4b2079109 fixed compilation in x86-64 off mode 2021-04-29 04:18:33 +00:00
Stanislav Shwartsman
d112ab9943 fixed compilation 2021-04-28 17:57:57 +00:00
Stanislav Shwartsman
f174ce2b6f SMM enter: never turn off EFER.SVME 2021-04-27 09:33:46 +00:00
Stanislav Shwartsman
2d2ec5e0aa hack to W/A NX paging fault under nested paging while virtualizing SMM under SVM 2021-04-27 08:22:45 +00:00
Stanislav Shwartsman
79d6a16e3b intercept SMI support in SVM 2021-04-27 08:22:04 +00:00
Stanislav Shwartsman
4e41530b8a SVM: Fixed EXITINFO error code after nested page fault (prevented Hyper-V from running) 2021-04-22 11:12:26 +00:00
Stanislav Shwartsman
8e58d7336f implement MSR PAR handling in AMD SVM 2021-03-21 15:33:18 +00:00
Stanislav Shwartsman
0736953e89 save GUEST PAT into VMCB for SVM 2021-03-19 06:03:04 +00:00
Stanislav Shwartsman
08a068a161 fixed SVM V_TPR handling SF bug #1428 AMD SVM Hyper-V fails 2021-03-11 21:19:45 +00:00
Volker Ruppert
ff93b11eb8 Removed SVN property "executable" from some files. 2021-02-21 09:25:33 +00:00
Stanislav Shwartsman
2ab50c7d66 solve code duplication between different cpudb models 2021-02-16 18:57:49 +00:00
Stanislav Shwartsman
b6e284b080 fix MSVC warnings 2021-02-11 15:05:06 +00:00
Stanislav Shwartsman
c87ce2d11a fixed some MSVC wannings in CPU code 2021-02-08 13:06:44 +00:00
Stanislav Shwartsman
1765a06d01 move debug.h from bochs.h and include it only where required 2021-01-31 15:22:58 +00:00
Stanislav Shwartsman
5874c8e29f fix compilation with SMP enabled 2021-01-31 14:03:28 +00:00
Stanislav Shwartsman
7153228d48 fixed compilation without bochs debugger 2021-01-30 20:31:03 +00:00
Stanislav Shwartsman
8285b6b51b regen Makefile include dependencies for CPU and internal debugger 2021-01-30 20:17:15 +00:00
Stanislav Shwartsman
1089e470e9 remove bochs-memory.h from bochs.h and include it only where required 2021-01-30 20:13:34 +00:00
Stanislav Shwartsman
6d6ff0e06b regen Makefile include dependencies for CPU, MEMORY and internal debugger 2021-01-30 19:44:41 +00:00
Stanislav Shwartsman
7cc9cffeed remove siminterface.h from bochs.h and include it only where required 2021-01-30 19:40:18 +00:00
Stanislav Shwartsman
0b83259417 regen include dep lists for cpu and memory - need to regen for all others 2021-01-30 18:57:45 +00:00
Stanislav Shwartsman
99e7b71540 remove gui.h from bochs.h and include it only where required 2021-01-30 18:47:25 +00:00
Stanislav Shwartsman
c878933057 remove pc_system.h from bochs.h and include it only where required 
next step: same for gui.h
 2021-01-30 18:29:28 +00:00
Stanislav Shwartsman
f79d6df458 strip redundant info from tigerlake cpuid text file 2021-01-30 08:45:34 +00:00
Stanislav Shwartsman
1bf18b8aae ! CPUID: Added TigerLake CPU definition (features CET and CLWB support) 
- CPU code refactor, remove uses of bx_bool datatype and use C++ classic bool instead.
  This enable better compiler optimizations and reduce binary size
 2021-01-30 08:35:35 +00:00
Stanislav Shwartsman
b7855153a0 new disasm: print branch target in 32-bit mode as 32-bit value 2021-01-02 16:48:13 +00:00
Stanislav Shwartsman
e15012cfcf fix code duplication in <limiting max cpuid leaf to 0x02 for winnt> feature 2021-01-02 16:28:51 +00:00
Stanislav Shwartsman
c33308731e fixed disasm of shift/rotate with implicit shift count=1 2021-01-02 15:12:29 +00:00
Stanislav Shwartsman
1a20dbc7f7 fixed bug in new disasm 2021-01-02 14:32:52 +00:00
Stanislav Shwartsman
980cfc1903 fixed compilation with no debugger configured in 2021-01-02 14:09:03 +00:00
Stanislav Shwartsman
bea432dacb fixed compilation with no debugger configured in 2021-01-02 14:04:35 +00:00
Stanislav Shwartsman
41ea50ba22 complete transition to new disasm, remove old disasm from source code 2021-01-02 13:43:10 +00:00
Stanislav Shwartsman
2f3adf849c enable syntax switch with new disasm also in GUI debugger, switch to new disasm by default everywhere 2021-01-02 12:04:52 +00:00
Stanislav Shwartsman
22774a0534 support for AT&T (GAS) disasm style in new disassembler 2021-01-02 11:12:23 +00:00
Stanislav Shwartsman
a4a2562c8d fixed compilation with no debugger enabled - will be cleaned up later 2020-12-30 16:58:17 +00:00
Stanislav Shwartsman
d2896bbd2a fixed compilation with no debugger enabled 2020-12-30 14:48:34 +00:00
Stanislav Shwartsman
bb568997c9 use new disasm wrapper method in more place 2020-12-30 14:09:25 +00:00
Stanislav Shwartsman
72db10d766 fix symbols display within disasm for new disassember, integrate new disasm with GUI debugger properly 2020-12-30 12:23:19 +00:00
Stanislav Shwartsman
79db3896d4 enable symbols for branch targets and JMP/CALL direct ptr instructions in new disassembler (still to be tested), attempt to use new disassembler in GUI debugger 2020-12-30 11:36:33 +00:00
Stanislav Shwartsman
e6822c81a1 fixed behavior of MMX PSRAW/PSRAD instructions when shift count is zero - still has to invalidate x87 tags for dest register 2020-12-15 20:05:54 +00:00
Stanislav Shwartsman
1df9bc0070 Fixed buffer overflow in LOAD_Wdq method when MXCSR.MM=1 -> thanks new gcc10 warning 2020-10-03 09:37:06 +00:00
Stanislav Shwartsman
c6050a99d1 implemented AVX encoded VNNI instructions published in recent SDM - not tested yet 2020-10-03 09:23:28 +00:00
Stanislav Shwartsman
a378441254 update CPUID bits and CR bits according to recently published SDM documents by Intel 2020-10-03 07:59:47 +00:00
Stanislav Shwartsman
d540e5b040 rename VMCS control enum 2020-05-29 12:55:56 +00:00
Stanislav Shwartsman
baa39a1b40 fixed comment 2020-05-29 12:52:26 +00:00
Stanislav Shwartsman
4023b640d6 Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS) 2020-05-29 12:35:30 +00:00
Stanislav Shwartsman
b891789c3d implemented (experimental) TSC Adjust MSR 2020-05-21 19:58:16 +00:00
Stanislav Shwartsman
dd3849b9e0 extract Bit128 arithmetic to separate wide_int.cc/wide_int.h compiled independently of long mode emulation 2020-05-19 16:01:23 +00:00
Stanislav Shwartsman
e50a3f8169 fixup code duplication in apic code 2020-05-17 19:32:14 +00:00
Stanislav Shwartsman
f97b20ddce deactivate apic timer when globally disabled 2020-05-17 19:03:39 +00:00
Stanislav Shwartsman
da169c0044 when apic is globally disabled - reset some fields to defaults 2020-05-17 18:57:27 +00:00
Stanislav Shwartsman
7a5fef764b fix for effcetive TSC compute when TSC multiplier is enabled 2020-05-17 18:39:52 +00:00
Stanislav Shwartsman
6ae26b39b3 fixed Sub-Page-Protection EPT violation (was triggered exactly opposite that excpected due to typo) 2020-05-17 14:12:29 +00:00
Stanislav Shwartsman
8e4a29fb0e reorg vmcs fields enabling based on their numeric order 2020-05-15 19:27:45 +00:00
Stanislav Shwartsman
499b138227 enable access to XSS_EXITING_BITMAP VMCS field 2020-05-15 19:05:41 +00:00
Stanislav Shwartsman
355c06e396 add defines for CPUID bits recently announced 2020-04-01 06:15:54 +00:00
Stanislav Shwartsman
81edc636d4 remove duplicate opcodes from decoder definitions 2020-03-28 14:36:27 +00:00
Stanislav Shwartsman
b686c8d423 add into ia_opcodes.def disasm field for every instruction 2020-03-28 14:23:54 +00:00
Stanislav Shwartsman
7d989b34a3 fixed recent segoverride assignment bug in SVN 2020-02-28 15:03:52 +00:00
Stanislav Shwartsman
6e2541daa6 CET: DS Seg override is kept for CET Endranch suppress hint even if overridden by other prefixes later 2020-02-21 19:38:23 +00:00
Stanislav Shwartsman
086f2779f5 fixed compilation with avx but without EVEX 2020-02-20 05:29:13 +00:00
Stanislav Shwartsman
1b208b0e93 fixed compilation under Visual Studio 2020-02-02 07:25:00 +00:00
Stanislav Shwartsman
6b691257dd fixed compilation with VMX off 2020-01-17 11:55:59 +00:00
Stanislav Shwartsman
a24b562e32 now when bios knows to set msr ia32_feature_ctrl, no need to initialize from reset code 2020-01-15 17:18:10 +00:00
Stanislav Shwartsman
5620a4968b set msr IA32_FEATURE_CTRL lock bit to ensure VMX is enabled - normally this should be done in Bios but init.cc can w/a 2020-01-11 07:04:44 +00:00
Stanislav Shwartsman
902ff1ef52 Part of the SF patch #548: Support Windows Hyper-V in Bochs by Xinyang 
When BX_SUPPORT_SMP is not defined, clear the bit in CPUID.[EAX=1].Bit[28] to indicate Hyper-Threading is unavailable.
 2020-01-11 06:18:13 +00:00
Stanislav Shwartsman
50bde4a38c flush TLBs on CR4.CET change 2020-01-10 20:04:22 +00:00
Stanislav Shwartsman
72dffd320d fixed CET fault on task switch when SSP is not 8-byte aligned. Bochs did #GP whiel SDM says #TS 2020-01-07 18:17:34 +00:00
Stanislav Shwartsman
694112732b use default base CPUID class method to detemine values of 0x80000008 leaf for IceLake CPUID 2020-01-03 19:53:20 +00:00
Stanislav Shwartsman
b69f2b052a extract calculation of MSR_IA32_XSS supported bits to a function 2020-01-03 19:33:16 +00:00
Stanislav Shwartsman
45a25a2b67 CET: make sure enbranch64 and enbranch32 do the right thing when mode mismatch 2020-01-03 18:55:17 +00:00
Stanislav Shwartsman
495206650b fixed CET wrmsr reserved bit checking 2020-01-03 18:44:15 +00:00
Stanislav Shwartsman
ea6b0c766c added more VMX reasons to enum according to Intel SDM 2020-01-03 17:35:02 +00:00
Stanislav Shwartsman
bac9104f73 fixed compilation of init.cc for old CPU models 2020-01-03 05:29:45 +00:00
Stanislav Shwartsman
9a35c6de79 fix and simplify combined_access handling in EPT page walk 2019-12-29 21:00:35 +00:00
Stanislav Shwartsman
016aa349e5 handle supervisor-shadow-stack protection feature in the EPT 2019-12-29 20:40:18 +00:00
Stanislav Shwartsman
4f7aa4bd76 fixed compilation issue 2019-12-28 15:20:38 +00:00
Stanislav Shwartsman
f56e1aab86 VMX: save CET state to VMCS only if CET is supported 2019-12-28 15:18:55 +00:00
Stanislav Shwartsman
bcafd5bb7a fix non-printable characters and add more verbose error messages 2019-12-28 15:08:53 +00:00
Stanislav Shwartsman
d091e3bda6 simplify XRSTOR* code 2019-12-28 14:03:54 +00:00
Stanislav Shwartsman
126ae0d0b4 more verbose debug print 2019-12-28 13:36:43 +00:00
Stanislav Shwartsman
9458e25486 reverting commit 13737 and doing correct fix 2019-12-28 13:11:13 +00:00
Stanislav Shwartsman
5d7c6d46b0 fixed compilation after prev commit 2019-12-28 13:02:02 +00:00
Stanislav Shwartsman
7f72252223 fixes in XSAVE/XRSTOR handling 2019-12-28 12:57:31 +00:00
Stanislav Shwartsman
b09126aa34 use enums for assign_srcs error output - help with debugging unexpected #UD cases 2019-12-27 19:34:32 +00:00
Stanislav Shwartsman
6879feebf5 SHA: SHA instructions in 128-bit memory operand require to be explicitly aligned 2019-12-27 14:24:43 +00:00
Stanislav Shwartsman
5c45f6b324 AVX512: EVEX.Z is forbidden for any vector instruction using opmask as source or destination (should cause #UD) 2019-12-27 14:23:53 +00:00
Stanislav Shwartsman
8bd5272591 correctly handle CET Enbranch override prefix 0x3E in 64-bit mode 2019-12-27 13:44:57 +00:00
Stanislav Shwartsman
596c197cea fix decoder: SHA1RNDS4 instruction should be with no SSE prefix 2019-12-27 13:08:20 +00:00
Stanislav Shwartsman
a2be16873c VMX: save guest CET state to VMCS on vmexit 2019-12-27 13:02:30 +00:00
Stanislav Shwartsman
8e2391c44b fixed compilation when compiling without EVEX 2019-12-26 20:12:40 +00:00
Stanislav Shwartsman
ff167d0f65 change a bit more defines to const with type 2019-12-26 16:48:33 +00:00
Stanislav Shwartsman
d6c3dcf033 revert for full vector read until figured out the right behavior for VPSHUFBITQMB 2019-12-24 20:08:33 +00:00
Stanislav Shwartsman
edcdce927c added ability to configure hidden VMCS field mapping through CPUID 2019-12-22 18:53:07 +00:00
Stanislav Shwartsman
fc1dbe68bc update dependencies in Mafefile.in 2019-12-21 21:42:35 +00:00
Stanislav Shwartsman
e593bb0084 CPUDB: Allow Icelake-U CPU model to exists without EVEX 2019-12-21 21:06:34 +00:00
Stanislav Shwartsman
e38cca20be disable fault suppression for VPEXPAND* until fugured out how it should work in real life 2019-12-21 20:54:45 +00:00
Stanislav Shwartsman
f99258a2fd fixed copy-paste issue 2019-12-21 20:30:15 +00:00
Stanislav Shwartsman
c16816485e use optimized function for broadcastss 2019-12-21 20:20:33 +00:00
Stanislav Shwartsman
1a0237e9af make order in AVX512 broadcast handlers, extract them into separate file 2019-12-21 20:07:03 +00:00
Stanislav Shwartsman
11585e4982 AVX512: VPBROADCASTB/W/D/Q with GPR source are only reg/reg 2019-12-21 18:29:51 +00:00
Stanislav Shwartsman
afa3626eb3 AVX512: fixed compressed immediate size (and memory access size) for VPBROADCASTB_Eb form 2019-12-21 18:17:51 +00:00
Stanislav Shwartsman
0169605f79 seems like GFNI VGF2P8AFFINEQB and VGF2P8AFFINEINVQB do not have fault suppression 2019-12-21 18:01:58 +00:00
Stanislav Shwartsman
4ac2122f3a rename function to correct English, add broadcast and fault suppression support for EVEX encoded GFNI instructions 2019-12-21 16:12:06 +00:00
Stanislav Shwartsman
dd1ab303df rename function to correct English 2019-12-21 15:54:52 +00:00
Stanislav Shwartsman
723554d535 AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-21 15:47:29 +00:00
Stanislav Shwartsman
74c73e5a76 AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-20 15:34:14 +00:00
Stanislav Shwartsman
0e5d843597 AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-20 14:58:56 +00:00
Stanislav Shwartsman
cff6a67adb AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-20 14:57:42 +00:00
Stanislav Shwartsman
9fbf974e6b AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-20 13:45:00 +00:00
Stanislav Shwartsman
222185ad11 AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-20 13:42:59 +00:00
Stanislav Shwartsman
553a9471d1 fixed push error check for VMX injecting event vector 21 on configuration that doesn't support CET 2019-12-20 13:27:18 +00:00
Stanislav Shwartsman
ec5f526ac0 ENBRANCH and RDSSP should remain NOP when CET not enabled, this means they not require an specifical CPU feature to be decoded into the hnadler 2019-12-20 13:16:52 +00:00
Stanislav Shwartsman
f90e5f4f44 Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071 
Only missing items (to be added soon):
  - Supervisor Shadow Stack EPT Control is not implemented yet
  - SMM placing for SSP
Currently have to be added manually to some CPUID model, for example to ICL-U
To enable configure with --enable-cet
 2019-12-20 07:42:07 +00:00
Stanislav Shwartsman
9c98d68f87 AVX512_VBMI2: Fixed shift count from register source for VBMI2 shift instructions (VPSHRDVD/VPSHLDVD/VPSHRDVQ/VPSHLDVQ) 2019-12-19 21:55:46 +00:00
Stanislav Shwartsman
1b9e0081b4 fixed bugs in recently implemented load methods with fault suppression support 2019-12-19 21:36:13 +00:00
Stanislav Shwartsman
39aee8773f AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-19 21:21:24 +00:00
Stanislav Shwartsman
682fbda5af AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-19 21:12:47 +00:00
Stanislav Shwartsman
59cad2e156 AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-19 21:12:23 +00:00
Stanislav Shwartsman
2df60c3b3f AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-19 20:08:49 +00:00
Stanislav Shwartsman
df986a05ca fixed bug in SHA256RNDS2 instruction - wrong order of dwords in result 2019-12-19 19:20:13 +00:00
Stanislav Shwartsman
9b556d7656 fixed compilation error in crregs.cc xsave method init code - more methods to fix 2019-12-19 19:14:37 +00:00
Stanislav Shwartsman
258679b6dc fixed compilation error in crregs.cc xsave method init code 2019-12-19 19:12:39 +00:00
Stanislav Shwartsman
bb58ef5548 fixed bug in SHA256RNDS2 instruction (wrong sha transformation used) 2019-12-19 19:08:50 +00:00
Stanislav Shwartsman
019c934cfd decode GFNI opcodes in 64-bit mode too 2019-12-18 19:55:04 +00:00
Stanislav Shwartsman
6b1992783e w/a compilation issue in gcc7 2019-12-18 18:19:52 +00:00
Stanislav Shwartsman
26b67c1942 fixed calling for XSAVE methods with BX_USE_SMF=0 2019-12-17 19:14:09 +00:00
Stanislav Shwartsman
eca847c8b3 fixed compilation error 2019-12-16 19:47:41 +00:00
Stanislav Shwartsman
895c4b75df rewritten xsave/xrestore implementation in generic way to simplify adding new xsave/xrestore extensions 2019-12-16 16:14:51 +00:00
Stanislav Shwartsman
112e61f1c3 coding style: avoid goto, magic constants and defines which could be replaced by enums 2019-12-15 18:45:04 +00:00
Stanislav Shwartsman
bcfcaf3958 unify branch_far32 and branhc_far64 methods 2019-12-14 17:20:35 +00:00
Stanislav Shwartsman
c117208bbf extending fix to AMD SVM 2019-12-13 18:47:51 +00:00
Stanislav Shwartsman
1968cdf248 proposed fix for SF issue #547 vmcshostptr not invalidated after memory swapped out 2019-12-13 18:31:43 +00:00
Stanislav Shwartsman
134b23a809 enable AVX512_CD for Icelake configuration 2019-12-13 16:48:15 +00:00
Stanislav Shwartsman
2ea27f1afb more correct fix for load with mask and broadcast 2019-12-13 14:57:32 +00:00
Stanislav Shwartsman
6d612df280 AVX512_BITALG: Fixed decoding of VPSHUFBITQMB instruction 2019-12-13 14:11:08 +00:00
Stanislav Shwartsman
abdeea560a AVX512: fix masked broadcast with mask of all zero corner case - no memory access should be made at all 2019-12-13 13:44:30 +00:00
Stanislav Shwartsman
c9ac9a1e43 AVX512_VBMI: Fixed decoding of VPERMB instruction 2019-12-13 13:24:02 +00:00
Stanislav Shwartsman
fc79466dcb AVX512_VBMI: Fixed decoding of VPERMI2B/VPERMT2B instructions 2019-12-13 13:08:45 +00:00
Stanislav Shwartsman
eb009ddd00 fixed VPACKSSDW/VPACKUSDW opcodes - allow broadcast 2019-12-13 12:53:48 +00:00
Stanislav Shwartsman
f9d04849b3 fixed decoding for VPSHLDVW/VPSHRDVW/VPSHLDVD/VPSHLDVQ/VPSHRDVD/VPSHRDVQ 2019-12-13 12:34:16 +00:00
Stanislav Shwartsman
9bbf43ed4b fixed decoding of AVX512_VNNI instructions 2019-12-13 08:39:23 +00:00
Stanislav Shwartsman
27e96c807c fixed decoding of VPBROADCASTMW2D opcode 2019-12-13 08:09:18 +00:00
Stanislav Shwartsman
7090abe1a1 fix one more place with incorrect detection of x2apic MSR space. use function instead of magic numbers in all places 2019-12-10 21:07:19 +00:00
Stanislav Shwartsman
e35fcd1782 clarify err message 2019-12-10 20:38:45 +00:00
Stanislav Shwartsman
6c8db0f569 simplify interfaces to DTLB/ITLB 2019-12-09 18:46:36 +00:00
Stanislav Shwartsman
4b66fecaad split Bochs CPU TLB to DTLB and ITLB to avoid aliasing conflicts between them. ~5% speedup measured 2019-12-09 18:37:02 +00:00
Stanislav Shwartsman
311ef81e87 fixed comment 2019-12-09 18:16:29 +00:00
Stanislav Shwartsman
b228d22303 expose TLB_INDEX_OF for debugger compilation 2019-12-09 16:55:41 +00:00
Stanislav Shwartsman
8befc3bf82 make separate class for TLB to be used in CPU class. preparation to DTLB and ITLB split of TLB structure 2019-12-09 16:49:51 +00:00
Stanislav Shwartsman
44b3ebeca2 remove BX_TRUE/BX_FALSE macros, use stdc++ true/false instead 2019-12-09 16:44:36 +00:00
Stanislav Shwartsman
96e2c50bef applying SF patch #545 Speling fixes 2019-12-09 16:29:23 +00:00
Stanislav Shwartsman
12d228abde split vmx initialization to multiple methods for better code readability, improve VMX error messages 2019-12-08 20:46:51 +00:00
Stanislav Shwartsman
b3076793b7 fixed MSR range reserved for x2apic 2019-12-08 19:17:46 +00:00
Stanislav Shwartsman
c7fdf6d428 add ability to read or write LVT_CMCI APIC register. It will never fire and interrupt as #MC is don't care but user can configure the interface 2019-12-06 19:38:59 +00:00
Stanislav Shwartsman
06d826755b increase max configurable msrs to 0x1000 again 2019-12-06 12:31:51 +00:00
Stanislav Shwartsman
8c385f2a9a fix in cpu features print 2019-12-06 11:05:05 +00:00
Stanislav Shwartsman
7861ff5160 fixed typo in feature name 2019-12-06 10:39:42 +00:00
Stanislav Shwartsman
0c75e0beaf extract xcr0_support bits calculation to a function 2019-12-06 09:23:28 +00:00
Stanislav Shwartsman
893aa10359 cosmetic changes 2019-12-04 19:53:08 +00:00
Stanislav Shwartsman
276482e67d fix set_PKRU method 2019-12-04 18:52:00 +00:00
Stanislav Shwartsman
951361a3a5 bugfix: PKRU should affect only user-mode memory accesses (bug in page translation) 2019-12-04 17:27:57 +00:00
Stanislav Shwartsman
4e9e3f85de simplify code by merging two opcodes with similar behavior 2019-11-27 15:31:32 +00:00
Stanislav Shwartsman
36991e9f59 fixed typo in comment 2019-11-26 17:39:09 +00:00
Stanislav Shwartsman
7833a82347 fixed bug in instruction decoding - regression before release 2019-11-22 17:46:54 +00:00
Stanislav Shwartsman
3b9db9e4cd fixed bug in faststring optimizations recently introduced 2019-11-22 10:54:36 +00:00
Stanislav Shwartsman
46b862fe5e do not truncate disasm branch target in 64-bit mode 2019-11-20 20:41:03 +00:00
Stanislav Shwartsman
a030d03935 fixed bug in instruction decoding - regression before release 2019-11-20 20:18:22 +00:00
Stanislav Shwartsman
83846cc821 fixed bug in instruction decoding - regression before release 2019-11-20 20:11:00 +00:00
Stanislav Shwartsman
82b6f7cb6c fixed bug in instruction decoding - regression before release 2019-11-20 19:58:51 +00:00
Stanislav Shwartsman
00237b5c9d add missing XSAVE_PKRU_STATE_LEN define 2019-11-12 22:02:02 +00:00
Stanislav Shwartsman
4aba3b54e7 do not use uint 2019-11-12 22:00:29 +00:00
Stanislav Shwartsman
b1e9701e5c avoid goto 2019-11-12 21:48:54 +00:00
Stanislav Shwartsman
8d7bffa311 optimize highest_priority_int routine 2019-11-12 21:42:57 +00:00
Stanislav Shwartsman
8d13fb3ffd rewritten APIC interfaces to hold irr/isr/tmr in Bit32u values instead of array of bytes 2019-11-12 21:15:29 +00:00
Stanislav Shwartsman
a70df308fa add defines for CPUID bits published in latest SDM 071 2019-11-12 18:54:08 +00:00
Stanislav Shwartsman
c098ab7de1 take msr.ia32_spec_ctrl out of @ifdef CPU_LEVEL=6 2019-10-26 20:17:41 +00:00
Stanislav Shwartsman
d766cc8112 implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition 2019-10-26 20:09:30 +00:00
Stanislav Shwartsman
a580b0ccbe cosmetic change with no logic affected 2019-10-24 20:33:05 +00:00
Stanislav Shwartsman
c97bb62b6c VMX: Fix RDRAND/RDSEED VMEXIT Instruction-Information Field 2019-10-24 20:12:00 +00:00
Stanislav Shwartsman
330c691367 VMX: Fix RDRAND/RDSEED VMEXIT Instruction-Information Field 2019-10-24 20:10:56 +00:00
Stanislav Shwartsman
27e23ad1eb give priority for VMX induced #UD in INVPCID and RDTSCP instructions over all other exeptions that could be generated there 2019-10-24 19:49:25 +00:00
Stanislav Shwartsman
72b9d26717 coding style changes, tab2space, macro2function or macro2const 2019-10-17 19:23:27 +00:00