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reverting commit 13737 and doing correct fix

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This commit is contained in:
Stanislav Shwartsman 2019-12-28 13:11:13 +00:00
parent 5d7c6d46b0
commit 9458e25486
3 changed files with 48 additions and 48 deletions
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36
bochs/cpu/cpu.h
View File

@ -4896,56 +4896,56 @@ public: // for now...
BX_SMF Bit32u get_xcr0_allow_mask(void);
BX_SMF Bit32u get_xinuse_vector(Bit32u requested_feature_bitmap);
BX_SMF bx_bool xsave_x87_state_xinuse(bxInstruction_c *i);
BX_SMF bx_bool xsave_x87_state_xinuse(void);
BX_SMF void xsave_x87_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_x87_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_init_x87_state(bxInstruction_c *i);
BX_SMF void xrstor_init_x87_state(void);
BX_SMF bx_bool xsave_sse_state_xinuse(bxInstruction_c *i);
BX_SMF bx_bool xsave_sse_state_xinuse(void);
BX_SMF void xsave_sse_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_sse_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_init_sse_state(bxInstruction_c *i);
BX_SMF void xrstor_init_sse_state(void);
#if BX_SUPPORT_AVX
BX_SMF bx_bool xsave_ymm_state_xinuse(bxInstruction_c *i);
BX_SMF bx_bool xsave_ymm_state_xinuse(void);
BX_SMF void xsave_ymm_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_ymm_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_init_ymm_state(bxInstruction_c *i);
BX_SMF void xrstor_init_ymm_state(void);
#if BX_SUPPORT_EVEX
BX_SMF bx_bool xsave_opmask_state_xinuse(bxInstruction_c *i);
BX_SMF bx_bool xsave_opmask_state_xinuse(void);
BX_SMF void xsave_opmask_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_opmask_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_init_opmask_state(bxInstruction_c *i);
BX_SMF void xrstor_init_opmask_state(void);
BX_SMF bx_bool xsave_zmm_hi256_state_xinuse(bxInstruction_c *i);
BX_SMF bx_bool xsave_zmm_hi256_state_xinuse(void);
BX_SMF void xsave_zmm_hi256_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_zmm_hi256_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_init_zmm_hi256_state(bxInstruction_c *i);
BX_SMF void xrstor_init_zmm_hi256_state(void);
BX_SMF bx_bool xsave_hi_zmm_state_xinuse(bxInstruction_c *i);
BX_SMF bx_bool xsave_hi_zmm_state_xinuse(void);
BX_SMF void xsave_hi_zmm_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_hi_zmm_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_init_hi_zmm_state(bxInstruction_c *i);
BX_SMF void xrstor_init_hi_zmm_state(void);
#endif
#endif
#if BX_SUPPORT_PKEYS
BX_SMF bx_bool xsave_pkru_state_xinuse(bxInstruction_c *i);
BX_SMF bx_bool xsave_pkru_state_xinuse(void);
BX_SMF void xsave_pkru_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_pkru_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_init_pkru_state(bxInstruction_c *i);
BX_SMF void xrstor_init_pkru_state(void);
#endif
#if BX_SUPPORT_CET
BX_SMF bx_bool xsave_cet_u_state_xinuse(bxInstruction_c *i);
BX_SMF bx_bool xsave_cet_u_state_xinuse(void);
BX_SMF void xsave_cet_u_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_cet_u_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_init_cet_u_state(bxInstruction_c *i);
BX_SMF void xrstor_init_cet_u_state(void);
BX_SMF bx_bool xsave_cet_s_state_xinuse(bxInstruction_c *i);
BX_SMF bx_bool xsave_cet_s_state_xinuse(void);
BX_SMF void xsave_cet_s_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_cet_s_state(bxInstruction_c *i, bx_address offset);
BX_SMF void xrstor_init_cet_s_state(bxInstruction_c *i);
BX_SMF void xrstor_init_cet_s_state(void);
#endif
#endif

8
bochs/cpu/crregs.h
View File

@ -303,15 +303,15 @@ struct xcr0_t {
};
#if BX_USE_CPU_SMF
typedef bx_bool (*XSaveStateInUsePtr_tR)(bxInstruction_c *i);
typedef bx_bool (*XSaveStateInUsePtr_tR)(void);
typedef void (*XSavePtr_tR)(bxInstruction_c *i, bx_address offset);
typedef void (*XRestorPtr_tR)(bxInstruction_c *i, bx_address offset);
typedef void (*XRestorInitPtr_tR)(bxInstruction_c *i);
typedef void (*XRestorInitPtr_tR)(void);
#else
typedef bx_bool (BX_CPU_C::*XSaveStateInUsePtr_tR)(bxInstruction_c *i);
typedef bx_bool (BX_CPU_C::*XSaveStateInUsePtr_tR)(void);
typedef void (BX_CPU_C::*XSavePtr_tR)(bxInstruction_c *i, bx_address offset);
typedef void (BX_CPU_C::*XRestorPtr_tR)(bxInstruction_c *i, bx_address offset);
typedef void (BX_CPU_C::*XRestorInitPtr_tR)(bxInstruction_c *i);
typedef void (BX_CPU_C::*XRestorInitPtr_tR)(void);
#endif
struct XSaveRestoreStateHelper {

52
bochs/cpu/xsave.cc
View File

@ -582,7 +582,7 @@ void BX_CPU_C::xrstor_x87_state(bxInstruction_c *i, bx_address offset)
}
}
void BX_CPU_C::xrstor_init_x87_state(bxInstruction_c *i)
void BX_CPU_C::xrstor_init_x87_state(void)
{
// initialize FPU with reset values
BX_CPU_THIS_PTR the_i387.init();
@ -593,7 +593,7 @@ void BX_CPU_C::xrstor_init_x87_state(bxInstruction_c *i)
}
}
bx_bool BX_CPU_C::xsave_x87_state_xinuse(bxInstruction_c *i)
bx_bool BX_CPU_C::xsave_x87_state_xinuse(void)
{
if (BX_CPU_THIS_PTR the_i387.get_control_word() != 0x037F ||
BX_CPU_THIS_PTR the_i387.get_status_word() != 0 ||
@ -638,7 +638,7 @@ void BX_CPU_C::xrstor_sse_state(bxInstruction_c *i, bx_address offset)
}
}
void BX_CPU_C::xrstor_init_sse_state(bxInstruction_c *i)
void BX_CPU_C::xrstor_init_sse_state(void)
{
// initialize SSE with reset values
for(unsigned index=0; index < 16; index++) {
@ -647,7 +647,7 @@ void BX_CPU_C::xrstor_init_sse_state(bxInstruction_c *i)
}
}
bx_bool BX_CPU_C::xsave_sse_state_xinuse(bxInstruction_c *i)
bx_bool BX_CPU_C::xsave_sse_state_xinuse(void)
{
for(unsigned index=0; index < 16; index++) {
// set XMM8-XMM15 only in 64-bit mode
@ -690,7 +690,7 @@ void BX_CPU_C::xrstor_ymm_state(bxInstruction_c *i, bx_address offset)
}
}
void BX_CPU_C::xrstor_init_ymm_state(bxInstruction_c *i)
void BX_CPU_C::xrstor_init_ymm_state(void)
{
// initialize upper part of AVX registers with reset values
for(unsigned index=0; index < 16; index++) {
@ -699,7 +699,7 @@ void BX_CPU_C::xrstor_init_ymm_state(bxInstruction_c *i)
}
}
bx_bool BX_CPU_C::xsave_ymm_state_xinuse(bxInstruction_c *i)
bx_bool BX_CPU_C::xsave_ymm_state_xinuse(void)
{
for(unsigned index=0; index < 16; index++) {
// set YMM8-YMM15 only in 64-bit mode
@ -737,7 +737,7 @@ void BX_CPU_C::xrstor_opmask_state(bxInstruction_c *i, bx_address offset)
}
}
void BX_CPU_C::xrstor_init_opmask_state(bxInstruction_c *i)
void BX_CPU_C::xrstor_init_opmask_state(void)
{
// initialize opmask registers with reset values
for(unsigned index=0; index < 8; index++) {
@ -745,7 +745,7 @@ void BX_CPU_C::xrstor_init_opmask_state(bxInstruction_c *i)
}
}
bx_bool BX_CPU_C::xsave_opmask_state_xinuse(bxInstruction_c *i)
bx_bool BX_CPU_C::xsave_opmask_state_xinuse(void)
{
for(unsigned index=0; index < 8; index++) {
if (BX_READ_OPMASK(index)) return true;
@ -762,7 +762,7 @@ bx_bool BX_CPU_C::xsave_opmask_state_xinuse(bxInstruction_c *i)
void BX_CPU_C::xsave_zmm_hi256_state(bxInstruction_c *i, bx_address offset)
{
unsigned num_regs = i->os64L() ? 16 : 8;
unsigned num_regs = long64_mode() ? 16 : 8;
bx_address asize_mask = i->asize_mask();
@ -774,7 +774,7 @@ void BX_CPU_C::xsave_zmm_hi256_state(bxInstruction_c *i, bx_address offset)
void BX_CPU_C::xrstor_zmm_hi256_state(bxInstruction_c *i, bx_address offset)
{
unsigned num_regs = i->os64L() ? 16 : 8;
unsigned num_regs = long64_mode() ? 16 : 8;
bx_address asize_mask = i->asize_mask();
@ -784,9 +784,9 @@ void BX_CPU_C::xrstor_zmm_hi256_state(bxInstruction_c *i, bx_address offset)
}
}
void BX_CPU_C::xrstor_init_zmm_hi256_state(bxInstruction_c *i)
void BX_CPU_C::xrstor_init_zmm_hi256_state(void)
{
unsigned num_regs = i->os64L() ? 16 : 8;
unsigned num_regs = long64_mode() ? 16 : 8;
// initialize upper part of ZMM registers with reset values
for(unsigned index=0; index < num_regs; index++) {
@ -794,9 +794,9 @@ void BX_CPU_C::xrstor_init_zmm_hi256_state(bxInstruction_c *i)
}
}
bx_bool BX_CPU_C::xsave_zmm_hi256_state_xinuse(bxInstruction_c *i)
bx_bool BX_CPU_C::xsave_zmm_hi256_state_xinuse(void)
{
unsigned num_regs = i->os64L() ? 16 : 8;
unsigned num_regs = long64_mode() ? 16 : 8;
for(unsigned index=0; index < num_regs; index++) {
for (unsigned n=2; n < 4; n++) {
@ -816,7 +816,7 @@ bx_bool BX_CPU_C::xsave_zmm_hi256_state_xinuse(bxInstruction_c *i)
void BX_CPU_C::xsave_hi_zmm_state(bxInstruction_c *i, bx_address offset)
{
if (!i->os64L()) return;
if (!long64_mode()) return;
bx_address asize_mask = i->asize_mask();
@ -828,7 +828,7 @@ void BX_CPU_C::xsave_hi_zmm_state(bxInstruction_c *i, bx_address offset)
void BX_CPU_C::xrstor_hi_zmm_state(bxInstruction_c *i, bx_address offset)
{
if (!i->os64L()) return;
if (!long64_mode()) return;
bx_address asize_mask = i->asize_mask();
@ -838,9 +838,9 @@ void BX_CPU_C::xrstor_hi_zmm_state(bxInstruction_c *i, bx_address offset)
}
}
void BX_CPU_C::xrstor_init_hi_zmm_state(bxInstruction_c *i)
void BX_CPU_C::xrstor_init_hi_zmm_state(void)
{
if (!i->os64L()) return;
if (!long64_mode()) return;
// initialize high ZMM registers with reset values
for(unsigned index=16; index < 32; index++) {
@ -848,9 +848,9 @@ void BX_CPU_C::xrstor_init_hi_zmm_state(bxInstruction_c *i)
}
}
bx_bool BX_CPU_C::xsave_hi_zmm_state_xinuse(bxInstruction_c *i)
bx_bool BX_CPU_C::xsave_hi_zmm_state_xinuse(void)
{
if (!i->os64L()) return true;
if (!long64_mode()) return true;
for(unsigned index=16; index < 32; index++) {
for (unsigned n=0; n < 4; n++) {
@ -879,14 +879,14 @@ void BX_CPU_C::xrstor_pkru_state(bxInstruction_c *i, bx_address offset)
TMP32 = read_virtual_dword(i->seg(), offset);
}
void BX_CPU_C::xrstor_init_pkru_state(bxInstruction_c *i)
void BX_CPU_C::xrstor_init_pkru_state(void)
{
// just write the pkru to TMP register for now and don't call set_PKRU
// calling it will take immediate effect on all future memory accesses including load of other XRSTOR components
TMP32 = 0;
}
bx_bool BX_CPU_C::xsave_pkru_state_xinuse(bxInstruction_c *i)
bx_bool BX_CPU_C::xsave_pkru_state_xinuse(void)
{
return (BX_CPU_THIS_PTR pkru != 0);
}
@ -914,13 +914,13 @@ void BX_CPU_C::xrstor_cet_u_state(bxInstruction_c *i, bx_address offset)
wrmsr(BX_MSR_IA32_PL3_SSP, ia32_pl3_ssp);
}
void BX_CPU_C::xrstor_init_cet_u_state(bxInstruction_c *i)
void BX_CPU_C::xrstor_init_cet_u_state(void)
{
BX_CPU_THIS_PTR msr.ia32_cet_control[1] = 0;
BX_CPU_THIS_PTR msr.ia32_pl_ssp[3] = 0;
}
bx_bool BX_CPU_C::xsave_cet_u_state_xinuse(bxInstruction_c *i)
bx_bool BX_CPU_C::xsave_cet_u_state_xinuse(void)
{
return BX_CPU_THIS_PTR msr.ia32_cet_control[1] == 0 &&
BX_CPU_THIS_PTR msr.ia32_pl_ssp[3] == 0;
@ -950,13 +950,13 @@ void BX_CPU_C::xrstor_cet_s_state(bxInstruction_c *i, bx_address offset)
wrmsr(BX_MSR_IA32_PL2_SSP, ia32_pl2_ssp);
}
void BX_CPU_C::xrstor_init_cet_s_state(bxInstruction_c *i)
void BX_CPU_C::xrstor_init_cet_s_state(void)
{
for (unsigned n=0;n<3;n++)
BX_CPU_THIS_PTR msr.ia32_pl_ssp[n] = 0;
}
bx_bool BX_CPU_C::xsave_cet_s_state_xinuse(bxInstruction_c *i)
bx_bool BX_CPU_C::xsave_cet_s_state_xinuse(void)
{
for (unsigned n=0;n<3;n++)
return BX_CPU_THIS_PTR msr.ia32_pl_ssp[n] != 0;