rewritten APIC interfaces to hold irr/isr/tmr in Bit32u values instead of array of bytes
This commit is contained in:
Stanislav Shwartsman
parent
a70df308fa
commit
8d13fb3ffd
@ -222,10 +222,10 @@ void bx_local_apic_c::reset(unsigned type)
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icr_lo = 0;
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task_priority = 0;
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for(i=0; i<BX_LAPIC_MAX_INTS; i++) {
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for(i=0; i<8; i++) {
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irr[i] = isr[i] = tmr[i] = 0;
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#if BX_CPU_LEVEL >= 6
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ier[i] = 1; // all interrupts are enabled
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ier[i] = 0xFFFFFFFF; // all interrupts are enabled
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#endif
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}
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@ -395,43 +395,28 @@ Bit32u bx_local_apic_c::read_aligned(bx_phy_address addr)
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case BX_LAPIC_ISR5: case BX_LAPIC_ISR6:
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case BX_LAPIC_ISR7: case BX_LAPIC_ISR8:
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{
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unsigned index = (apic_reg - BX_LAPIC_ISR1) << 1;
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Bit32u value = 0, mask = 1;
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for(int i=0;i<32;i++) {
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if(isr[index+i]) value |= mask;
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mask <<= 1;
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}
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data = value;
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int index = (apic_reg - BX_LAPIC_ISR1) >> 4;
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data = isr[index];
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break;
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}
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break;
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case BX_LAPIC_TMR1: case BX_LAPIC_TMR2:
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case BX_LAPIC_TMR3: case BX_LAPIC_TMR4:
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case BX_LAPIC_TMR5: case BX_LAPIC_TMR6:
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case BX_LAPIC_TMR7: case BX_LAPIC_TMR8:
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{
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unsigned index = (apic_reg - BX_LAPIC_TMR1) << 1;
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Bit32u value = 0, mask = 1;
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for(int i=0;i<32;i++) {
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if(tmr[index+i]) value |= mask;
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mask <<= 1;
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}
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data = value;
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int index = (apic_reg - BX_LAPIC_TMR1) >> 4;
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data = tmr[index];
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break;
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}
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break;
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case BX_LAPIC_IRR1: case BX_LAPIC_IRR2:
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case BX_LAPIC_IRR3: case BX_LAPIC_IRR4:
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case BX_LAPIC_IRR5: case BX_LAPIC_IRR6:
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case BX_LAPIC_IRR7: case BX_LAPIC_IRR8:
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{
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unsigned index = (apic_reg - BX_LAPIC_IRR1) << 1;
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Bit32u value = 0, mask = 1;
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for(int i=0;i<32;i++) {
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if(irr[index+i]) value |= mask;
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mask <<= 1;
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}
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data = value;
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int index = (apic_reg - BX_LAPIC_IRR1) >> 4;
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data = irr[index];
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break;
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}
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break;
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case BX_LAPIC_ESR: // error status reg
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data = error_status; break;
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case BX_LAPIC_ICR_LO: // interrupt command reg 0-31
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@ -479,15 +464,10 @@ Bit32u bx_local_apic_c::read_aligned(bx_phy_address addr)
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case BX_LAPIC_IER5: case BX_LAPIC_IER6:
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case BX_LAPIC_IER7: case BX_LAPIC_IER8:
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{
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unsigned index = (apic_reg - BX_LAPIC_IER1) << 1;
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Bit32u value = 0, mask = 1;
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for(int i=0;i<32;i++) {
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if(ier[index+i]) value |= mask;
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mask <<= 1;
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}
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data = value;
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int index = (apic_reg - BX_LAPIC_IER1) >> 4;
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data = ier[index];
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break;
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}
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break;
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#endif
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default:
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shadow_error_status |= APIC_ERR_ILLEGAL_ADDR;
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@ -609,12 +589,8 @@ void bx_local_apic_c::write_aligned(bx_phy_address addr, Bit32u value)
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break;
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}
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unsigned index = (apic_reg - BX_LAPIC_IER1) << 1;
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Bit32u mask = 1;
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for(int i=0;i<32;i++) {
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if(value & mask) ier[index+i] = 1;
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mask <<= 1;
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}
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int index = (apic_reg - BX_LAPIC_IER1) >> 4;
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ier[index] = value;
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}
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break;
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#endif
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@ -736,10 +712,10 @@ void bx_local_apic_c::receive_EOI(Bit32u value)
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else {
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if ((Bit32u) vec != spurious_vector) {
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BX_DEBUG(("local apic received EOI, hopefully for vector 0x%02x", vec));
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isr[vec] = 0;
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if(tmr[vec]) {
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clear_vector(isr, vec);
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if(get_vector(tmr, vec)) {
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apic_bus_broadcast_eoi(vec);
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tmr[vec] = 0;
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clear_vector(tmr, vec);
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}
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service_local_apic();
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}
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@ -756,12 +732,12 @@ void bx_local_apic_c::receive_SEOI(Bit8u vec)
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return;
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}
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if (isr[vec]) {
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if (get_vector(isr, vec)) {
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BX_DEBUG(("local apic received SEOI for vector 0x%02x", vec));
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isr[vec] = 0;
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if(tmr[vec]) {
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clear_vector(isr, vec);
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if(get_vector(tmr, vec)) {
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apic_bus_broadcast_eoi(vec);
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tmr[vec] = 0;
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clear_vector(tmr, vec);
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}
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service_local_apic();
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}
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@ -775,13 +751,28 @@ void bx_local_apic_c::startup_msg(Bit8u vector)
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cpu->deliver_SIPI(vector);
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}
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int bx_local_apic_c::highest_priority_int(Bit8u *array)
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bx_bool bx_local_apic_c::get_vector(Bit32u *reg, unsigned vector)
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{
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return (reg[vector / 32] >> (vector % 32)) & 0x1;
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}
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void bx_local_apic_c::set_vector(Bit32u *reg, unsigned vector)
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{
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reg[vector / 32] |= (1 << (vector % 32));
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}
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void bx_local_apic_c::clear_vector(Bit32u *reg, unsigned vector)
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{
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reg[vector / 32] &= ~(1 << (vector % 32));
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}
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int bx_local_apic_c::highest_priority_int(Bit32u *array)
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{
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for(int i=BX_LAPIC_LAST_VECTOR; i>=BX_LAPIC_FIRST_VECTOR; i--) {
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#if BX_CPU_LEVEL >= 6
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if (! ier[i]) continue;
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if (! get_vector(ier, i)) continue;
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#endif
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if (array[i]) return i;
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if (get_vector(array, i)) return i;
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}
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return -1;
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@ -862,18 +853,19 @@ void bx_local_apic_c::trigger_irq(Bit8u vector, unsigned trigger_mode, bx_bool b
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BX_DEBUG(("triggered vector %#02x", vector));
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if(bypass_irr_isr) {
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goto service_vector;
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if(! bypass_irr_isr) {
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if(get_vector(irr, vector)) {
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BX_DEBUG(("triggered vector %#02x not accepted", vector));
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return;
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}
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}
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if(irr[vector] != 0) {
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BX_DEBUG(("triggered vector %#02x not accepted", vector));
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return;
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}
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set_vector(irr, vector);
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if (trigger_mode)
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set_vector(tmr, vector); // set for level triggered
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else
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clear_vector(tmr, vector);
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service_vector:
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irr[vector] = 1;
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tmr[vector] = trigger_mode; // set for level triggered
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service_local_apic();
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}
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@ -882,8 +874,8 @@ void bx_local_apic_c::untrigger_irq(Bit8u vector, unsigned trigger_mode)
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BX_DEBUG(("untrigger interrupt vector=0x%02x", vector));
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// hardware says "no more". clear the bit. If the CPU hasn't yet
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// acknowledged the interrupt, it will never be serviced.
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BX_ASSERT(irr[vector] == 1);
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irr[vector] = 0;
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BX_ASSERT(get_vector(irr, vector));
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clear_vector(irr, vector);
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if(bx_dbg.apic) print_status();
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}
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@ -896,10 +888,10 @@ Bit8u bx_local_apic_c::acknowledge_int(void)
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int vector = highest_priority_int(irr);
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if (vector < 0) goto spurious;
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if((vector & 0xf0) <= get_ppr()) goto spurious;
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BX_ASSERT(irr[vector] == 1);
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BX_ASSERT(get_vector(irr, vector));
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BX_DEBUG(("acknowledge_int() returning vector 0x%02x", vector));
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irr[vector] = 0;
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isr[vector] = 1;
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clear_vector(irr, vector);
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set_vector(isr, vector);
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if(bx_dbg.apic) {
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BX_INFO(("Status after setting isr:"));
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print_status();
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@ -917,9 +909,9 @@ spurious:
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void bx_local_apic_c::print_status(void)
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{
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BX_INFO(("lapic %d: status is {:", apic_id));
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for(int vec=0; vec<BX_LAPIC_MAX_INTS; vec++) {
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if(irr[vec] || isr[vec]) {
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BX_INFO(("vec 0x%x: irr=%d, isr=%d", vec,(int)irr[vec],(int)isr[vec]));
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for(int vec=0; vec<256; vec++) {
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if(get_vector(irr, vec) || get_vector(isr, vec)) {
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BX_INFO(("vec: %u, irr=%u, isr=%u", get_vector(irr, vec), get_vector(isr, vec)));
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}
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}
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BX_INFO(("}"));
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@ -1010,7 +1002,7 @@ Bit8u bx_local_apic_c::get_apr(void)
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bx_bool bx_local_apic_c::is_focus(Bit8u vector)
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{
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if(focus_disable) return 0;
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return(irr[vector] || isr[vector]) ? 1 : 0;
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return get_vector(irr, vector) || get_vector(isr, vector);
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}
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void bx_local_apic_c::periodic_smf(void *this_ptr)
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@ -1394,23 +1386,23 @@ void bx_local_apic_c::register_state(bx_param_c *parent)
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BXRS_HEX_PARAM_SIMPLE(lapic, ldr);
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BXRS_HEX_PARAM_SIMPLE(lapic, dest_format);
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bx_list_c *ISR = new bx_list_c(lapic, "isr");
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bx_list_c *TMR = new bx_list_c(lapic, "tmr");
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bx_list_c *IRR = new bx_list_c(lapic, "irr");
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for (i=0; i<BX_LAPIC_MAX_INTS; i++) {
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sprintf(name, "0x%02x", i);
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new bx_shadow_num_c(ISR, name, &isr[i]);
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new bx_shadow_num_c(TMR, name, &tmr[i]);
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new bx_shadow_num_c(IRR, name, &irr[i]);
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for (i=0; i<8; i++) {
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sprintf(name, "isr%u", i);
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new bx_shadow_num_c(lapic, name, &isr[i], BASE_HEX);
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sprintf(name, "tmr%u", i);
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new bx_shadow_num_c(lapic, name, &tmr[i], BASE_HEX);
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sprintf(name, "irr%u", i);
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new bx_shadow_num_c(lapic, name, &irr[i], BASE_HEX);
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}
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#if BX_CPU_LEVEL >= 6
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if (cpu->is_cpu_extension_supported(BX_ISA_XAPIC_EXT)) {
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BXRS_HEX_PARAM_SIMPLE(lapic, xapic_ext);
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bx_list_c *IER = new bx_list_c(lapic, "ier");
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for (i=0; i<BX_LAPIC_MAX_INTS; i++) {
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sprintf(name, "0x%02x", i);
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new bx_shadow_num_c(IER, name, &ier[i]);
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for (i=0; i<8; i++) {
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sprintf(name, "ier%u", i);
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new bx_shadow_num_c(lapic, name, &ier[i], BASE_HEX);
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}
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}
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#endif
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@ -1420,10 +1412,9 @@ void bx_local_apic_c::register_state(bx_param_c *parent)
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BXRS_HEX_PARAM_SIMPLE(lapic, icr_hi);
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BXRS_HEX_PARAM_SIMPLE(lapic, icr_lo);
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bx_list_c *LVT = new bx_list_c(lapic, "lvt");
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for (i=0; i<APIC_LVT_ENTRIES; i++) {
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sprintf(name, "%u", i);
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new bx_shadow_num_c(LVT, name, &lvt[i], BASE_HEX);
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sprintf(name, "lvt%u", i);
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new bx_shadow_num_c(lapic, name, &lvt[i], BASE_HEX);
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}
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BXRS_HEX_PARAM_SIMPLE(lapic, timer_initial);
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@ -33,7 +33,6 @@ enum {
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const bx_phy_address BX_LAPIC_BASE_ADDR = 0xfee00000; // default Local APIC address
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#define BX_NUM_LOCAL_APICS BX_SMP_PROCESSORS
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#define BX_LAPIC_MAX_INTS 256
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enum {
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BX_APIC_GLOBALLY_DISABLED = 0,
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@ -155,19 +154,19 @@ class BOCHSAPI bx_local_apic_c : public logfunctions
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// ISR=in-service register. When an IRR bit is cleared, the corresponding
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// bit in ISR is set.
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Bit8u isr[BX_LAPIC_MAX_INTS];
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Bit32u isr[8];
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// TMR=trigger mode register. Cleared for edge-triggered interrupts
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// and set for level-triggered interrupts. If set, local APIC must send
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// EOI message to all other APICs.
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Bit8u tmr[BX_LAPIC_MAX_INTS];
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Bit32u tmr[8];
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// IRR=interrupt request register. When an interrupt is triggered by
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// the I/O APIC or another processor, it sets a bit in irr. The bit is
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// cleared when the interrupt is acknowledged by the processor.
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Bit8u irr[BX_LAPIC_MAX_INTS];
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Bit32u irr[8];
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#if BX_CPU_LEVEL >= 6
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// IER=interrupt enable register. Only vectors that are enabled in IER
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// participare in APIC's computation of highest priority pending interrupt.
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Bit8u ier[BX_LAPIC_MAX_INTS];
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Bit32u ier[8];
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#endif
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#define APIC_ERR_ILLEGAL_ADDR 0x80
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@ -214,6 +213,10 @@ class BOCHSAPI bx_local_apic_c : public logfunctions
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BX_CPU_C *cpu;
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bx_bool get_vector(Bit32u *reg, uint vector);
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void set_vector(Bit32u *reg, uint vector);
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void clear_vector(Bit32u *reg, uint vector);
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public:
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bx_bool INTR;
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bx_local_apic_c(BX_CPU_C *cpu, unsigned id);
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@ -238,7 +241,7 @@ public:
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void trigger_irq(Bit8u vector, unsigned trigger_mode, bx_bool bypass_irr_isr = 0);
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void untrigger_irq(Bit8u vector, unsigned trigger_mode);
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Bit8u acknowledge_int(void); // only the local CPU should call this
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int highest_priority_int(Bit8u *array);
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int highest_priority_int(Bit32u *array);
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void receive_EOI(Bit32u value);
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void send_ipi(apic_dest_t dest, Bit32u lo_cmd);
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void write_spurious_interrupt_register(Bit32u value);
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