list in debug CR4 more already published bits (UINTR)
fix debug print of XCR0
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@ -1022,7 +1022,8 @@ void bx_dbg_info_control_regs_command(void)
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dbg_printf(" PWT=page-level write-through=%d\n", (cr3>>3) & 1);
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#if BX_CPU_LEVEL >= 5
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Bit32u cr4 = SIM->get_param_num("CR4", dbg_cpu_list)->get();
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dbg_printf("CR4=0x%08x: %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s\n", cr4,
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dbg_printf("CR4=0x%08x: %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s\n", cr4,
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(cr4 & (1<<25)) ? "UINTR" : "uintr",
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(cr4 & (1<<24)) ? "PKS" : "pks",
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(cr4 & (1<<23)) ? "CET" : "cet",
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(cr4 & (1<<22)) ? "PKE" : "pke",
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@ -1063,9 +1064,10 @@ void bx_dbg_info_control_regs_command(void)
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#if BX_CPU_LEVEL >= 6
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if (BX_CPU(dbg_cpu)->is_cpu_extension_supported(BX_ISA_XSAVE)) {
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Bit32u xcr0 = SIM->get_param_num("XCR0", dbg_cpu_list)->get();
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dbg_printf("XCR0=0x%08x: %s %s %s %s %s %s %s %s %s %s %s\n", xcr0,
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(xcr0 & (1<<11)) ? "CET_S" : "cet_s",
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(xcr0 & (1<<10)) ? "CET_U" : "cet_u",
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dbg_printf("XCR0=0x%08x: %s %s %s %s %s %s %s %s %s %s %s %s\n", xcr0,
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(xcr0 & (1<<14)) ? "UINTR" : "uintr",
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(xcr0 & (1<<12)) ? "CET_S" : "cet_s",
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(xcr0 & (1<<11)) ? "CET_U" : "cet_u",
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(xcr0 & (1<<9)) ? "PKRU" : "pkru",
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(xcr0 & (1<<7)) ? "HI_ZMM" : "hi_zmm",
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(xcr0 & (1<<6)) ? "ZMM_HI256" : "zmm_hi256",
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@ -112,6 +112,7 @@ struct bx_cr0_t {
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#define BX_CR4_PKE_MASK (1 << 22)
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#define BX_CR4_CET_MASK (1 << 23)
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#define BX_CR4_PKS_MASK (1 << 24)
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#define BX_CR4_UINTR_MASK (1 << 25)
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struct bx_cr4_t {
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Bit32u val32; // 32bit value of register
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@ -144,6 +145,7 @@ struct bx_cr4_t {
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IMPLEMENT_CRREG_ACCESSORS(PKE, 22);
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IMPLEMENT_CRREG_ACCESSORS(CET, 23);
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IMPLEMENT_CRREG_ACCESSORS(PKS, 24);
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IMPLEMENT_CRREG_ACCESSORS(UINTR, 25);
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BX_CPP_INLINE Bit32u get32() const { return val32; }
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BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }
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