mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

implemented AVX IFMA instructions

Browse Source
This commit is contained in:
Stanislav Shwartsman 2022-10-02 22:08:20 +03:00
parent 698859df13
commit 9f76eaacea
4 changed files with 12 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
bochs/cpu/cpuid.cc
View File

@ -113,6 +113,7 @@ static const char *cpu_feature_name[] =
"avx512bitalg", // BX_ISA_AVX512_BITALG
"avx512vp2intersect", // BX_ISA_AVX512_VP2INTERSECT
"avx_vnni", // BX_ISA_AVX_VNNI
"avx_ifma", // BX_ISA_AVX_IFMA
"xapic", // BX_ISA_XAPIC
"x2apic", // BX_ISA_X2APIC
"xapicext", // BX_ISA_XAPICEXT

1
bochs/cpu/decoder/decoder.h
View File

@ -108,6 +108,7 @@ enum x86_feature_name {
BX_ISA_AVX512_BITALG, /* AVX-512 BITALG Instructions */
BX_ISA_AVX512_VP2INTERSECT, /* AVX-512 VP2INTERSECT Instructions */
BX_ISA_AVX_VNNI, /* AVX encoded VNNI Instructions */
BX_ISA_AVX_IFMA, /* AVX encoded IFMA Instructions */
BX_ISA_XAPIC, /* XAPIC support */
BX_ISA_X2APIC, /* X2APIC support */
BX_ISA_XAPIC_EXT, /* XAPIC Extensions support */

7
bochs/cpu/decoder/fetchdecode_avx.h
View File

@ -1114,6 +1114,9 @@ static const Bit64u BxOpcodeGroup_VEX_0F38AF[] = {
last_opcode(ATTR_SSE_PREFIX_66 | ATTR_VEX_W1, BX_IA_VFNMSUB213SD_VpdHsdWsd)
};
static const Bit64u BxOpcodeGroup_VEX_0F38B4[] = { last_opcode(ATTR_SSE_PREFIX_66 | ATTR_VEX_W1, BX_IA_VPMADD52LUQ_VdqHdqWdq) };
static const Bit64u BxOpcodeGroup_VEX_0F38B5[] = { last_opcode(ATTR_SSE_PREFIX_66 | ATTR_VEX_W1, BX_IA_VPMADD52HUQ_VdqHdqWdq) };
static const Bit64u BxOpcodeGroup_VEX_0F38B6[] = {
form_opcode(ATTR_SSE_PREFIX_66 | ATTR_VEX_W0, BX_IA_VFMADDSUB231PS_VpsHpsWps),
last_opcode(ATTR_SSE_PREFIX_66 | ATTR_VEX_W1, BX_IA_VFMADDSUB231PD_VpdHpdWpd)
@ -1872,8 +1875,8 @@ static const Bit64u *BxOpcodeTableVEX[256*3] = {
/* B1 */ ( BxOpcodeGroup_ERR ),
/* B2 */ ( BxOpcodeGroup_ERR ),
/* B3 */ ( BxOpcodeGroup_ERR ),
/* B4 */ ( BxOpcodeGroup_ERR ),
/* B5 */ ( BxOpcodeGroup_ERR ),
/* B4 */ ( BxOpcodeGroup_VEX_0F38B4 ),
/* B5 */ ( BxOpcodeGroup_VEX_0F38B5 ),
/* B6 */ ( BxOpcodeGroup_VEX_0F38B6 ),
/* B7 */ ( BxOpcodeGroup_VEX_0F38B7 ),
/* B8 */ ( BxOpcodeGroup_VEX_0F38B8 ),

5
bochs/cpu/decoder/ia_opcodes.def
View File

@ -2414,6 +2414,11 @@ bx_define_opcode(BX_IA_VPDPWSSD_VdqHdqWdq, "vpdpwssd", "vpdpwssd", &BX_CPU_C::LO
bx_define_opcode(BX_IA_VPDPWSSDS_VdqHdqWdq, "vpdpwssds", "vpdpwssds", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPDPWSSDS_VdqHdqWdqR, BX_ISA_AVX_VNNI, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_AVX)
// AVX VNNI
// AVX IFMA
bx_define_opcode(BX_IA_VPMADD52LUQ_VdqHdqWdq, "vpmadd52luq", "vpmadd52luq", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMADD52LUQ_VdqHdqWdqR, BX_ISA_AVX_IFMA, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VPMADD52HUQ_VdqHdqWdq, "vpmadd52huq", "vpmadd52huq", &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMADD52HUQ_VdqHdqWdqR, BX_ISA_AVX_IFMA, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_AVX)
// AVX IFMA
// BMI1 - VexW64 aliased
bx_define_opcode(BX_IA_ANDN_GdBdEd, "andn", "andnl", &BX_CPU_C::LOAD_Ed, &BX_CPU_C::ANDN_GdBdEdR, BX_ISA_BMI1, OP_Gd, OP_Bd, OP_Ed, OP_NONE, 0)
bx_define_opcode(BX_IA_ANDN_GqBqEq, "andn", "andnq", &BX_CPU_C::LOAD_Eq, &BX_CPU_C::ANDN_GqBqEqR, BX_ISA_BMI1, OP_Gq, OP_Bq, OP_Eq, OP_NONE, 0)