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avx
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regen Makefile include dependencies for CPU and internal debugger
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2021-01-30 20:17:15 +00:00 |
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cpudb
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Removed SVN property "executable" from some files.
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2021-02-21 09:25:33 +00:00 |
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decoder
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fix MSVC warnings
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2021-02-11 15:05:06 +00:00 |
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fpu
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Removed SVN property "executable" from some files.
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2021-02-21 09:25:33 +00:00 |
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3dnow.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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access2.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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access.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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access.h
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keep def of YMM/ZMM register even if AVX or EVEX are not compiled in and let reading/writing them to MEM
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2018-04-04 19:31:56 +00:00 |
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aes.cc
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avoid gcc 7.3 warning
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2018-05-27 19:09:59 +00:00 |
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apic.cc
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fixed some MSVC wannings in CPU code
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2021-02-08 13:06:44 +00:00 |
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apic.h
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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arith8.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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arith16.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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arith32.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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arith64.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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bcd.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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bit16.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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bit32.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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bit64.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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bit.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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bmi32.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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bmi64.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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call_far.cc
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Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
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2019-12-20 07:42:07 +00:00 |
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cet.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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cpu.cc
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fix MSVC warnings
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2021-02-11 15:05:06 +00:00 |
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cpu.h
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fixed some MSVC wannings in CPU code
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2021-02-08 13:06:44 +00:00 |
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cpuid.cc
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solve code duplication between different cpudb models
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2021-02-16 18:57:49 +00:00 |
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cpuid.h
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solve code duplication between different cpudb models
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2021-02-16 18:57:49 +00:00 |
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cpustats.h
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added few tlb specific cpustat counters
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2015-09-28 19:09:32 +00:00 |
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crc32.cc
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change a bit more defines to const with type
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2019-12-26 16:48:33 +00:00 |
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crregs.cc
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fixed SVM V_TPR handling SF bug #1428 AMD SVM Hyper-V fails
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2021-03-11 21:19:45 +00:00 |
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crregs.h
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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ctrl_xfer16.cc
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Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
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2019-12-20 07:42:07 +00:00 |
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ctrl_xfer32.cc
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Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
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2019-12-20 07:42:07 +00:00 |
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ctrl_xfer64.cc
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Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
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2019-12-20 07:42:07 +00:00 |
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ctrl_xfer_pro.cc
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Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
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2019-12-20 07:42:07 +00:00 |
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data_xfer8.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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data_xfer16.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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data_xfer32.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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data_xfer64.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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debugstuff.cc
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fixed compilation without bochs debugger
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2021-01-30 20:31:03 +00:00 |
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descriptor.h
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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event.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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exception.cc
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fixed some MSVC wannings in CPU code
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2021-02-08 13:06:44 +00:00 |
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faststring.cc
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Removed SVN property "executable" from some files.
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2021-02-21 09:25:33 +00:00 |
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flag_ctrl_pro.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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flag_ctrl.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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fpu_emu.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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generic_cpuid.cc
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solve code duplication between different cpudb models
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2021-02-16 18:57:49 +00:00 |
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generic_cpuid.h
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solve code duplication between different cpudb models
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2021-02-16 18:57:49 +00:00 |
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gf2.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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i387.h
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coding style changes, tab2space, macro2function or macro2const
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2019-10-17 19:23:27 +00:00 |
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icache.cc
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fix compilation with SMP enabled
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2021-01-31 14:03:28 +00:00 |
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icache.h
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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init.cc
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remove siminterface.h from bochs.h and include it only where required
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2021-01-30 19:40:18 +00:00 |
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io.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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iret.cc
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Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
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2019-12-20 07:42:07 +00:00 |
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jmp_far.cc
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Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
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2019-12-20 07:42:07 +00:00 |
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lazy_flags.h
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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load.cc
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Fixed buffer overflow in LOAD_Wdq method when MXCSR.MM=1 -> thanks new gcc10 warning
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2020-10-03 09:37:06 +00:00 |
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logical8.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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logical16.cc
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more faststring cleanup
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2019-10-14 14:54:07 +00:00 |
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logical32.cc
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more faststring cleanup
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2019-10-14 14:54:07 +00:00 |
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logical64.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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Makefile.in
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regen Makefile include dependencies for CPU and internal debugger
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2021-01-30 20:17:15 +00:00 |
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mmx.cc
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fixed behavior of MMX PSRAW/PSRAD instructions when shift count is zero - still has to invalidate x87 tags for dest register
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2020-12-15 20:05:54 +00:00 |
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msr.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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msr.h
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Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS)
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2020-05-29 12:35:30 +00:00 |
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mult8.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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mult16.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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mult32.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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mult64.cc
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extract Bit128 arithmetic to separate wide_int.cc/wide_int.h compiled independently of long mode emulation
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2020-05-19 16:01:23 +00:00 |
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mwait.cc
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remove siminterface.h from bochs.h and include it only where required
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2021-01-30 19:40:18 +00:00 |
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paging.cc
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remove bochs-memory.h from bochs.h and include it only where required
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2021-01-30 20:13:34 +00:00 |
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proc_ctrl.cc
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remove gui.h from bochs.h and include it only where required
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2021-01-30 18:47:25 +00:00 |
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protect_ctrl.cc
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applying SF patch #545 Speling fixes
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2019-12-09 16:29:23 +00:00 |
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rdrand.cc
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VMX: Fix RDRAND/RDSEED VMEXIT Instruction-Information Field
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2019-10-24 20:12:00 +00:00 |
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ret_far.cc
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Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
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2019-12-20 07:42:07 +00:00 |
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scalar_arith.h
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fix MSVC warnings
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2021-02-11 15:05:06 +00:00 |
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segment_ctrl_pro.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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segment_ctrl.cc
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VMX: save guest CET state to VMCS on vmexit
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2019-12-27 13:02:30 +00:00 |
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sha.cc
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fixed bug in SHA256RNDS2 instruction - wrong order of dwords in result
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2019-12-19 19:20:13 +00:00 |
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shift8.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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shift16.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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shift32.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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shift64.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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simd_compare.h
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Implement AVX512BW and AVX512DQ extensions published in recently published Intel Archtecture Extensions manual rev20.
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2014-07-18 11:14:25 +00:00 |
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simd_int.h
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fixed some MSVC wannings in CPU code
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2021-02-08 13:06:44 +00:00 |
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simd_pfp.h
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Added shape of implementation for last missing VSCALEF* AVX-512 instructons.
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2014-03-09 21:42:11 +00:00 |
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smm.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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smm.h
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Fixed SF bug [3548109] VMX State Not Restored After Entering SMM on 32-bit Systems
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2012-07-27 08:13:39 +00:00 |
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soft_int.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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sse_move.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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sse_pfp.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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sse_rcp.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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sse_string.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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sse.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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stack16.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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stack32.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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stack64.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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stack.cc
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split Bochs CPU TLB to DTLB and ITLB to avoid aliasing conflicts between them. ~5% speedup measured
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2019-12-09 18:37:02 +00:00 |
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stack.h
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Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
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2019-12-20 07:42:07 +00:00 |
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string.cc
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remove pc_system.h from bochs.h and include it only where required
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2021-01-30 18:29:28 +00:00 |
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svm.cc
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implement MSR PAR handling in AMD SVM
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2021-03-21 15:33:18 +00:00 |
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svm.h
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implement MSR PAR handling in AMD SVM
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2021-03-21 15:33:18 +00:00 |
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tasking.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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tlb.h
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fixed some MSVC wannings in CPU code
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2021-02-08 13:06:44 +00:00 |
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todo
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Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
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2019-12-20 07:42:07 +00:00 |
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vapic.cc
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remove bochs-memory.h from bochs.h and include it only where required
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2021-01-30 20:13:34 +00:00 |
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vm8086.cc
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Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071
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2019-12-20 07:42:07 +00:00 |
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vmcs.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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vmexit.cc
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remove pc_system.h from bochs.h and include it only where required
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2021-01-30 18:29:28 +00:00 |
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vmfunc.cc
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cleanup return value of all instruction handlers
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2018-02-16 07:57:32 +00:00 |
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vmx.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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vmx.h
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
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wide_int.cc
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extract Bit128 arithmetic to separate wide_int.cc/wide_int.h compiled independently of long mode emulation
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2020-05-19 16:01:23 +00:00 |
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wide_int.h
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extract Bit128 arithmetic to separate wide_int.cc/wide_int.h compiled independently of long mode emulation
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2020-05-19 16:01:23 +00:00 |
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xmm.h
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implemented AVX encoded VNNI instructions published in recent SDM - not tested yet
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2020-10-03 09:23:28 +00:00 |
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xsave.cc
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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2021-01-30 08:35:35 +00:00 |
