AVX512_VBMI2: Fixed shift count from register source for VBMI2 shift instructions (VPSHRDVD/VPSHLDVD/VPSHRDVQ/VPSHLDVQ)
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@ -706,7 +706,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VPSHLDVD_MASK_VdqHdqWdqR(bxInstruction_c *
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unsigned len = i->getVL();
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for (unsigned n=0; n < DWORD_ELEMENTS(len); n++) {
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unsigned count = op2.vmm16u(n) & 31;
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unsigned count = op2.vmm32u(n) & 31;
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if (count) {
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dst.vmm32u(n) = (dst.vmm32u(n) << count) | (op1.vmm32u(n) >> (32 - count));
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}
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@ -746,7 +746,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VPSHLDVQ_MASK_VdqHdqWdqR(bxInstruction_c *
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unsigned len = i->getVL();
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for (unsigned n=0; n < QWORD_ELEMENTS(len); n++) {
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unsigned count = op2.vmm16u(n) & 63;
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unsigned count = op2.vmm64u(n) & 63;
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if (count) {
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dst.vmm64u(n) = (dst.vmm64u(n) << count) | (op1.vmm64u(n) >> (64 - count));
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}
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@ -826,7 +826,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VPSHRDVD_MASK_VdqHdqWdqR(bxInstruction_c *
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unsigned len = i->getVL();
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for (unsigned n=0; n < DWORD_ELEMENTS(len); n++) {
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unsigned count = op2.vmm16u(n) & 31;
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unsigned count = op2.vmm32u(n) & 31;
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if (count) {
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dst.vmm32u(n) = (dst.vmm32u(n) >> count) | (op1.vmm32u(n) << (32 - count));
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}
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@ -866,7 +866,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VPSHRDVQ_MASK_VdqHdqWdqR(bxInstruction_c *
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unsigned len = i->getVL();
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for (unsigned n=0; n < QWORD_ELEMENTS(len); n++) {
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unsigned count = op2.vmm16u(n) & 63;
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unsigned count = op2.vmm64u(n) & 63;
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if (count) {
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dst.vmm64u(n) = (dst.vmm64u(n) >> count) | (op1.vmm64u(n) << (64 - count));
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}
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