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Bochs/bochs/cpu
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Satoshi Tanda 88f881c6d5
Fix that the INIT signal remains pending even after delivery of VM-exit/#VMEXIT(INIT) (#16) 
* Clear pending INIT signal

When the INIT signal is translated into corresponding VM-exit/#VMEXIT,
the signal should no longer be marked as pending. Otherwise, the signal
would be (incorrectly) delivered again.

* Remove trailing space and fix an incorrect indent
2022-07-24 07:14:01 +03:00
..
avx
remove cpudb.h from some Makefile dependencies. it should be only in cpu/init.cc and config.cc
2021-07-25 18:21:41 +00:00
cpudb
Applied two patches from Debian.
2021-09-10 15:33:22 +00:00
decoder
fix MSVC warnings
2021-02-11 15:05:06 +00:00
fpu
remove cpudb.h from some Makefile dependencies. TODO: it should be only in cpu/init.cc and config.cc
2021-07-25 18:06:31 +00:00
3dnow.cc
…
access2.cc
Fix two bugs around monitor/mwait
2022-07-13 21:51:15 -05:00
access.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
access.h
…
aes.cc
…
apic.cc
Removed APIC timer handles from save/restore list. They are set by the
2021-09-12 15:13:20 +00:00
apic.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
arith8.cc
…
arith16.cc
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arith32.cc
…
arith64.cc
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bcd.cc
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bit16.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
bit32.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
bit64.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
bit.cc
…
bmi32.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
bmi64.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
call_far.cc
…
cet.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
cpu.cc
fix MSVC warnings
2021-02-11 15:05:06 +00:00
cpu.h
more robust handling of SVM VMCB host ptr
2021-07-23 09:30:17 +00:00
cpuid.cc
solve code duplication between different cpudb models
2021-02-16 18:57:49 +00:00
cpuid.h
define and mention newly disclosed CPUID bits (#7)
2022-07-17 18:45:36 +03:00
cpustats.h
…
crc32.cc
…
crregs.cc
fixed SVM V_TPR handling SF bug #1428 AMD SVM Hyper-V fails
2021-03-11 21:19:45 +00:00
crregs.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
ctrl_xfer16.cc
…
ctrl_xfer32.cc
…
ctrl_xfer64.cc
…
ctrl_xfer_pro.cc
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data_xfer8.cc
…
data_xfer16.cc
…
data_xfer32.cc
…
data_xfer64.cc
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debugstuff.cc
fixed compilation without bochs debugger
2021-01-30 20:31:03 +00:00
descriptor.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
event.cc
Fix that the INIT signal remains pending even after delivery of VM-exit/#VMEXIT(INIT) (#16)
2022-07-24 07:14:01 +03:00
exception.cc
fixed some MSVC wannings in CPU code
2021-02-08 13:06:44 +00:00
faststring.cc
Removed SVN property "executable" from some files.
2021-02-21 09:25:33 +00:00
flag_ctrl_pro.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
flag_ctrl.cc
…
fpu_emu.cc
…
generic_cpuid.cc
solve code duplication between different cpudb models
2021-02-16 18:57:49 +00:00
generic_cpuid.h
solve code duplication between different cpudb models
2021-02-16 18:57:49 +00:00
gf2.cc
…
i387.h
…
icache.cc
fix compilation with SMP enabled
2021-01-31 14:03:28 +00:00
icache.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
init.cc
remove cpudb.h from bochs.h
2021-07-25 18:01:28 +00:00
io.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
iret.cc
…
jmp_far.cc
…
lazy_flags.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
load.cc
Fixed buffer overflow in LOAD_Wdq method when MXCSR.MM=1 -> thanks new gcc10 warning
2020-10-03 09:37:06 +00:00
logical8.cc
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logical16.cc
…
logical32.cc
…
logical64.cc
…
Makefile.in
Applied two patches from Debian.
2021-09-10 15:33:22 +00:00
mmx.cc
fixed behavior of MMX PSRAW/PSRAD instructions when shift count is zero - still has to invalidate x87 tags for dest register
2020-12-15 20:05:54 +00:00
msr.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
msr.h
…
mult8.cc
…
mult16.cc
…
mult32.cc
…
mult64.cc
…
mwait.cc
remove siminterface.h from bochs.h and include it only where required
2021-01-30 19:40:18 +00:00
paging.cc
Fix two bugs around monitor/mwait
2022-07-13 21:51:15 -05:00
proc_ctrl.cc
remove gui.h from bochs.h and include it only where required
2021-01-30 18:47:25 +00:00
protect_ctrl.cc
VMX: fixed exit qualification info for VMREAD/VMWRITE instructions
2021-07-03 14:31:14 +00:00
rdrand.cc
VMX: fixed exit qualification info for VMREAD/VMWRITE instructions
2021-07-03 14:31:14 +00:00
ret_far.cc
…
scalar_arith.h
fix MSVC warnings
2021-02-11 15:05:06 +00:00
segment_ctrl_pro.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
segment_ctrl.cc
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sha.cc
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shift8.cc
…
shift16.cc
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shift32.cc
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shift64.cc
…
simd_compare.h
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simd_int.h
fixed some MSVC wannings in CPU code
2021-02-08 13:06:44 +00:00
simd_pfp.h
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smm.cc
minor coding style modifications
2021-05-25 06:27:49 +00:00
smm.h
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soft_int.cc
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sse_move.cc
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sse_pfp.cc
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sse_rcp.cc
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sse_string.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
sse.cc
…
stack16.cc
…
stack32.cc
…
stack64.cc
…
stack.cc
…
stack.h
…
string.cc
remove pc_system.h from bochs.h and include it only where required
2021-01-30 18:29:28 +00:00
svm.cc
more robust handling of SVM VMCB host ptr
2021-07-23 09:30:17 +00:00
svm.h
implement MSR PAR handling in AMD SVM
2021-03-21 15:33:18 +00:00
tasking.cc
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
tlb.h
fixed some MSVC wannings in CPU code
2021-02-08 13:06:44 +00:00
todo
…
vapic.cc
remove bochs-memory.h from bochs.h and include it only where required
2021-01-30 20:13:34 +00:00
vm8086.cc
…
vmcs.cc
minor coding style modifications
2021-05-25 06:27:49 +00:00
vmexit.cc
VMX: fixed exit qualification info for VMREAD/VMWRITE instructions
2021-07-03 14:31:14 +00:00
vmfunc.cc
…
vmx.cc
Fix that the blocking by SMI bit maybe set when a VM-exit ends outside SMM (#15)
2022-07-23 19:36:31 +03:00
vmx.h
! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
2021-01-30 08:35:35 +00:00
wide_int.cc
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wide_int.h
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xmm.h
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xsave.cc
Fixed two compiler warnings in the cpu code.
2021-07-27 15:36:11 +00:00