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rename function to correct English, add broadcast and fault suppression support for EVEX encoded GFNI instructions

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This commit is contained in:
Stanislav Shwartsman 2019-12-21 16:12:06 +00:00
parent dd1ab303df
commit 4ac2122f3a
3 changed files with 6 additions and 10 deletions
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4
bochs/cpu/decoder/fetchdecode.h
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@ -161,7 +161,7 @@ enum {
BX_VMM_SCALAR = 0x5,
BX_VMM_HALF_VECTOR = 0x6,
BX_VMM_QUARTER_VECTOR = 0x7,
BX_VMM_OCT_VECTOR = 0x8,
BX_VMM_EIGHTH_VECTOR = 0x8,
BX_VMM_VEC128 = 0x9,
BX_VMM_VEC256 = 0xA
// encodings 0xB to 0xF are still free
@ -291,7 +291,7 @@ const Bit8u OP_mVdq32 = BX_FORM_SRC(BX_VMM_SCALAR_DWORD, BX_SRC_VECTOR_RM);
const Bit8u OP_mVdq64 = BX_FORM_SRC(BX_VMM_SCALAR_QWORD, BX_SRC_VECTOR_RM);
const Bit8u OP_mVHV = BX_FORM_SRC(BX_VMM_HALF_VECTOR, BX_SRC_VECTOR_RM);
const Bit8u OP_mVQV = BX_FORM_SRC(BX_VMM_QUARTER_VECTOR, BX_SRC_VECTOR_RM);
const Bit8u OP_mVOV = BX_FORM_SRC(BX_VMM_OCT_VECTOR, BX_SRC_VECTOR_RM);
const Bit8u OP_mVOV = BX_FORM_SRC(BX_VMM_EIGHTH_VECTOR, BX_SRC_VECTOR_RM);
const Bit8u OP_mVdq128 = BX_FORM_SRC(BX_VMM_VEC128, BX_SRC_VECTOR_RM);
const Bit8u OP_mVdq256 = BX_FORM_SRC(BX_VMM_VEC256, BX_SRC_VECTOR_RM);

2
bochs/cpu/decoder/fetchdecode32.cc
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@ -1648,7 +1648,7 @@ unsigned evex_displ8_compression(const bxInstruction_c *i, unsigned ia_opcode, u
#endif
return (4 * len);
case BX_VMM_OCT_VECTOR:
case BX_VMM_EIGHTH_VECTOR:
#if BX_SUPPORT_EVEX
BX_ASSERT(! i->getEvexb());
#endif

10
bochs/cpu/decoder/ia_opcodes.def
View File

@ -2237,12 +2237,10 @@ bx_define_opcode(BX_IA_VGF2P8AFFINEQB_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_C
bx_define_opcode(BX_IA_VGF2P8AFFINEINVQB_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VGF2P8AFFINEINVQB_VdqHdqWdqIbR, BX_ISA_GFNI, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VGF2P8MULB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VGF2P8MULB_VdqHdqWdqR, BX_ISA_GFNI, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_AVX)
// VexW64 aliased
bx_define_opcode(BX_IA_V128_VMOVD_VdqEd, &BX_CPU_C::MOVSS_VssWssM, &BX_CPU_C::MOVD_VdqEdR, BX_ISA_AVX, OP_Vdq, OP_Ed, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVQ_VdqEq, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::MOVQ_VdqEqR, BX_ISA_AVX, OP_Vdq, OP_Eq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVD_EdVd, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::MOVD_EdVdR, BX_ISA_AVX, OP_Ed, OP_Vd, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVQ_EqVq, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOVQ_EqVqR, BX_ISA_AVX, OP_Eq, OP_Vq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
// VexW64 aliased
bx_define_opcode(BX_IA_V128_VPINSRB_VdqEbIb, &BX_CPU_C::VPINSRB_VdqHdqEbIbM, &BX_CPU_C::VPINSRB_VdqHdqEbIbR, BX_ISA_AVX, OP_Vdq, OP_Hdq, OP_Ew, OP_Ib, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPINSRW_VdqEwIb, &BX_CPU_C::VPINSRW_VdqHdqEwIbM, &BX_CPU_C::VPINSRW_VdqHdqEwIbR, BX_ISA_AVX, OP_Vdq, OP_Hdq, OP_Ew, OP_Ib, BX_PREPARE_AVX)
@ -2250,12 +2248,10 @@ bx_define_opcode(BX_IA_V128_VPEXTRW_GdUdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXT
bx_define_opcode(BX_IA_V128_VPEXTRB_EbdVdqIb, &BX_CPU_C::PEXTRB_EbdVdqIbM, &BX_CPU_C::PEXTRB_EbdVdqIbR, BX_ISA_AVX, OP_Ebd, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPEXTRW_EwdVdqIb, &BX_CPU_C::PEXTRW_EwdVdqIbM, &BX_CPU_C::PEXTRW_EwdVdqIbR, BX_ISA_AVX, OP_Ewd, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_AVX)
// VexW64 aliased
bx_define_opcode(BX_IA_V128_VPINSRD_VdqEdIb, &BX_CPU_C::VPINSRD_VdqHdqEdIbM, &BX_CPU_C::VPINSRD_VdqHdqEdIbR, BX_ISA_AVX, OP_Vdq, OP_Hdq, OP_Ed, OP_Ib, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPINSRQ_VdqEqIb, &BX_CPU_C::VPINSRQ_VdqHdqEqIbM, &BX_CPU_C::VPINSRQ_VdqHdqEqIbR, BX_ISA_AVX, OP_Vdq, OP_Hdq, OP_Eq, OP_Ib, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPEXTRD_EdVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_ISA_AVX, OP_Ed, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPEXTRQ_EqVdqIb, &BX_CPU_C::PEXTRQ_EqVdqIbM, &BX_CPU_C::PEXTRQ_EqVdqIbR, BX_ISA_AVX, OP_Eq, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_AVX)
// VexW64 aliased
bx_define_opcode(BX_IA_VCVTPS2PD_VpdWps, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VCVTPS2PD_VpdWpsR, BX_ISA_AVX, OP_Vpd, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VCVTTPD2DQ_VdqWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VCVTTPD2DQ_VdqWpdR, BX_ISA_AVX, OP_Vq, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_AVX)
@ -3893,8 +3889,8 @@ bx_define_opcode(BX_IA_V512_VAESDECLAST_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_C
bx_define_opcode(BX_IA_V512_VPCLMULQDQ_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPCLMULQDQ_VdqHdqWdqIbR, BX_ISA_VAES_VPCLMULQDQ, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
// EVEX form of GFNI instructions
bx_define_opcode(BX_IA_V512_VGF2P8AFFINEQB_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VGF2P8AFFINEQB_VdqHdqWdqIbR, BX_ISA_GFNI, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE)
bx_define_opcode(BX_IA_V512_VGF2P8AFFINEINVQB_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VGF2P8AFFINEINVQB_VdqHdqWdqIbR, BX_ISA_GFNI, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_EVEX_NO_SAE)
bx_define_opcode(BX_IA_V512_VGF2P8MULB_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VGF2P8MULB_VdqHdqWdqR, BX_ISA_GFNI, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VGF2P8AFFINEQB_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VGF2P8AFFINEQB_VdqHdqWdqIbR, BX_ISA_GFNI, OP_Vdq, OP_Hdq, OP_mVpd, OP_Ib, BX_PREPARE_EVEX_NO_SAE)
bx_define_opcode(BX_IA_V512_VGF2P8AFFINEINVQB_VdqHdqWdqIb_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VGF2P8AFFINEINVQB_VdqHdqWdqIbR, BX_ISA_GFNI, OP_Vdq, OP_Hdq, OP_mVpd, OP_Ib, BX_PREPARE_EVEX_NO_SAE)
bx_define_opcode(BX_IA_V512_VGF2P8MULB_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_MASK_VectorB, &BX_CPU_C::VGF2P8MULB_VdqHdqWdqR, BX_ISA_GFNI, OP_Vdq, OP_Hdq, OP_mVpd, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
#endif // BX_SUPPORT_EVEX