increase max configurable msrs to 0x1000 again
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@ -1280,7 +1280,7 @@ bx_bool bx_local_apic_c::read_x2apic(unsigned index, Bit64u *val_64)
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*val_64 = read_aligned(index);
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break;
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default:
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BX_DEBUG(("read_x2apic: not supported apic register 0x%08x", index));
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BX_ERROR(("read_x2apic: not supported apic register 0x%08x", index));
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return 0;
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}
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@ -1366,7 +1366,7 @@ bx_bool bx_local_apic_c::write_x2apic(unsigned index, Bit32u val32_hi, Bit32u va
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case BX_LAPIC_TIMER_DIVIDE_CFG:
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break; // use legacy write
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default:
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BX_DEBUG(("write_x2apic: not supported apic register 0x%08x", index));
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BX_ERROR(("write_x2apic: not supported apic register 0x%08x", index));
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return 0;
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}
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@ -328,7 +328,7 @@ enum BxCpuMode {
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BX_MODE_LONG_64 = 4 // EFER.LMA = 1, CR0.PE=1, CS.L=1
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};
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const unsigned BX_MSR_MAX_INDEX = 0x800;
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const unsigned BX_MSR_MAX_INDEX = 0x1000;
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extern const char* cpu_mode_string(unsigned cpu_mode);
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