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coding style changes, tab2space, macro2function or macro2const

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This commit is contained in:
Stanislav Shwartsman 2019-10-17 19:23:27 +00:00
parent eec720c62b
commit 72b9d26717
4 changed files with 58 additions and 56 deletions
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3
bochs/cpu/crregs.h
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@ -141,8 +141,7 @@ struct bx_cr4_t {
BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }
};
#define BX_CR4_FLUSH_TLB_MASK \
(BX_CR4_PSE_MASK | BX_CR4_PAE_MASK | BX_CR4_PGE_MASK | BX_CR4_PCIDE_MASK | BX_CR4_SMEP_MASK | BX_CR4_SMAP_MASK | BX_CR4_PKE_MASK)
const Bit32u BX_CR4_FLUSH_TLB_MASK = (BX_CR4_PSE_MASK | BX_CR4_PAE_MASK | BX_CR4_PGE_MASK | BX_CR4_PCIDE_MASK | BX_CR4_SMEP_MASK | BX_CR4_SMAP_MASK | BX_CR4_PKE_MASK);
#endif // #if BX_CPU_LEVEL >= 5

52
bochs/cpu/fpu/status_w.h
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@ -25,42 +25,42 @@
#define _STATUS_H_
/* Status Word */
#define FPU_SW_Backward (0x8000) /* backward compatibility */
#define FPU_SW_C3 (0x4000) /* condition bit 3 */
#define FPU_SW_Top (0x3800) /* top of stack */
#define FPU_SW_C2 (0x0400) /* condition bit 2 */
#define FPU_SW_C1 (0x0200) /* condition bit 1 */
#define FPU_SW_C0 (0x0100) /* condition bit 0 */
#define FPU_SW_Summary (0x0080) /* exception summary */
#define FPU_SW_Stack_Fault (0x0040) /* stack fault */
#define FPU_SW_Precision (0x0020) /* loss of precision */
#define FPU_SW_Underflow (0x0010) /* underflow */
#define FPU_SW_Overflow (0x0008) /* overflow */
#define FPU_SW_Zero_Div (0x0004) /* divide by zero */
#define FPU_SW_Denormal_Op (0x0002) /* denormalized operand */
#define FPU_SW_Invalid (0x0001) /* invalid operation */
#define FPU_SW_Backward (0x8000) /* backward compatibility */
#define FPU_SW_C3 (0x4000) /* condition bit 3 */
#define FPU_SW_Top (0x3800) /* top of stack */
#define FPU_SW_C2 (0x0400) /* condition bit 2 */
#define FPU_SW_C1 (0x0200) /* condition bit 1 */
#define FPU_SW_C0 (0x0100) /* condition bit 0 */
#define FPU_SW_Summary (0x0080) /* exception summary */
#define FPU_SW_Stack_Fault (0x0040) /* stack fault */
#define FPU_SW_Precision (0x0020) /* loss of precision */
#define FPU_SW_Underflow (0x0010) /* underflow */
#define FPU_SW_Overflow (0x0008) /* overflow */
#define FPU_SW_Zero_Div (0x0004) /* divide by zero */
#define FPU_SW_Denormal_Op (0x0002) /* denormalized operand */
#define FPU_SW_Invalid (0x0001) /* invalid operation */
#define FPU_SW_CC (FPU_SW_C0|FPU_SW_C1|FPU_SW_C2|FPU_SW_C3)
#define FPU_SW_Exceptions_Mask (0x027f) /* status word exceptions bit mask */
#define FPU_SW_Exceptions_Mask (0x027f) /* status word exceptions bit mask */
/* Exception flags: */
#define FPU_EX_Precision (0x0020) /* loss of precision */
#define FPU_EX_Underflow (0x0010) /* underflow */
#define FPU_EX_Overflow (0x0008) /* overflow */
#define FPU_EX_Zero_Div (0x0004) /* divide by zero */
#define FPU_EX_Denormal (0x0002) /* denormalized operand */
#define FPU_EX_Invalid (0x0001) /* invalid operation */
#define FPU_EX_Precision (0x0020) /* loss of precision */
#define FPU_EX_Underflow (0x0010) /* underflow */
#define FPU_EX_Overflow (0x0008) /* overflow */
#define FPU_EX_Zero_Div (0x0004) /* divide by zero */
#define FPU_EX_Denormal (0x0002) /* denormalized operand */
#define FPU_EX_Invalid (0x0001) /* invalid operation */
/* Special exceptions: */
#define FPU_EX_Stack_Overflow (0x0041|FPU_SW_C1) /* stack overflow */
#define FPU_EX_Stack_Underflow (0x0041) /* stack underflow */
#define FPU_EX_Stack_Overflow (0x0041|FPU_SW_C1) /* stack overflow */
#define FPU_EX_Stack_Underflow (0x0041) /* stack underflow */
/* precision control */
#define FPU_EX_Precision_Lost_Up (EX_Precision | SW_C1)
#define FPU_EX_Precision_Lost_Dn (EX_Precision)
#define FPU_EX_Precision_Lost_Up (EX_Precision | SW_C1)
#define FPU_EX_Precision_Lost_Dn (EX_Precision)
#define setcc(cc) \
#define setcc(cc) \
FPU_PARTIAL_STATUS = (FPU_PARTIAL_STATUS & ~(FPU_SW_CC)) | ((cc) & FPU_SW_CC)
#define clear_C1() { FPU_PARTIAL_STATUS &= ~FPU_SW_C1; }

54
bochs/cpu/i387.h
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@ -52,32 +52,32 @@ struct BOCHSAPI_MSVCONLY i387_t
i387_t() {}
public:
void init(); // used by FINIT/FNINIT instructions
void reset(); // called on CPU reset
void init(); // used by FINIT/FNINIT instructions
void reset(); // called on CPU reset
int is_IA_masked() const { return (cwd & FPU_CW_Invalid); }
int is_IA_masked() const { return (cwd & FPU_CW_Invalid); }
Bit16u get_control_word() const { return cwd; }
Bit16u get_tag_word() const { return twd; }
Bit16u get_status_word() const { return (swd & ~FPU_SW_Top & 0xFFFF) | ((tos << 11) & FPU_SW_Top); }
Bit16u get_partial_status() const { return swd; }
Bit16u get_control_word() const { return cwd; }
Bit16u get_tag_word() const { return twd; }
Bit16u get_status_word() const { return (swd & ~FPU_SW_Top & 0xFFFF) | ((tos << 11) & FPU_SW_Top); }
Bit16u get_partial_status() const { return swd; }
void FPU_pop ();
void FPU_push();
void FPU_pop ();
void FPU_push();
void FPU_settagi(int tag, int stnr);
void FPU_settagi_valid(int stnr);
int FPU_gettagi(int stnr);
void FPU_settagi(int tag, int stnr);
void FPU_settagi_valid(int stnr);
int FPU_gettagi(int stnr);
floatx80 FPU_read_regi(int stnr) { return st_space[(tos+stnr) & 7]; }
void FPU_save_regi(floatx80 reg, int stnr);
void FPU_save_regi(floatx80 reg, int tag, int stnr);
floatx80 FPU_read_regi(int stnr) { return st_space[(tos+stnr) & 7]; }
void FPU_save_regi(floatx80 reg, int stnr);
void FPU_save_regi(floatx80 reg, int tag, int stnr);
public:
Bit16u cwd; // control word
Bit16u swd; // status word
Bit16u twd; // tag word
Bit16u foo; // last instruction opcode
Bit16u cwd; // control word
Bit16u swd; // status word
Bit16u twd; // tag word
Bit16u foo; // last instruction opcode
bx_address fip;
bx_address fdp;
@ -92,10 +92,10 @@ public:
unsigned char align3;
};
#define IS_TAG_EMPTY(i) \
#define IS_TAG_EMPTY(i) \
((BX_CPU_THIS_PTR the_i387.FPU_gettagi(i)) == FPU_Tag_Empty)
#define BX_READ_FPU_REG(i) \
#define BX_READ_FPU_REG(i) \
(BX_CPU_THIS_PTR the_i387.FPU_read_regi(i))
#define BX_WRITE_FPU_REG(value, i) \
@ -255,15 +255,15 @@ typedef BxPackedRegister BxPackedMmxRegister;
#define BX_MMX_REG(index) (BX_FPU_REG(index).fraction)
#define BX_READ_MMX_REG(index) \
#define BX_READ_MMX_REG(index) \
(*((const BxPackedMmxRegister*)(&(BX_MMX_REG(index)))))
#define BX_WRITE_MMX_REG(index, value) \
{ \
(BX_FPU_REG(index)).fraction = MMXUQ(value); \
(BX_FPU_REG(index)).exp = 0xffff; \
#define BX_WRITE_MMX_REG(index, value) \
{ \
(BX_FPU_REG(index)).fraction = MMXUQ(value); \
(BX_FPU_REG(index)).exp = 0xffff; \
}
#endif /* BX_SUPPORT_FPU */
#endif /* BX_SUPPORT_FPU */
#endif

5
bochs/cpu/tlb.h
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@ -35,7 +35,10 @@
const Bit32u BX_TLB_SIZE = 1024;
const Bit32u BX_TLB_MASK = ((BX_TLB_SIZE-1) << 12);
#define BX_TLB_INDEX_OF(lpf, len) ((((unsigned)(lpf) + (len)) & BX_TLB_MASK) >> 12)
BX_CPP_INLINE unsigned BX_TLB_INDEX_OF(bx_address lpf, unsigned len)
{
return (((unsigned(lpf) + len) & BX_TLB_MASK) >> 12);
}
typedef bx_ptr_equiv_t bx_hostpageaddr_t;