update CPUID bits and CR bits according to recently published SDM documents by Intel
This commit is contained in:
Stanislav Shwartsman
parent
8e0541fe5a
commit
a378441254
@ -1023,12 +1023,13 @@ void bx_dbg_info_control_regs_command(void)
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dbg_printf(" PWT=page-level write-through=%d\n", (cr3>>3) & 1);
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#if BX_CPU_LEVEL >= 5
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Bit32u cr4 = SIM->get_param_num("CR4", dbg_cpu_list)->get();
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dbg_printf("CR4=0x%08x: %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s\n", cr4,
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dbg_printf("CR4=0x%08x: %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s\n", cr4,
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(cr4 & (1<<24)) ? "PKS" : "pks",
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(cr4 & (1<<23)) ? "CET" : "cet",
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(cr4 & (1<<22)) ? "PKE" : "pke",
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(cr4 & (1<<21)) ? "SMAP" : "smap",
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(cr4 & (1<<20)) ? "SMEP" : "smep",
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(cr4 & (1<<19)) ? "KEYLOCK" : "keylock",
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(cr4 & (1<<18)) ? "OSXSAVE" : "osxsave",
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(cr4 & (1<<17)) ? "PCID" : "pcid",
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(cr4 & (1<<16)) ? "FSGSBASE" : "fsgsbase",
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@ -1063,16 +1064,18 @@ void bx_dbg_info_control_regs_command(void)
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#if BX_CPU_LEVEL >= 6
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if (BX_CPU(dbg_cpu)->is_cpu_extension_supported(BX_ISA_XSAVE)) {
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Bit32u xcr0 = SIM->get_param_num("XCR0", dbg_cpu_list)->get();
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dbg_printf("XCR0=0x%08x: %s %s %s %s %s %s %s %s %s\n", xcr0,
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(xcr0 & (1<<9)) ? "PKRU" : "pkru",
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(xcr0 & (1<<7)) ? "HI_ZMM" : "hi_zmm",
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(xcr0 & (1<<6)) ? "ZMM_HI256" : "zmm_hi256",
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(xcr0 & (1<<5)) ? "OPMASK" : "opmask",
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(xcr0 & (1<<4)) ? "BNDCFG" : "bndcfg",
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(xcr0 & (1<<3)) ? "BNDREGS" : "bndregs",
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(xcr0 & (1<<2)) ? "YMM" : "ymm",
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(xcr0 & (1<<1)) ? "SSE" : "sse",
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(xcr0 & (1<<0)) ? "FPU" : "fpu");
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dbg_printf("XCR0=0x%08x: %s %s %s %s %s %s %s %s %s %s %s\n", xcr0,
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(xcr0 & (1<<11)) ? "CET_S" : "cet_s",
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(xcr0 & (1<<10)) ? "CET_U" : "cet_u",
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(xcr0 & (1<<9)) ? "PKRU" : "pkru",
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(xcr0 & (1<<7)) ? "HI_ZMM" : "hi_zmm",
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(xcr0 & (1<<6)) ? "ZMM_HI256" : "zmm_hi256",
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(xcr0 & (1<<5)) ? "OPMASK" : "opmask",
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(xcr0 & (1<<4)) ? "BNDCFG" : "bndcfg",
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(xcr0 & (1<<3)) ? "BNDREGS" : "bndregs",
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(xcr0 & (1<<2)) ? "YMM" : "ymm",
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(xcr0 & (1<<1)) ? "SSE" : "sse",
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(xcr0 & (1<<0)) ? "FPU" : "fpu");
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}
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#endif
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}
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@ -400,6 +400,7 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
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// [16:16] LA57: LA57 and 5-level paging
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// [21:17] reserved
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// [22:22] RDPID: Read Processor ID support
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// [23:23] Keylocker
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// [24:23] reserved
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// [25:25] CLDEMOTE: CLDEMOTE instruction support
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// [26:26] reserved
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@ -432,7 +433,7 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
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#define BX_CPUID_EXT4_RESERVED20 (1 << 20)
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#define BX_CPUID_EXT4_RESERVED21 (1 << 21)
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#define BX_CPUID_EXT4_RDPID (1 << 22)
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#define BX_CPUID_EXT4_RESERVED23 (1 << 23)
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#define BX_CPUID_EXT4_KEYLOCKER (1 << 23)
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#define BX_CPUID_EXT4_RESERVED24 (1 << 24)
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#define BX_CPUID_EXT4_CLDEMOTE (1 << 25)
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#define BX_CPUID_EXT4_RESERVED26 (1 << 26)
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@ -448,7 +449,8 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
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// [2:2] AVX512 4VNNIW instructions support
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// [3:3] AVX512 4FMAPS instructions support
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// [4:4] Support of Fast REP MOV instructions with short length
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// [7:5] reserved
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// [5:5] UINTR: User interrupts support
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// [7:6] reserved
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// [8:8] AVX512 VP2INTERSECT instructions support
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// [9:9] reserved
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// [10:10] MD clear
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@ -458,7 +460,11 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
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// [16:16] TSXLDTRK: TSX suspent load tracking support
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// [19:17] reserved
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// [20:20] CET IBT: Support CET indirect branch tracking
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// [25:21] reserved
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// [21:21] reserved
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// [22:22] AMX BF16 support
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// [23:23] AVX512_FP16 instructions support
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// [24:24] AMX TILE architecture support
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// [25:25] AMX INT8 support
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// [26:26] IBRS and IBPB: Indirect branch restricted speculation (SCA)
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// [27:27] STIBP: Single Thread Indirect Branch Predictors supported (SCA)
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// [28:28] L1D_FLUSH supported (SCA)
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@ -471,7 +477,7 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
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#define BX_CPUID_EXT5_AVX512_4VNNIW (1 << 2)
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#define BX_CPUID_EXT5_AVX512_4FMAPS (1 << 3)
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#define BX_CPUID_EXT5_FAST_SHORT_REP_MOV (1 << 4)
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#define BX_CPUID_EXT5_RESERVED5 (1 << 5)
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#define BX_CPUID_EXT5_UINTR (1 << 5)
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#define BX_CPUID_EXT5_RESERVED6 (1 << 6)
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#define BX_CPUID_EXT5_RESERVED7 (1 << 7)
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#define BX_CPUID_EXT5_AVX512_VPINTERSECT (1 << 8)
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@ -488,10 +494,10 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
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#define BX_CPUID_EXT5_RESERVED19 (1 << 19)
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#define BX_CPUID_EXT5_CET_IBT (1 << 20)
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#define BX_CPUID_EXT5_RESERVED21 (1 << 21)
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#define BX_CPUID_EXT5_RESERVED22 (1 << 22)
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#define BX_CPUID_EXT5_RESERVED23 (1 << 23)
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#define BX_CPUID_EXT5_RESERVED24 (1 << 24)
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#define BX_CPUID_EXT5_RESERVED25 (1 << 25)
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#define BX_CPUID_EXT5_AMX_BF16 (1 << 22)
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#define BX_CPUID_EXT5_AVX512_FP16 (1 << 23)
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#define BX_CPUID_EXT5_AMX_TILE (1 << 24)
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#define BX_CPUID_EXT5_AMX_INT8 (1 << 25)
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#define BX_CPUID_EXT5_SCA_IBRS_IBPB (1 << 26)
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#define BX_CPUID_EXT5_SCA_STIBP (1 << 27)
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#define BX_CPUID_EXT5_L1D_FLUSH (1 << 28)
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@ -106,6 +106,7 @@ struct bx_cr0_t {
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#define BX_CR4_FSGSBASE_MASK (1 << 16)
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#define BX_CR4_PCIDE_MASK (1 << 17)
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#define BX_CR4_OSXSAVE_MASK (1 << 18)
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#define BX_CR4_KEYLOCKER_MASK (1 << 19)
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#define BX_CR4_SMEP_MASK (1 << 20)
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#define BX_CR4_SMAP_MASK (1 << 21)
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#define BX_CR4_PKE_MASK (1 << 22)
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@ -137,6 +138,7 @@ struct bx_cr4_t {
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#endif
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IMPLEMENT_CRREG_ACCESSORS(PCIDE, 17);
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IMPLEMENT_CRREG_ACCESSORS(OSXSAVE, 18);
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IMPLEMENT_CRREG_ACCESSORS(KEYLOCKER, 19);
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IMPLEMENT_CRREG_ACCESSORS(SMEP, 20);
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IMPLEMENT_CRREG_ACCESSORS(SMAP, 21);
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IMPLEMENT_CRREG_ACCESSORS(PKE, 22);
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@ -275,6 +277,9 @@ struct xcr0_t {
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BX_XCR0_PKRU_BIT = 9,
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BX_XCR0_CET_U_BIT = 11,
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BX_XCR0_CET_S_BIT = 12,
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BX_XCR0_UINTR_BIT = 14,
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BX_XCR0_XTILECFG_BIT = 17,
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BX_XCR0_XTILEDATA_BIT = 18,
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BX_XCR0_LAST
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};
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@ -290,6 +295,9 @@ struct xcr0_t {
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#define BX_XCR0_PKRU_MASK (1 << xcr0_t::BX_XCR0_PKRU_BIT)
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#define BX_XCR0_CET_U_MASK (1 << xcr0_t::BX_XCR0_CET_U_BIT)
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#define BX_XCR0_CET_S_MASK (1 << xcr0_t::BX_XCR0_CET_S_BIT)
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#define BX_XCR0_UINTR_MASK (1 << xcr0_t::BX_XCR0_UINTR_BIT)
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#define BX_XCR0_XTILECFG_MASK (1 << xcr0_t::BX_XCR0_XTILECFG_BIT)
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#define BX_XCR0_XTILEDATA_MASK (1 << xcr0_t::BX_XCR0_XTILEDATA_BIT)
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IMPLEMENT_CRREG_ACCESSORS(FPU, BX_XCR0_FPU_BIT);
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IMPLEMENT_CRREG_ACCESSORS(SSE, BX_XCR0_SSE_BIT);
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@ -301,6 +309,10 @@ struct xcr0_t {
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IMPLEMENT_CRREG_ACCESSORS(HI_ZMM, BX_XCR0_HI_ZMM_BIT);
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IMPLEMENT_CRREG_ACCESSORS(PT, BX_XCR0_PT_BIT);
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IMPLEMENT_CRREG_ACCESSORS(PKRU, BX_XCR0_PKRU_BIT);
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IMPLEMENT_CRREG_ACCESSORS(CET_U, BX_XCR0_CET_U_BIT);
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IMPLEMENT_CRREG_ACCESSORS(CET_S, BX_XCR0_CET_S_BIT);
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IMPLEMENT_CRREG_ACCESSORS(XTILECFG, BX_XCR0_XTILECFG_BIT);
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IMPLEMENT_CRREG_ACCESSORS(XTILEDATA, BX_XCR0_XTILEDATA_BIT);
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BX_CPP_INLINE Bit32u get32() const { return val32; }
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BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }
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