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remove BX_TRUE/BX_FALSE macros, use stdc++ true/false instead

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This commit is contained in:
Stanislav Shwartsman 2019-12-09 16:44:36 +00:00
parent 96e2c50bef
commit 44b3ebeca2
13 changed files with 87 additions and 90 deletions
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2
bochs/bochs.h
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@ -134,7 +134,7 @@ int bx_write_usb_options(FILE *fp, int maxports, bx_list_c *base);
Bit32u crc32(const Bit8u *buf, int len);
// used to print param tree from debugger
void print_tree(bx_param_c *node, int level = 0, bx_bool xml = BX_FALSE);
void print_tree(bx_param_c *node, int level = 0, bx_bool xml = false);
#if BX_ENABLE_STATISTICS
// print statistics

3
bochs/config.h.in
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@ -534,9 +534,6 @@ typedef Bit32u bx_phy_address;
// on any system.
typedef Bit32u bx_bool;
#define BX_TRUE (1)
#define BX_FALSE (0)
#if BX_WITH_MACOS
# define bx_ptr_t char *
#else

4
bochs/cpu/cpu.h
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@ -4268,8 +4268,8 @@ public: // for now...
BX_CPU_THIS_PTR espPageWindowSize = 0;
}
BX_SMF bx_bool write_virtual_checks(bx_segment_reg_t *seg, Bit32u offset, unsigned len, bx_bool align = BX_FALSE) BX_CPP_AttrRegparmN(4);
BX_SMF bx_bool read_virtual_checks(bx_segment_reg_t *seg, Bit32u offset, unsigned len, bx_bool align = BX_FALSE) BX_CPP_AttrRegparmN(4);
BX_SMF bx_bool write_virtual_checks(bx_segment_reg_t *seg, Bit32u offset, unsigned len, bx_bool align = false) BX_CPP_AttrRegparmN(4);
BX_SMF bx_bool read_virtual_checks(bx_segment_reg_t *seg, Bit32u offset, unsigned len, bx_bool align = false) BX_CPP_AttrRegparmN(4);
BX_SMF bx_bool execute_virtual_checks(bx_segment_reg_t *seg, Bit32u offset, unsigned len) BX_CPP_AttrRegparmN(3);
BX_SMF Bit8u read_linear_byte(unsigned seg, bx_address offset) BX_CPP_AttrRegparmN(2);

4
bochs/cpu/decoder/disasm.cc
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@ -608,13 +608,13 @@ char* disasm(char *disbufptr, const bxInstruction_c *i, bx_address cs_base, bx_a
const char *opname = i->getIaOpcodeNameShort(); // skip the "BX_IA_"
unsigned n;
#if BX_SUPPORT_EVEX
bx_bool is_vector = BX_FALSE;
bx_bool is_vector = false;
#endif
if (! strncmp(opname, "V128_", 5) || ! strncmp(opname, "V256_", 5) || ! strncmp(opname, "V512_", 5)) {
opname += 5;
#if BX_SUPPORT_EVEX
is_vector = BX_TRUE;
is_vector = true;
#endif
}

46
bochs/cpu/decoder/fetchdecode32.cc
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@ -1700,13 +1700,13 @@ bx_bool assign_srcs(bxInstruction_c *i, unsigned ia_opcode, unsigned nnn, unsign
}
}
return BX_TRUE;
return true;
}
#if BX_SUPPORT_AVX
bx_bool assign_srcs(bxInstruction_c *i, unsigned ia_opcode, bx_bool is_64, unsigned nnn, unsigned rm, unsigned vvv, unsigned vex_w, bx_bool had_evex = BX_FALSE, bx_bool displ8 = BX_FALSE)
bx_bool assign_srcs(bxInstruction_c *i, unsigned ia_opcode, bx_bool is_64, unsigned nnn, unsigned rm, unsigned vvv, unsigned vex_w, bx_bool had_evex = false, bx_bool displ8 = false)
{
bx_bool use_vvv = BX_FALSE;
bx_bool use_vvv = false;
#if BX_SUPPORT_EVEX
unsigned displ8_scale = 1;
#endif
@ -1717,7 +1717,7 @@ bx_bool assign_srcs(bxInstruction_c *i, unsigned ia_opcode, bx_bool is_64, unsig
unsigned type = BX_DISASM_SRC_TYPE(src);
src = BX_DISASM_SRC_ORIGIN(src);
#if BX_SUPPORT_EVEX
bx_bool mem_src = BX_FALSE;
bx_bool mem_src = false;
#endif
switch(src) {
@ -1732,7 +1732,7 @@ bx_bool assign_srcs(bxInstruction_c *i, unsigned ia_opcode, bx_bool is_64, unsig
case BX_SRC_NNN:
i->setSrcReg(n, nnn);
if (type == BX_KMASK_REG) {
if (nnn >= 8) return BX_FALSE;
if (nnn >= 8) return false;
}
break;
case BX_SRC_RM:
@ -1744,7 +1744,7 @@ bx_bool assign_srcs(bxInstruction_c *i, unsigned ia_opcode, bx_bool is_64, unsig
}
else {
#if BX_SUPPORT_EVEX
mem_src = BX_TRUE;
mem_src = true;
#endif
i->setSrcReg(n, (type == BX_VMM_REG) ? BX_VECTOR_TMP_REGISTER : BX_TMP_REGISTER);
}
@ -1756,17 +1756,17 @@ bx_bool assign_srcs(bxInstruction_c *i, unsigned ia_opcode, bx_bool is_64, unsig
else {
i->setSrcReg(n, BX_VECTOR_TMP_REGISTER);
#if BX_SUPPORT_EVEX
mem_src = BX_TRUE;
mem_src = true;
if (n == 0) // zero masking is not allowed for memory destination
if (i->isZeroMasking()) return BX_FALSE;
if (i->isZeroMasking()) return false;
#endif
}
break;
case BX_SRC_VVV:
i->setSrcReg(n, vvv);
use_vvv = BX_TRUE;
use_vvv = true;
if (type == BX_KMASK_REG) {
if (vvv >= 8) return BX_FALSE;
if (vvv >= 8) return false;
}
break;
case BX_SRC_VIB:
@ -1784,13 +1784,13 @@ bx_bool assign_srcs(bxInstruction_c *i, unsigned ia_opcode, bx_bool is_64, unsig
break;
case BX_SRC_VSIB:
if (! i->as32L() || i->sibIndex() == BX_NIL_REGISTER) {
return BX_FALSE;
return false;
}
#if BX_SUPPORT_EVEX
i->setSibIndex(i->sibIndex() | (vvv & 0x10));
// zero masking is not allowed for gather/scatter
if (i->isZeroMasking()) return BX_FALSE;
mem_src = BX_TRUE;
if (i->isZeroMasking()) return false;
mem_src = true;
#endif
break;
default:
@ -1815,10 +1815,10 @@ bx_bool assign_srcs(bxInstruction_c *i, unsigned ia_opcode, bx_bool is_64, unsig
#endif
if (! use_vvv && vvv != 0) {
return BX_FALSE;
return false;
}
return BX_TRUE;
return true;
}
#endif
@ -1930,7 +1930,7 @@ int decoder_vex32(const Bit8u *iptr, unsigned &remain, bxInstruction_c *i, unsig
}
}
if (! assign_srcs(i, ia_opcode, BX_FALSE, nnn, rm, vvv, vex_w))
if (! assign_srcs(i, ia_opcode, false, nnn, rm, vvv, vex_w))
ia_opcode = BX_IA_ERROR;
#endif
@ -1952,7 +1952,7 @@ int decoder_evex32(const Bit8u *iptr, unsigned &remain, bxInstruction_c *i, unsi
}
#if BX_SUPPORT_EVEX
bx_bool displ8 = BX_FALSE;
bx_bool displ8 = false;
if (sse_prefix)
return(BX_IA_ERROR);
@ -2030,7 +2030,7 @@ int decoder_evex32(const Bit8u *iptr, unsigned &remain, bxInstruction_c *i, unsi
return(-1);
if (modrm.mod == 0x40) { // mod==01b
displ8 = BX_TRUE;
displ8 = true;
}
// EVEX.b in reg form implies 512-bit vector length
@ -2065,7 +2065,7 @@ int decoder_evex32(const Bit8u *iptr, unsigned &remain, bxInstruction_c *i, unsi
}
}
if (! assign_srcs(i, ia_opcode, BX_FALSE, modrm.nnn, modrm.rm, vvv, vex_w, BX_TRUE, displ8))
if (! assign_srcs(i, ia_opcode, false, modrm.nnn, modrm.rm, vvv, vex_w, true, displ8))
ia_opcode = BX_IA_ERROR;
// EVEX specific #UD conditions
@ -2140,10 +2140,10 @@ int decoder_xop32(const Bit8u *iptr, unsigned &remain, bxInstruction_c *i, unsig
ia_opcode = findOpcode(BxOpcodeTableXOP[opcode_byte], decmask);
if (fetchImmediate(iptr, remain, i, ia_opcode, BX_FALSE) < 0)
if (fetchImmediate(iptr, remain, i, ia_opcode, false) < 0)
return (-1);
if (! assign_srcs(i, ia_opcode, BX_FALSE, modrm.nnn, modrm.rm, vvv, vex_w))
if (! assign_srcs(i, ia_opcode, false, modrm.nnn, modrm.rm, vvv, vex_w))
ia_opcode = BX_IA_ERROR;
#endif
@ -2208,7 +2208,7 @@ int decoder32_modrm(const Bit8u *iptr, unsigned &remain, bxInstruction_c *i, uns
Bit16u ia_opcode = findOpcode((Bit64u *) opcode_table, decmask);
if (fetchImmediate(iptr, remain, i, ia_opcode, BX_FALSE) < 0)
if (fetchImmediate(iptr, remain, i, ia_opcode, false) < 0)
return (-1);
assign_srcs(i, ia_opcode, modrm.nnn, modrm.rm);
@ -2231,7 +2231,7 @@ int decoder32(const Bit8u *iptr, unsigned &remain, bxInstruction_c *i, unsigned
Bit16u ia_opcode = findOpcode((Bit64u *) opcode_table, decmask);
if (fetchImmediate(iptr, remain, i, ia_opcode, BX_FALSE) < 0)
if (fetchImmediate(iptr, remain, i, ia_opcode, false) < 0)
return (-1);
assign_srcs(i, ia_opcode, nnn, rm);

18
bochs/cpu/decoder/fetchdecode64.cc
View File

@ -104,7 +104,7 @@ extern Bit16u findOpcode(const Bit64u *opMap, Bit32u opMsk);
extern bx_bool assign_srcs(bxInstruction_c *i, unsigned ia_opcode, unsigned nnn, unsigned rm);
#if BX_SUPPORT_AVX
extern bx_bool assign_srcs(bxInstruction_c *i, unsigned ia_opcode, bx_bool is_64, unsigned nnn, unsigned rm, unsigned vvv, unsigned vex_w, bx_bool had_evex = BX_FALSE, bx_bool displ8 = BX_FALSE);
extern bx_bool assign_srcs(bxInstruction_c *i, unsigned ia_opcode, bx_bool is_64, unsigned nnn, unsigned rm, unsigned vvv, unsigned vex_w, bx_bool had_evex = false, bx_bool displ8 = false);
#endif
extern const Bit8u *decodeModrm64(const Bit8u *iptr, unsigned &remain, bxInstruction_c *i, unsigned mod, unsigned nnn, unsigned rm, unsigned rex_r, unsigned rex_x, unsigned rex_b);
@ -1276,7 +1276,7 @@ int decoder_vex64(const Bit8u *iptr, unsigned &remain, bxInstruction_c *i, unsig
}
}
if (! assign_srcs(i, ia_opcode, BX_TRUE, nnn, rm, vvv, vex_w))
if (! assign_srcs(i, ia_opcode, true, nnn, rm, vvv, vex_w))
ia_opcode = BX_IA_ERROR;
#endif
@ -1295,7 +1295,7 @@ int decoder_evex64(const Bit8u *iptr, unsigned &remain, bxInstruction_c *i, unsi
unsigned rm = 0, mod = 0, nnn = 0;
unsigned b2 = 0;
bx_bool displ8 = BX_FALSE;
bx_bool displ8 = false;
// EVEX prefix 0x62
assert(b1 == 0x62);
@ -1396,7 +1396,7 @@ int decoder_evex64(const Bit8u *iptr, unsigned &remain, bxInstruction_c *i, unsi
if (! iptr)
return(-1);
if (mod == 0x40) { // mod==01b
displ8 = BX_TRUE;
displ8 = true;
}
}
@ -1433,7 +1433,7 @@ int decoder_evex64(const Bit8u *iptr, unsigned &remain, bxInstruction_c *i, unsi
}
}
if (! assign_srcs(i, ia_opcode, BX_TRUE, nnn, rm, vvv, vex_w, BX_TRUE, displ8))
if (! assign_srcs(i, ia_opcode, true, nnn, rm, vvv, vex_w, true, displ8))
ia_opcode = BX_IA_ERROR;
// EVEX specific #UD conditions
@ -1537,10 +1537,10 @@ int decoder_xop64(const Bit8u *iptr, unsigned &remain, bxInstruction_c *i, unsig
ia_opcode = findOpcode(BxOpcodeTableXOP[opcode_byte], decmask);
if (fetchImmediate(iptr, remain, i, ia_opcode, BX_TRUE) < 0)
if (fetchImmediate(iptr, remain, i, ia_opcode, true) < 0)
return (-1);
if (! assign_srcs(i, ia_opcode, BX_TRUE, nnn, rm, vvv, vex_w))
if (! assign_srcs(i, ia_opcode, true, nnn, rm, vvv, vex_w))
ia_opcode = BX_IA_ERROR;
#endif
@ -1606,7 +1606,7 @@ int decoder64_modrm(const Bit8u *iptr, unsigned &remain, bxInstruction_c *i, uns
Bit16u ia_opcode = findOpcode((const Bit64u*) opcode_table, decmask);
if (fetchImmediate(iptr, remain, i, ia_opcode, BX_TRUE) < 0)
if (fetchImmediate(iptr, remain, i, ia_opcode, true) < 0)
return (-1);
assign_srcs(i, ia_opcode, modrm.nnn, modrm.rm);
@ -1637,7 +1637,7 @@ int decoder64(const Bit8u *iptr, unsigned &remain, bxInstruction_c *i, unsigned
Bit16u ia_opcode = findOpcode((const Bit64u*) opcode_table, decmask);
if (fetchImmediate(iptr, remain, i, ia_opcode, BX_TRUE) < 0)
if (fetchImmediate(iptr, remain, i, ia_opcode, true) < 0)
return (-1);
assign_srcs(i, ia_opcode, nnn, rm);

4
bochs/cpu/icache.h
View File

@ -203,9 +203,9 @@ public:
// break all links bewteen traces
if (++traceLinkTimeStamp == 0xffffffff) {
flushICacheEntries();
return BX_TRUE;
return true;
}
return BX_FALSE;
return false;
}
};

12
bochs/cpu/msr.cc
View File

@ -480,9 +480,9 @@ bx_bool isMemTypeValidMTRR(unsigned memtype)
case BX_MEMTYPE_WT:
case BX_MEMTYPE_WP:
case BX_MEMTYPE_WB:
return BX_TRUE;
return true;
default:
return BX_FALSE;
return false;
}
}
@ -496,9 +496,9 @@ bx_bool isValidMSR_PAT(Bit64u pat_val)
// use packed register as 64-bit value with convinient accessors
BxPackedRegister pat_msr = pat_val;
for (unsigned i=0; i<8; i++)
if (! isMemTypeValidPAT(pat_msr.ubyte(i))) return BX_FALSE;
if (! isMemTypeValidPAT(pat_msr.ubyte(i))) return false;
return BX_TRUE;
return true;
}
bx_bool isValidMSR_FixedMTRR(Bit64u fixed_mtrr_val)
@ -506,9 +506,9 @@ bx_bool isValidMSR_FixedMTRR(Bit64u fixed_mtrr_val)
// use packed register as 64-bit value with convinient accessors
BxPackedRegister fixed_mtrr_msr = fixed_mtrr_val;
for (unsigned i=0; i<8; i++)
if (! isMemTypeValidMTRR(fixed_mtrr_msr.ubyte(i))) return BX_FALSE;
if (! isMemTypeValidMTRR(fixed_mtrr_msr.ubyte(i))) return false;
return BX_TRUE;
return true;
}
#endif

20
bochs/cpu/vapic.cc
View File

@ -33,32 +33,32 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::is_virtual_apic_page(bx_phy_address pad
if (BX_CPU_THIS_PTR in_vmx_guest) {
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_VIRTUALIZE_APIC_ACCESSES))
if (PPFOf(paddr) == vm->apic_access_page) return BX_TRUE;
if (PPFOf(paddr) == vm->apic_access_page) return true;
}
return BX_FALSE;
return false;
}
bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::virtual_apic_access_vmexit(unsigned offset, unsigned len)
{
if((offset & ~0x3) != ((offset+len-1) & ~0x3)) {
BX_ERROR(("Virtual APIC access at offset 0x%08x spans 32-bit boundary !", offset));
return BX_TRUE;
return true;
}
if (is_pending(BX_EVENT_VMX_VTPR_UPDATE | BX_EVENT_VMX_VEOI_UPDATE | BX_EVENT_VMX_VIRTUAL_APIC_WRITE)) {
if (BX_CPU_THIS_PTR vmcs.apic_access != offset) {
BX_ERROR(("Second APIC virtualization at offset 0x%08x (first access at offset 0x%08x)", offset, BX_CPU_THIS_PTR vmcs.apic_access));
return BX_TRUE;
return true;
}
}
// access is not instruction fetch because cpu::prefetch will crash them
if (! VMEXIT(VMX_VM_EXEC_CTRL2_TPR_SHADOW) || len > 4 || offset >= 0x400)
return BX_TRUE;
return true;
BX_CPU_THIS_PTR vmcs.apic_access = offset;
return BX_FALSE;
return false;
}
Bit32u BX_CPU_C::VMX_Read_Virtual_APIC(unsigned offset)
@ -467,7 +467,7 @@ bx_bool BX_CPU_C::Virtualize_X2APIC_Write(unsigned msr, Bit64u val_64)
VMX_Write_Virtual_APIC(BX_LAPIC_TPR + 4, 0);
VMX_TPR_Virtualization();
return BX_TRUE;
return true;
}
#if BX_SUPPORT_VMX >= 2
@ -479,7 +479,7 @@ bx_bool BX_CPU_C::Virtualize_X2APIC_Write(unsigned msr, Bit64u val_64)
VMX_EOI_Virtualization();
return BX_TRUE;
return true;
}
if (msr == 0x83f) {
@ -497,12 +497,12 @@ bx_bool BX_CPU_C::Virtualize_X2APIC_Write(unsigned msr, Bit64u val_64)
VMX_Self_IPI_Virtualization(vector);
}
return BX_TRUE;
return true;
}
}
#endif
return BX_FALSE;
return false;
}
#endif // BX_SUPPORT_VMX && BX_SUPPORT_X86_64

6
bochs/cpu/vmcs.cc
View File

@ -89,14 +89,14 @@ bx_bool VMCS_Mapping::clear_mapping(Bit32u encoding)
bx_bool VMCS_Mapping::set_mapping(Bit32u encoding, Bit32u offset)
{
if (is_reserved(encoding))
return BX_FALSE;
return false;
unsigned field = VMCS_FIELD(encoding);
if (field >= VMX_HIGHEST_VMCS_ENCODING)
return BX_FALSE;
return false;
vmcs_map[VMCS_FIELD_INDEX(encoding)][field] = offset;
return BX_TRUE;
return true;
}
unsigned VMCS_Mapping::vmcs_field_offset(Bit32u encoding) const

20
bochs/cpu/vmexit.cc
View File

@ -669,15 +669,15 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::Vmexit_Vmread(bxInstruction_c *i)
{
BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
if (! SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_VMCS_SHADOWING)) return BX_TRUE;
if (! SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_VMCS_SHADOWING)) return true;
#if BX_SUPPORT_X86_64
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
if (BX_READ_64BIT_REG_HIGH(i->src())) return BX_TRUE;
if (BX_READ_64BIT_REG_HIGH(i->src())) return true;
}
#endif
unsigned encoding = BX_READ_32BIT_REG(i->src());
if (encoding > 0x7fff) return BX_TRUE;
if (encoding > 0x7fff) return true;
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
@ -687,24 +687,24 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::Vmexit_Vmread(bxInstruction_c *i)
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, MEMTYPE(resolve_memtype(pAddr)), BX_READ, BX_VMREAD_BITMAP_ACCESS, &bitmap);
if (bitmap & (1 << (encoding & 7)))
return BX_TRUE;
return true;
return BX_FALSE;
return false;
}
bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::Vmexit_Vmwrite(bxInstruction_c *i)
{
BX_ASSERT(BX_CPU_THIS_PTR in_vmx_guest);
if (! SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_VMCS_SHADOWING)) return BX_TRUE;
if (! SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_VMCS_SHADOWING)) return true;
#if BX_SUPPORT_X86_64
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
if (BX_READ_64BIT_REG_HIGH(i->dst())) return BX_TRUE;
if (BX_READ_64BIT_REG_HIGH(i->dst())) return true;
}
#endif
unsigned encoding = BX_READ_32BIT_REG(i->dst());
if (encoding > 0x7fff) return BX_TRUE;
if (encoding > 0x7fff) return true;
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
@ -714,9 +714,9 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::Vmexit_Vmwrite(bxInstruction_c *i)
BX_NOTIFY_PHY_MEMORY_ACCESS(pAddr, 1, MEMTYPE(resolve_memtype(pAddr)), BX_READ, BX_VMWRITE_BITMAP_ACCESS, &bitmap);
if (bitmap & (1 << (encoding & 7)))
return BX_TRUE;
return true;
return BX_FALSE;
return false;
}
void BX_CPU_C::Virtualization_Exception(Bit64u qualification, Bit64u guest_physical, Bit64u guest_linear)

26
bochs/cpu/xsave.cc
View File

@ -731,14 +731,14 @@ bx_bool BX_CPU_C::xsave_x87_state_xinuse(void)
BX_CPU_THIS_PTR the_i387.get_tag_word() != 0xFFFF ||
BX_CPU_THIS_PTR the_i387.foo != 0 ||
BX_CPU_THIS_PTR the_i387.fip != 0 || BX_CPU_THIS_PTR the_i387.fcs != 0 ||
BX_CPU_THIS_PTR the_i387.fdp != 0 || BX_CPU_THIS_PTR the_i387.fds != 0) return BX_TRUE;
BX_CPU_THIS_PTR the_i387.fdp != 0 || BX_CPU_THIS_PTR the_i387.fds != 0) return true;
for (unsigned index=0;index<8;index++) {
floatx80 reg = BX_FPU_REG(index);
if (reg.exp != 0 || reg.fraction != 0) return BX_TRUE;
if (reg.exp != 0 || reg.fraction != 0) return true;
}
return BX_FALSE;
return false;
}
// SSE state management //
@ -784,11 +784,11 @@ bx_bool BX_CPU_C::xsave_sse_state_xinuse(void)
// set XMM8-XMM15 only in 64-bit mode
if (index < 8 || long64_mode()) {
const BxPackedXmmRegister *reg = &BX_XMM_REG(index);
if (! is_clear(reg)) return BX_TRUE;
if (! is_clear(reg)) return true;
}
}
return BX_FALSE;
return false;
}
#if BX_SUPPORT_AVX
@ -836,11 +836,11 @@ bx_bool BX_CPU_C::xsave_ymm_state_xinuse(void)
// set YMM8-YMM15 only in 64-bit mode
if (index < 8 || long64_mode()) {
const BxPackedXmmRegister *reg = &BX_READ_AVX_REG_LANE(index, 1);
if (! is_clear(reg)) return BX_TRUE;
if (! is_clear(reg)) return true;
}
}
return BX_FALSE;
return false;
}
#if BX_SUPPORT_EVEX
@ -879,10 +879,10 @@ void BX_CPU_C::xrstor_init_opmask_state(void)
bx_bool BX_CPU_C::xsave_opmask_state_xinuse(void)
{
for(unsigned index=0; index < 8; index++) {
if (BX_READ_OPMASK(index)) return BX_TRUE;
if (BX_READ_OPMASK(index)) return true;
}
return BX_FALSE;
return false;
}
// ZMM_HI256 (upper part of zmm0..zmm15 registers) state management //
@ -920,11 +920,11 @@ bx_bool BX_CPU_C::xsave_zmm_hi256_state_xinuse(void)
for(unsigned index=0; index < 16; index++) {
for (unsigned n=2; n < 4; n++) {
const BxPackedXmmRegister *reg = &BX_READ_AVX_REG_LANE(index, n);
if (! is_clear(reg)) return BX_TRUE;
if (! is_clear(reg)) return true;
}
}
return BX_FALSE;
return false;
}
// HI_ZMM (zmm15..zmm31) state management //
@ -962,11 +962,11 @@ bx_bool BX_CPU_C::xsave_hi_zmm_state_xinuse(void)
for(unsigned index=16; index < 32; index++) {
for (unsigned n=0; n < 4; n++) {
const BxPackedXmmRegister *reg = &BX_READ_AVX_REG_LANE(index, n);
if (! is_clear(reg)) return BX_TRUE;
if (! is_clear(reg)) return true;
}
}
return BX_FALSE;
return false;
}
#endif // BX_SUPPORT_EVEX

12
bochs/gui/paramtree.h
View File

@ -174,7 +174,7 @@ public:
virtual int parse_param(const char *value) { return -1; }
virtual void dump_param(FILE *fp) {}
virtual int dump_param(char *buf, int buflen, bx_bool dquotes = BX_FALSE) { return 0; }
virtual int dump_param(char *buf, int buflen, bx_bool dquotes = false) { return 0; }
};
typedef Bit64s (*param_event_handler)(class bx_param_c *, int set, Bit64s val);
@ -239,7 +239,7 @@ public:
#endif
virtual int parse_param(const char *value);
virtual void dump_param(FILE *fp);
virtual int dump_param(char *buf, int buflen, bx_bool dquotes = BX_FALSE);
virtual int dump_param(char *buf, int buflen, bx_bool dquotes = false);
};
// a bx_shadow_num_c is like a bx_param_num_c except that it doesn't
@ -328,7 +328,7 @@ public:
#endif
virtual int parse_param(const char *value);
virtual void dump_param(FILE *fp);
virtual int dump_param(char *buf, int buflen, bx_bool dquotes = BX_FALSE);
virtual int dump_param(char *buf, int buflen, bx_bool dquotes = false);
};
// a bx_shadow_bool_c is a shadow param based on bx_param_bool_c.
@ -379,7 +379,7 @@ public:
#endif
virtual int parse_param(const char *value);
virtual void dump_param(FILE *fp);
virtual int dump_param(char *buf, int buflen, bx_bool dquotes = BX_FALSE);
virtual int dump_param(char *buf, int buflen, bx_bool dquotes = false);
};
typedef const char* (*param_string_event_handler)(class bx_param_string_c *,
@ -426,7 +426,7 @@ public:
#endif
virtual int parse_param(const char *value);
virtual void dump_param(FILE *fp);
virtual int dump_param(char *buf, int buflen, bx_bool dquotes = BX_FALSE);
virtual int dump_param(char *buf, int buflen, bx_bool dquotes = false);
};
class BOCHSAPI bx_param_bytestring_c : public bx_param_string_c {
@ -456,7 +456,7 @@ public:
#endif
virtual int parse_param(const char *value);
virtual int dump_param(char *buf, int buflen, bx_bool dquotes = BX_FALSE);
virtual int dump_param(char *buf, int buflen, bx_bool dquotes = false);
};
// Declare a filename class. It is identical to a string, except that