AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come
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@ -1925,6 +1925,8 @@ public: // for now...
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BX_SMF void LOAD_Oct_Vector(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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#endif
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#if BX_SUPPORT_EVEX
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BX_SMF void LOAD_MASK_Wss(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOAD_MASK_Wsd(bxInstruction_c *i) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOAD_MASK_VectorB(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOAD_MASK_VectorW(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOAD_BROADCAST_VectorD(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -89,6 +89,21 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wss(bxInstruction_c *i)
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#endif
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}
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#if BX_SUPPORT_EVEX
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_MASK_Wss(bxInstruction_c *i)
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{
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Bit32u val_32 = 0;
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if (BX_SCALAR_ELEMENT_MASK(i->opmask())) {
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
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val_32 = read_virtual_dword(i->seg(), eaddr);
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}
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BX_WRITE_XMM_REG_LO_DWORD(BX_VECTOR_TMP_REGISTER, val_32);
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BX_CPU_CALL_METHOD(i->execute2(), (i));
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}
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#endif
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wsd(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL >= 6
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@ -100,6 +115,21 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wsd(bxInstruction_c *i)
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#endif
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}
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#if BX_SUPPORT_EVEX
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_MASK_Wsd(bxInstruction_c *i)
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{
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Bit64u val_64 = 0;
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if (BX_SCALAR_ELEMENT_MASK(i->opmask())) {
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bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
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val_64 = read_virtual_qword(i->seg(), eaddr);
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}
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BX_WRITE_XMM_REG_LO_DWORD(BX_VECTOR_TMP_REGISTER, val_64);
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BX_CPU_CALL_METHOD(i->execute2(), (i));
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}
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#endif
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wdq(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL >= 6
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