on 64 bit register that's not correctly signed extended. The R4x00 support
works again on DECstations. A similar change to the XTLBMiss handler probably
needs to be made, but I have not done that since I am unable to test any
changes to that.
Also re-order a couple of instructions to allow for delay with mfc0.
- Fix an error in mips3_cpu_switch_resume(); ASID was not set correctly.
- Remove global variable 'curpcb' reference in mips1_proc_trampoline().
- Restore 'cpuregs.h'.
* Add the correct version of locore_mips1.S [ See previous revision for
description of changes ]
* Use defopt'ed MIPS3_L2CACHE_ABSENT in mips_machdep.c and pmap.c
to avoid generating extraneous code.
* GC pmap_set_referenced in pmap.c
minor of libc and the major of libutil). For little-endian architectures
merge the bnswap() assembly versions with nto* and hton* using symbols
aliasing. Use symbol renaming for the bswap function in this case to avoid
namespace pollution.
Declare bswap* in machine/bswap.h, not machine/endian.h. For little-endian
machines, common code for inline macros go in machine/byte_swap.h
Sync libkern with libc.
Adjust #include in kernel sources for machine/bswap.h.
Affected files:
include/mips_param.h, include/pcb.h,
mips/locore_mips1.S, mips/locore_mips3.S,
mips/mips_machdep.c, mips/vm_machdep.c
Issue:
So far, NetBSD/mips has not successfully got rid of fixed-address
kernel stack. USPACE (two 4KB pages) of each process has two distinct
KSEG2 addresses, both refer to a single physical storage; one address
for fixed range [ UADDR .. KERNELSTACK ), and another for "normal" KSEG2
address which was allocated by kernel memory manager and unique to each
others of processes.
"Doubly mapped" USPACE complicates context switch. Both address ranges
have to be managed with a special care of "wired" TLB entries which
are never replaced until next context switch to ensure no TLB miss for
USPACE access. It's equally crumbersome that MIPS processor's cache
machinary gets be confused about USPACE contents because there are two
distinct KSEG2 addresses to manipulate one physical storage.
Solution:
Purge KERNELSTACK constant for kernel stack pointer and replace
it with process unique values. Kernel stack bottom is located at
'curproc->p_addr + USPACE'. Context switch is simplified as it unloads
half of TLB hardwiring burden. It just manages the unique KSEG2 address
of each USPACE to be wired. As the side effect, switch_exit() has no
MIPS processor ISA dependent code anymore. It switchs kernel stack to
proc0's USPACE which has KSEG0 address and no need of TLB entry.
* Extensive use of 'genassym.cf'
To hide target port dependent and/or processor register size dependent
constants from assembler routines, 'genassym.cf' now has an extentive
set of definitions for various constants and offset values of
structural objects. This change will contribute possible NetBSD/mips64
portability too.
* Separation and rename of locore_r2000/_r4000.S
Those files are now indepedent standalones from locore.S to ease
maintainance works, and renamed to match MIPS processor ISA version.
* Changes in kernel mode exception handlers
Kernel mode exception handlers hold exception contexts by pushing a
certain set of register values on stack for resuming kernel mode
processing. This context is now represented with 'struct trapframe',
which is smaller than full scale (user mode) exception context 'struct
frame'. Stack consumption of kernel mode exception services is now
similar to 4.4BSD/mips.
* Relocation of exception frame
User mode context 'struct frame' is moved to the very bottom of kernel
stack at 'curproc->p_addr + USPACE - sizeof(struct frame)' This change
saves a bit of instructions on every return to user processes as it
eliminates reference to global variable 'curpcb' each time.
* Refurblished DDB backtrace routine
It's a growing concern to maintain stacktrace() code correctly. It
could be simplified by enforcing special arrangements for some of
obscure locore routines which violate usual coding conventions.
New backtrace code searchs for certain instructions peculiar to any of
function tails. Specifically, "jr ra" for normal function returns, "jr
k0" for MIPS1 exception handlers and "eret" for MIPS3 handlers.
* Support for 64-bit safe user code
Affected Files:
${ARCH}/include/pubassym.cf lib/libc/arch/mips/gen/*setjmp*
include/setjmp.h mips/include/[lots] mips/mips/[lots]
Solution:
We define macros REG_L/REG_S and SZREG for loading and storing
registers and for the size of registers. The exact meaning
of these is controlled by a macro (currently _MIPS64) which
allows one to treat the registers as either 32-bit or 64-bit.
There are data types mips_reg_t and mips_fpreg_t which represent
the true register sizes, and avoid confusing register_t.
We needed a way to dynamically gen the structure sizes of things
like sigcontext for setjmp.h, so we defined a pubassym.cf for
libc routines like setjmp and longjmp.
NetBSD/mips allows ${ARCH}'s to be defined which preserve
all 64-bits of registers across user context switches. There
are still a few niceties to clean up for kernel mode context
switches.
* Support for QED 52xx processors
Affected Files:
mips/locore_mips3.S mips/pmap.c include/locore.h
Issue:
The QED 52xx family of processors are targeted at low cost
embedded systems, (i.e. CPUs ~$30) for systems like routers, printers,
etc. We have added preliminary support for some of the idiosyncrasies
of this processor, e.g. no L2 cache, etc. More work needs to be
done here because with a modest 2-way L1 cache, some of the rampant
flushing has significant performance implications. However,
it doesn't crash, which is a start.
Solution:
A routine for flushing the cache based on virtual addresses was added;
a routine which deals with the two-way set associativity of the
5230 L1 cache was added, accomodations to 5230's instruction hazards
were added.
* TLB Miss code for mips3/mips4 processors cleaned up significantly.
Affected Files:
mips/locore_mips3.S mips/vm_machdep.c include/locore.h mips_machdep.c
Issue:
The TLB Miss handler exceeded the allowed size, which wasn't
a problem because there was no handler for when the processor
was in 64-bit mode. The handler for invalid TLB exceptions
also appears to have much vestigial code, which made it
difficult to understand.
Solution:
Use the XCONTEXT register to store a pointer to the segment
map table, this coupled with removing some dead code allows
the handlers to fit.
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.
* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.
* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.
* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
- Don't make a reference of curproc when it has NULL value. It causes
double fault upon a fatal panic ocation.
- Macro FETCH_INSTRUCTION() took a value of address 0.
-
UVM relies on pmap modules keeping track of modified/referenced bits
after a page has been removed from all mappings. So *dont* clear
PV_REFERENCED or PV_MODIFIED flags in pmap_remove().
either OP_JR function code or *OP_JALR* function code (not OP_JAL opcode).
insn_unconditional_flow_transfer() was to read an unintialized variable.
Those MD DDB routines seems not useful work so far.
- returned EOPNOTSUPP rather than -1.
- no check for negative offset.
many of these fix potential security problems in these drivers.
XXX XXX XXX
the d_mmap cdev routine should be changed to have a prototype like:
paddr_t (*d_mmap) __P((dev_t, off_t, int));
by someone!
Track page modification status in the PV entry like the alpha, and let
pmap_is_modified() return current status back to the VM system. UVM now
works reliably.
Garbage collect the old pmap_attribute[] stuff.
- cpu_set_kpc() now takes void *arg third argument, passed to the
entry point.
- cpu_fork() allows parent to be non-curproc iff parent is proc0.
When forking non-curproc, assume its state has already been saved.
- Adjust various pieces of machine-dependent code to account of all of this.
* commit isapnpvar.h changes required for ARC to support plain isa.
* fixup mistake over mips/include/cpuregs.h.
* mips/mips_machdep.c:
set L2 cache-size for arc, cleanup use of L2cache present
vs L2 cache-size variables. check for no L2 cache on kernels
configured to require one. misc cleanups.
* mips/mpis/trap.c: more locore stack-traceback label cleanup.
XXX Locore callbacks for mips3, mips4, r4600 cacheflush need more work.
Adds (most) support for ARC platform to port-independent mips code.
Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.
Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.
* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.
u-area in machine-dependent code. Instead, call exit2() to schedule
the reaper to free them for us, once it is safe to do so (i.e. we are
no longer running on the dead proc's vmspace and stack).
- bump cpu_model[] length as the longest name occupies over 30 characters.
- place machine_arch[] beside machine[] for clearity.
- nuke useless #include directives.
- small scale cleanup in vm_machdep.c
address on 2 architectures anyhow. Also, move the definition of the `label_t'
type inside _KERNEL protection, since it is specific to the in-kernel
setjmp()/longjmp() implementations.
as with user-land programs, include files are installed by each directory
in the tree that has includes to install. (This allows more flexibility
as to what gets installed, makes 'partial installs' easier, and gives us
more options as to which machines' includes get installed at any given
time.) The old SYS_INCLUDES={symlinks,copies} behaviours are _both_
still supported, though at least one bug in the 'symlinks' case is
fixed by this change. Include files can't be build before installation,
so directories that have includes as targets (e.g. dev/pci) have to move
those targets into a different Makefile.
there is one. The Mach VM system seems to take care of this, so it
hasn't knowingly caused a problem. UVM does change mappings without
removing the current mapping, and will pmap_page_protect() hangs
if pmap_enter() doesn't remove the previous mapping.
prototype declearation for method to override wbflush() callback
vector with model-specific code. Used on DEC r2000a machines with
writebuffers which indicate writebuffer drain via cp0 usability bit.
read and write compare register (controls cycle-driven periodic interrupt).
Use cycle counter for microsecond time on mips3, but for now only on
3min motherboards (5000/150). the MAXINE baseboard microsecond
counter is more stable and I don't ave no 5000/260 to test.
XXX clkread() is a mess, it should be rewritten.
XXX should add nanotime() to give inkernel nanosecond resolution,
and then microtime() reworked to use nanotime().
interrupt-callout vector from mips locore dispatch code to port code.
* Move branch-emulation declaration to mips/include/trap.h.
* Garbage-collect pmax/pmax/trap.h.
Not needed now pmax/pmax_trap.c is gone, and after above tidy-up.
common place:
- allocsys(), which computes space for and assigns addresses
to kernel data structures at boot time.
- mips_init_msgbuf(), which initializes the error message
buffer at the end of core.
- mips_init_proc0(), which initializes the U-area for proc0
and nullproc.
didn't make it in. Aproved by Jonathan and tested here at Stanford.
While I'm here, add conditional prototypes for clnlintr() and nsintr()
so that NS and ISO will compile correctly.
to the TLB dump routines arguements. Machines would die horibbly when
trying to dump the TLB entries in DDB. Also don't explicitly "page" the
output, since db_printf takes care of that.
if the break instruction is still there. This works around a problem with
the software single step in DDB not recognizing the temporary breakpoint
set to emulate the single step.
- fix _C_LABEL so that it actually works.
- make __RENAME use _C_LABEL.
- fix __RENAME so that it expects an unquoted argument.
- fix __indr_reference and __warn_references so that they
supply their own final semicolon.
- define __warn_references to nothing if not GNU C (required
by the way it's used).
The __warn_references semicolon change has to be made
so that __warn_references can be defined into nothing.
(A ; all by itself isn't a great idea.) The __indr_reference
change was made for consistency.
From /sys/news3400/news3400/locore.s, with id
@(#)locore.s 8.3 (Berkeley) 9/23/93
Kazumasa Utashiro notes that the pmax cacheflush routines don't work:
#ifndef NOTDEF /* I don't know why Ralph's code doesn't work. KU:XXX */
It's because pmax hardware wries the COP0 bit to external branch
logic. news3400s don't, and so the bc0f loop fails. It will also
fail on some other models of pmax, but we dont' support them.
Surround the relevant framgents in locore_r200.S with "#ifdef pmax".
Longer-term, the cacheflush entry in the locore callback may have
to be a CPU baseboard-specific entry, not just CPU-version specific.
(_BYTE_ORDER, _BIG_ENDIAN, _LITTLE_ENDIAN).
Define old names from the ANSI ones if not _POSIX_SOURCE.
* Define _QUAD_HIGHWORD and _QUAD_LOWWORD properly when
_BYTE_ORDER == _BIG_ENDIAN.
Only assembly version for i386 bswap16 and bswap32 for now (bswap64 uses
bswap32). Contribution of assembly versions of these are welcome.
Add byte-swapping of ext2fs metadata for big-endian systems.
Tested on i386 and sparc.
msgbuf. Note that old 'dmesg' and 'syslogd' binaries will continue running,
though old 'dmesg' binaries will output a few bytes of junk at the start of
the buffer, and will miss a few bytes at the end of the buffer.
Compute CPU speed(MHz) and loop multiplier for DELAY() based on
counting empty loop between mcclock ticks. New global: cpu_mhz.
Change pmax/pmax/machdep.c to build baseboard model names from cpu_mhz.
Set 'cpuspeed' for more realistic DELAY() on mips3 models.
Mips CPU constants, testing, and calibration from D. Sean Davidson
<davidson@zk3.dec.com> and Simon Burge <simonb@telstra.com.au>.
* prototype and definition for pmap_activate(p). Updates the segtab,
and changes the active ASID if p == curproc.
* Make reserved fixed-address (UADDR) kernelstack PTEs global,
so we still have a kernel stack after pmap_activate() on curproc.
* make KSEG2 mappings for p_addr global (see above.)
Seems to detune contextswitch and NTP resolution (by 60 ms), but
thepmap_activate() interface is mandatory. Needs more thought.
of cache-index incompatible virtual mappings for a physical page may be
required for hardware without secondary (level 2) cache to detect and
correct virtual coherency problems. I'm not sure this is really needed
anymore, since pmap_prefer() took care of of the cache-index
incompatible mappings that I have seen. Count the times a page is
cache inhibited in enter_stats if DEBUG.
Wait for memory instead of panic() on failure to allocate a page for the
segtab or segmap [from OpenBSD arc port]. Also check for malloc()
failure on allocation of a new pv entry and panic().
Increment resident_count when adding a new page to a pmap [also from
OpenBSD]. Process resident size is now valid.
cache flush operations required on a virtually-indexed, physically-tagged
mips3 with no L2 cache to provide cache-coherence exceptions.
(Similar to what's needed with a virtually-indexed, virtually-tagged cache.)
faults. Use curpcb, which always points to the current pcb. If curproc
was NULL when the kernel faulted, the trap handling would fault recursively
and the kernel stack would overflow.
Has unrolled loop for aligned-to-aligned copy.
Notes:
1. this code tuned for DEC 5000/200. ioasic decstations do more unaligned
copies. Better than old non-unrolled loop, but could be improved.
2. Undoes changes made for MIPS3 with comment implying an r4000 TLB bug.
We can't reproduce this on 5000/150 (jonathan) or 5000/50 (mhitch).
Calls to previous bcopy with a bad address show similar symptoms,
reporting a trap in bcopy() after bcopy() has returned. Same thing??
Needs re-checking on an r4000 with no L2 cache.
sigcode():
executed from user-space stack.
mips1_cpu_switch_resume, mips3_cpu_switch_resume:
arguments passed in via v0, t0, t1 (outlined from cpu_switch())
mips3_VCED(), mips3_VCEI():
called from exception-vector code without any register save,
$at, $ra are live.
undone by rev 1.7:
>redo pmax/include/reg.h
>so that the definitions needed by locore.S are in a separate file,
>pmax/include/regnum.h.
* Add explicit `#include <mips/regnum.h>' where symbolic offsets
into a mips trapframe or struct reg are used..
Add DDB interface to /sys/arch/mips/mips..
Rework heuristic stack traceback to work with DDB.
Add hooks to print exception log from DDB.
Add hooks from pmax console drivers: call Debugger()
after break from serial console, or 'DO' key from LK-xxx.
ktlbmiss on the kernel stack. It was showing the temporary SP, not the
original SP.
Add a display of the first few wired entries of the TLB so when the ktblmiss
occurs, the TLB entries mapping the kernel stack can be verified.
* cpuregs.h:
rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx.
Add compile-time MIPS3-only, compile-time MIPS1-only, and
runtime (both) definitions for number of TLB ASIDs (tlb pids)
and shift count to extract a TLB pid.
* locore.h:
Delete unused vector slot for indexed TLB writes.
mips1 and mips3 TLBs are different enough that we have
to break them out at the caller anyway.
* Add compile-time MIPS3-only andcompile-time MIPS1-only
macros to call locore functions directly by name.
Use the existing method table only if
* mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c:
Use MIPS3_ or MIPS1_ specific names for TLB pids in
mips3 and mips1 specific code paths (e.g., creating the kernel stack
for process 0).
Add `options MIPS3' to pmax/conf/GENERIC.
Remove unused debug procedure I forgot to remove previously.
Consolidate the vm_page_free1() calls in pmap_release(). Duplicate code
was a result of the way I merged the MIPS3 support from the pica pmap.c.
Enhance the comment on flushing the cache when releasing the segmap pages,
and add a comment about the currently unused code to uncache pages in
pmap_enter_pv().
unsigned cause register wouldn't have worked.
Add missing ')' in trapdump that shows up when compiled with DEBUG.
Fix (unfix?) previous change to printf formats in mips3_dump_tlb: vad_to_pfn
is now consistant with single-CPU and merged-CPU support.
* cpuregs.h:
Delete unused VMMACH_ names (e.g., duplicates of PTE bits in pte.h).
Change remaining VMMACH_xxx names to MIPS1_xxx or MIPS3_xx.
Fold remaining compile-time definitions into a single #ifdef MIPS3.
* Use MIPS1_ names in locore_r2000.S, mips3_ names in locore_r4000.S
* Garbage-collect MachHitFlushDCache()
* psl.h:
use MIPS1_, MIPS3_ symbolic names for Cause register bits.
change _R3K to MIPS1_, _R4K to MIPS3. Conditionalize for mips1 only,
mips3 only, or when both are defined, use runtime CPUISMIPS3 test.
Remove cpu-specific routines from locore.S and add them to locore_r2000.S
and locore_r4000.S. Add entries in locore jump vector table for switch_exit()
and the cpu_switch() context resume.
Add offsets into the jump vector to genassym.cf for use in locore.S.
Remove cpu-specific routines from locore.S and add them to locore_r2000.S
and locore_r4000.S. Add entries in locore jump vector table for switch_exit()
and the cpu_switch() context resume.
Add offsets into the jump vector to genassym.cf for use in locore.S.
Use same cachesize variables for mips1 and mips3, and rename the variables
per Jonathan's request.
the stack frame when usermode interrupt occurs. The interrupt may have
modified the PC [such as sendsig()]. This got dropped with the stackframe
changes.
Remove old code now that the new version is working.
Correct typo for 16K cache (R4400).
Align the saved AT register location; seems to hang if not aligned on 8
byte boundry.
similar design and code by Jason Thorpe and Jonathan Stone.
NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.
mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.
mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.
mips/include/mips1_pte.h:
mips1 TLB bit definitions.
mips/include/mips3_pte.h:
mips3 TLB bit definitions.
mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.
mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.
mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.
mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)
mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.
mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().
pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.
Move mips-specific pmap definitions (PMAP_PREFER for mips3, declaratin
of pmap_bootstrap() for the system-specific machdep.c) from
arch/pmax/include/pmap.h to arch/mips/include/pmap.h.
* Move declaration of locore communcation variables (CPU family,
cache sizes, etc) to mips/include/locore.h. Delete from
pmax/include/cpu.h and older versions from pica/include/cpu.h.
* Move definitions of CLKF_BASEPRI, CLKF_USERMODE to mips/include/cpu.
* Delete duplicate definitions in pica/include/cpu.h, pmax/include/cpu.h.
Change pmax/include/psl.h to just do #include <mips/psl.h>.
pmax/include/psl.h would go away completely if it wasn't stil required
by compat/common/kern_exit_43.c.
processing from generic trap processing, _FORKBRAINDAMAGE is gone -
user process entered through proc_trampoline(), mini-debugger from pica
port.
More merged MIPS1/MIPS3 support for DECstations.
proc_trampoline(); move away from UADDR access to user structure.
From Toru Nishimura: exception trapframe changes, mini-debugger from pica
port, separate out syscall exception.
DECstation MIPS3 support: wbflush() is cpu-dependent, MIPS3 level 2 cache
support.
interrupt-enable bit in the status register, and all lower bits.
Can be used for spl{bio,net,tty,clock,statclock} on machines where
devices are wried to mips hard-interrupt levels in ascending bit order
so as to match the BSD spl.9 ordering.
Some of the stuff (e.g., rarpd, bootpd, dhcpd etc., libsa) still will
only support Ethernet. Tcpdump itself should be ok, but libpcap needs
lot of work.
For the detailed change history, look at the commit log entries for
the is-newarp branch.
Fixes profiling for non-underscore-prepending toolchains
(elf, e.g., shared libs), and breaks a.out/ecoff toolchains.
May break mips kernel profiling too. Needs more thought, since the
original intent of __mcount vs ___mcount on mips date back to pre-1.0 days.
* handle interpreters with nonzero virtual address of entry-point:
subtract p_vaddr from computed entrypoint, as the mips elf exec did.
* Add #ifdef ELF_INTERP_NON_RELOCATABLE/#endif around the code
that tries to choose a `good' address at which to load an interpreter,
if none was set by the emul probe function.
(the address chosen could be improved to avoid fragmenting the
process virtual address space).
* define ELF_INTERP_NON_RELOCATABLE in machine/elf_machdep.h for mips CPUs,
which currently use a GNU-derived ld.so.
ELF_INTERP_NON_RELOCATABLE is not necessary for native NetBSD/alpha ELF
binaries. It may be required for GNU-derived ELF dynamic loaders (Linux/i386?)
mips_r2000_, mips_R2000_ -> mips1_
mips_r4000_, mips_R4000_ -> mips3_
(which are also, for mnemonic reasons, consistent with gcc flag usage,
rather than using mipsI_ and mipsIII_).
* Move mips-I pte (TLBlo) definitions from pmax/include/pte.h
to mips/include/mips1_pte.h
* Move mips-III pte (TLBlo) definitions from pica/include/pte.h
to mips/include/mips3_pte.h
* Add new mips/include/pte.h, which includes exactly one of
mips1_pte.h or mips3_pte.h (which still have namespace collisions),
depending on "options MIPS1" or "options MIPS3". (hack).
Move soft kvtopte(), ptetovk() definitions to mips/include/pte.h
* Add macro PTE_TO_PADDR() to hide the different hardware TLB formats
when mapping from pte to physical address.
* Add macro PTE_READONLY() to hide lack of SW read-only bit in mips-III
tlb. (mips1 pmap uses a sw bit in the PTE, mips3 looks up RO bit in
the kernel pmap.)
* Use macros (not direct TLB frobbing) in mips/trap.c, to make it
mips-1/mips-III indepenndet.
* Change {pmax,pica}/include/pte.h to just do #include <mips/pte.h>.
jump-table) locore entrypoints, so the stack traceback code can use
the end marker to handle entry points specially when doing tracebacks,
even if it doesn't know about them explicitly.
add catch-all case, with distinct mips1 and mips3 ranges for locore
entry points, cases to catch othewise-unknown locore entrypoints and
vector code (which have special entry sequences and require special
support to trace through). The relevant mips1 and mips3 functions are
of course now distinct.
* Create arch/mips/Makefile.inc with source list of generic MIPS-cpu
files for tags
* Use mips/Makefile.inc and updated tag list in pmax/Makefile
* Try building bootblocks in arch/pmax/stand.
consistency with the way machdep headers for other things are done.
(the creation of the ecoff_machdep.h files was done on the CVS server, to
keep the RCS logs intact.)
macros to use to remove #ifdefs from the machine ID case check.
Eventually, these headers will contain other information, e.g.
machine-dependent relocation information, etc.
in the branch-emulation code was uninitialized, due to a misplaced #endif.
Remove the relevant #ifdef (macro version of GetBranchDest), and move the
XXX note about r4000 branch targets to the function definition.
definitions.
* Include <mips/cpuregs.h> in <cpu.h> so kern_clock.c has user/kernel
status bits in scope. Still needs work; r2k/r4k previous-mode bits
are different.
* Include <mips/mips_param.h> in pica/include/param.h, for locore declarations,
and definitions of vm and other constants that should be shared across
NetBSD/mips systems to esnsure user-level binary compatibility.
which was taken from OpenBSD/pica.
The previous revision of elf.c replaced Ted Lemon's elf exec machinery
with something closer to Christos' MI elf machinery. It turns out
that old NetBSD/pmax elf binaries have three segments, and the newer
elf exec machinery cannot exec them.
The old elf exec machinery is folded back into cpu_exec.c, which falls
back onto using the old machinery if the new machinery fails. The
old-style binaries will be deprecated at the 1.2 release.
* Update arch/mips/mips/cpu_exec.c to include MI exec_elf.h header,
and to use the MI interface exec_elf_makecmds().
* Replace arch/mips/mips/elf.c (Ted Lemon's elf code) with
a version of Christos's MI elf exec code, munged to support demand paging
and mips shared libraries.
it into three pieces:
* locore.S, which contains generic mips locore code,
applicable for both r2000/r3000 and r4000s (in 32-bit mode).
* locore_r2000.S, which contains r2000/r3000 (MIPS-I) versions
of the locore functions that need mips-generation-specific
instructions or handling.
* locore_r4000.S, which contains r4000/r4400/r4600 (MIPS-III?) versions
of the locore functions that need mips-generation-specific
instructions or handling.
Much of the code in locore_r4000.S is derived from Per Fogelstrom's Pica port.
locore.S still contains some pmax-specific DMA-buffer copy functions.
to the mips tree.
* Add declarations of functions used by vm_machdep.c.
* Add declarations of functions printed by name in stack tracebacks.
* Add declarations of functions used by the model-independnet mips machdep.c
code.
symbolic lookup of the CPU-level specific locore entry points to use the
r2k, not the r4k, labels.
Include header files to get prototyped declarations of ipintr() and arpintr().
Remove unused variables and parenthesize assignments in if () expressions.
Gcc warns of a possible && vs || operator-precedence bug in the network
softint dispatch code, which needs more thought.
locore calls to go via a locore-entry jumptable.
Cast the (int) arguments to MachTLBUpdateEntry() to avoid
warnings. Variables TLB entries are still type-punned as either structs
or ints, without any regard, when the pmax-specific VM code passes
them as arguments to functions.
locore calls to go via a locore-entry jumptable.
Use mips_btop(), mips_round_page, mips_trunc_seg() instead
of pmax_btop(), pmax_round_page, pmax_trunc_seg().
Add Per's software-readonly-bit mechanism, since the r2000 and r4000
hardware TLB entries are very different, and the r4k has no space for
software bits in TLB entries. That is, this pmap code still won't work
on r4000 machines. Some other solution, like another jump table for
clients of the pmap code, is necessary.
locore calls to go via a locore-entry jumptable.
Declare r2000- and r4000-specific exception-handler functions, to which
trap() and interrupt() dispatch exceptions. Initialize r2000- and r4000-
specific exception-handler vectors, when CPU_R4000 and CPU_R2000 are
defined.
Update the stack-traceback code (partially) to understand and print
the new low-level exception-handler code, via which machine exception-vectors
send exceptions to call trap() or interrupt(). This needs more work.
an vector (struct) of function pointers. Add prototype declarations for
each vector entry.
Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore
versions of the relevant functions.
to all mips ports.
So far, this consists of code to initialize a vector, or jump-table, of
pointers to locore functions that require different definitions on different
Mips CPUs (eg., r2000/3000 and r4000); a generic wrapper for setting up
CPU-specific exception vectors; and CPU and FPU identification code.
locore functions. The new names are used by C code to construct a jump-table,.
making it less infeasible to have a single kernel image work on both
r3000 and r4000 systems.
Add prototypes to (most of) src/sys/arch/pmax/pmax. (The un-protytyped
parts still have pending merges with the Pica port.)
Fix splx() glitches in pmax/clock.c.
Delete old cpu/fpu identification from pmax/autoconf.c, use r4400/r4600/idt
aware code from Pica port, now in mips/mips/mips_machdep.c.
Delete unused multi-CPU autoconfiguration code; NetBSD/pmax does not
support decsystem 5800s anyway.
Replace impliclty-sized types (u_long, u_short) used in
declarations of byteorder functions witho explicitly sized types
(u_int32_t, u_int16_t).
Avoids problems with using ntohl(foo) as (eg) an argument to printf().
Do not define __BDEVSW_DUMP_OLD_TYPE, as it breaks prototyping
of device dump functions, and should be port-dependent in any case.
The pmax 4.4bsd/pmax-derived drivers are being fixed, and the pica port
uses the MI scsi drivers already.
Move to mips/pmax/genassym.c, as (most of) the assembler locore code is
being merged into a generic-MIPS locore.
Remove the redundant pmax/pmax/genassym.c.
* cut-and-paste all the code for both r2000 (MIPS-I) and r4000 (MIPS-III)
into both the pica and pmax locore.S.
* Change the names of the small segments of vector code that are
bcopied to the machine vector locations, to avoid clashing.
Get rid of the Sprite MachXXX names for the vector code, and
use use mips_r2000_xxx and mips_r4000_xxx instead.
Update the names used in the vector-copying code and trap handlers
to match.
* Most of the rest of the pica locore.S was copied from the pmax
locore.S, and then edited to work on an r4000. The names of
functions and of manifest constants stayed the same, although
both assmbler code and constant values changed.
cut-and-paste such code into contiguous blocks protected by
#if / #endif. Much of the cache and trap-handling code
needs r3000-only register fields, on the r3000, and r4000-only
insns and registers on the r4000.
* change the pmax r2000 exception-handling code to extract a trap
code with the user/kernel bit at 0x20 rather than 0x10.
(r2000s have 4-bit execption codes, r4000s have 5-bit.)
Use the a 16 from-user-space + 16-from-kernel space jump table,
just like on the r4000 pica port.
* add NOPs to the common code where required by the r4000 pipeline
constraints.
* add _C_LABEL() macros to the r4000 locore.
Comitted to provide a snapshot for others to test, and work on a cleaner merge.
* add "MIPS_3k_" for the MIPS-I r[23]000-specific register definitions.
* add "MIPS_4k_" for the MIPS-II/III r4000-specific register definitions.
* add #defines that provide the old values for locore and user
code, so the existing code continues to compile.
Regression-tested against the old headers by grepping for #define's,
editing out the defined symbols, and preprocessing with both the previous
machConst.h headers and this version.
Some unused symbols (CPU and FPU must-be-zero constants) are no longer defined.
Pica interrupt masks are now constant expressions instead of constant
values.
TODO:
* factor out the common #defines into src/sys/arch/mips.
* Get rid of the Sprite coding-style names (MACH_xxx).
* Separate out the r3k/r4k differences from the Pica/pmax differences.
* Figure out how to have a run-time choice of r3k vs. r4k support,
instead of a compile-time choice.
* Delete pmax-specific functions and declarations from trap.c
* Delete mips-geeneric functions and declaratinos from pmax_trap.c
* Rename the function pointer used to handle hardware interrupts to
"mips_hardware_intr". Define it in trap.c. Change references elsewhere,
including machdep.c.
Verified to boot on a 5000/200.
* Add spl4() and spl5() functions from the Pica port.
* Add MachFPTrap() as an alternate entry point for MachFPInterrupt.
The r4k reports floating-point execptions as a trap, not an interrupt,
and the Pica port uses the name MachFPTrap().
* Add nops to the Mach_spl?() functions and MachFPInterrupt, as required
for the r4k port.
Commit "floppy" interrupt counter for vmstat -i.
always be eight digits.
Copy the kn02 memory-interrupt reporting function to the kn03 (5k/240)
memory-error handler, since the 3MAXPLUS seems to use the same ECC hardware
as the 3MAX.
Update the include-idempotency preprocessor token to match.
References to machAsmDefs in vendor (sprite, 4.4bsd) headers left unchanged,
for historical accuracy.
provide r3k and r4k versions of each, and move to sys/arch/mips/include.
Note in comments where each mips-based port should provide
definitions in its own cpu.h after including this file.
opcodes from the Pica port. Per Fogelstrom claims the latter are all
supposedly MIPS-II (r6000) instructions, rather than MIPS-III (R4000),
but we haven't checked to be sure. Are LL/SC really in MIPS-II?
CVS:: ----------------------------------------------------------------------
versions work correctly; at some point between then and the immediately
preceding revisions, the "stylistic" changes to one (or both) stdarg.h
and varargs.h broke passing doubles to printf().
parameter parameters shadowing locals. Replace vmapbuf() and vunmapbuf()
with the Alpha-port versions, which are cleaner (use round_page(),
trunc_page(), etc.)
* add a new enum decstation_intr_t to trap.c, naming each instrumented
interrupt symbolically, and used to index into intrcnt[]. Change the
model-specific interrupt handlers to use the decstation_intr_t when
updating interrupt counters.
* add instrumentation to the kmin and maxine interrupt handlers.
* fix a bug that counted each hardclock interrupts on the kn02 twice.
The hardcoded mapping from locore names to units is gross; but these
counters will hopefully be useful in identifying interrupt hot-spots
and PPP problems on the 3MIN.
Rename the ioctl asic register and slot macros from ASIC_<xxx> to
IOASIC_<xxx>, to be compatible with the machine-indpendent names in
sys/dev/tc/ioasicvar.h. The pmax code still uses
sys/arch/pmax/pmax/asic.h, as some of the registers and offsets
defined there are not yet defined in sys/dev/tc/ioasicvar.h.
Rename the ioctl asic base-address pointer from `asic_base' to `ioasic_base'.
independent TC support in sys/dev/tc/tc.c and sys/dev/tc/tcvar.h:
* Change the tc autoconfiguration tables to use a struct tc_attach_args
instead of the ad-hoc structure.
* Change all pmax device drivers to use a `struct confargs' that's
assignment-compatible with sys/dev/tc/tcvar.h `struct tcdev_attach_args'.
Devices that can be present on a TC or as ioctl asic/mainbus builtins
use the same `struct confargs'.
* Eliminate the `BUS_CVTADDR()' macros which the pmax port inherited from
an old, now-obsolete sys/arch/alpha snapshot.
* Update the comments and debugging code in interrupt handlers to
be consistent with the machine-independent TC support.
Other commits that overlap the same source files include: re-enabling
clock-tick interrupts earlier, and counting hardclock ticks for vmstat -i.
Kernel-debugger breakpoints in user space, or FP insns that cause
underflow in a delay slot, should now work properly. Single-stepping
of arbitrary user processes, from user level, should be added.
* define PT_GETREGS and PT_SETREGS in pmax/include/ptrace.h
* Flesh out the stubs in pmax/pmax/process_machdep.c to handle
those requests.
* Now that "struct reg" is actually used, remove the bogus
#ifdef LANGUAGE_C around its definition, and redo pmax/include/reg.h
so that the definitions needed by locore.S are in a separate file,
pmax/include/regnum.h.
* update locore.S to match.
to "kn01_<func>", to avoid confounding a model name (PMAX) with the name of the
entire port (pmax).
Change the signature of interrupt-handlers to take a void *
(a pointer to the softc) and return an int (indicating spurious
interrupts or other conditions.)
Pass softc pointers to the scsi and ethernet kn01 (DS_PMAX) drivers,
rather than having unit numbers wired into the base-level interrupt
handler.
consistent with the (default) prepending of underscores to identifiers.
Because this reference is inside an ASM string it's too hairy to
conditionalize to support different toolchains that don't prepend underscores.
(Just don't do profiling with such toolchains.)
Instead of being a no-op, kn03_intr_enable() sets the sw copy of the
interrupt-enable mask *and* writes it into the IO asic intr-enable
register. Boot code sets the sw copy (kn03_tc_imask) to something
sane (KN03_IM0, with tc option slots turned off). Tested and works.
Interrupt code for other IOASIC machines should be redone so that
interrupts for devices are enabled by drivers, rather than by
cpu-specific boot code. Functions common to all IOASIC machines
(PSWARN?) should be done by asic_init().
Checked in without the above changes so that 3MAX+, MAXINE and 3MIN
interrupt-(enable,handle) can converge.
castor