* Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate choosing these on a port by port basis. * Create <machine/pubassym.h> mechanism to allow jmp_buf structure size to be calculated at system build time. * Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae for the architecture. For 64-bit oriented systems set the Status Register to allow 64-bit instructions. * Remove UADDR related macros because kernel U structure is now mapped normally. * Separate cpu.h into cpu.h and cpuarch.h to keep things neat. * Add support for QED 52xx processors
This commit is contained in:
castor
parent
77b1ebc172
commit
a84ec5a3c1
@ -1,13 +1,13 @@
|
||||
# $NetBSD: Makefile,v 1.1 1998/06/12 23:22:39 cgd Exp $
|
||||
# $NetBSD: Makefile,v 1.2 1999/01/14 18:45:46 castor Exp $
|
||||
|
||||
KDIR= /sys/arch/mips/include
|
||||
INCSDIR= /usr/include/mips
|
||||
|
||||
INCS= ansi.h aout_machdep.h asm.h bsd-aout.h cachectl.h cdefs.h conf.h \
|
||||
cpu.h cpuregs.h db_machdep.h ecoff_machdep.h elf.h elf_machdep.h \
|
||||
cpu.h cpuarch.h db_machdep.h ecoff_machdep.h elf.h elf_machdep.h \
|
||||
endian.h float.h ieeefp.h intr.h kcore.h kdbparam.h limits.h locore.h \
|
||||
mips1_pte.h mips3_pte.h mips_opcode.h mips_param.h pcb.h pmap.h \
|
||||
proc.h profile.h psl.h pte.h ptrace.h reg.h regdef.h regnum.h reloc.h \
|
||||
proc.h profile.h psl.h pte.h ptrace.h reg.h regnum.h reloc.h \
|
||||
setjmp.h signal.h stdarg.h sysarch.h trap.h types.h varargs.h \
|
||||
vmparam.h
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: asm.h,v 1.14 1998/12/02 00:58:43 thorpej Exp $ */
|
||||
/* $NetBSD: asm.h,v 1.15 1999/01/14 18:45:46 castor Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
@ -64,13 +64,12 @@
|
||||
* Define -pg profile entry code.
|
||||
* XXX assume .set noreorder for kernel, .set reorder for user code.
|
||||
*/
|
||||
#define _KERN_MCOUNT \
|
||||
.set noat; \
|
||||
move $1,$31; \
|
||||
jal _mcount; \
|
||||
subu sp,sp,8; \
|
||||
.set at;
|
||||
|
||||
#define _KERN_MCOUNT \
|
||||
.set noat; \
|
||||
move $1,$31; \
|
||||
jal _mcount; \
|
||||
subu sp,sp,8; \
|
||||
.set at
|
||||
|
||||
#ifdef GPROF
|
||||
# if defined(_KERNEL) || defined(_LOCORE)
|
||||
@ -92,6 +91,13 @@
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef USE_AENT
|
||||
#define AENT(x) \
|
||||
.aent x, 0
|
||||
#else
|
||||
#define AENT(x)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* WARN_REFERENCES: create a warning if the specified symbol is referenced
|
||||
* (ELF only, and thus, no leading underscores).
|
||||
@ -107,97 +113,174 @@
|
||||
#endif /* __ELF__ */
|
||||
|
||||
/*
|
||||
* LEAF(x)
|
||||
*
|
||||
* Declare a leaf routine.
|
||||
* LEAF
|
||||
* A leaf routine does
|
||||
* - call no other function,
|
||||
* - never use any register that callee-saved (S0-S8), and
|
||||
* - not use any local stack storage.
|
||||
*/
|
||||
#define LEAF(x) \
|
||||
.globl _C_LABEL(x); \
|
||||
.ent _C_LABEL(x), 0; \
|
||||
_C_LABEL(x): ; \
|
||||
.frame sp, 0, ra; \
|
||||
#define LEAF(x) \
|
||||
.globl _C_LABEL(x); \
|
||||
.ent _C_LABEL(x), 0; \
|
||||
_C_LABEL(x): ; \
|
||||
.frame sp, 0, ra; \
|
||||
MCOUNT
|
||||
|
||||
/*
|
||||
* NLEAF(x)
|
||||
*
|
||||
* Declare a non-profiled leaf routine.
|
||||
* LEAF_NOPROFILE
|
||||
* No profilable leaf routine.
|
||||
*/
|
||||
#define NLEAF(x) \
|
||||
.globl _C_LABEL(x); \
|
||||
.ent _C_LABEL(x), 0; \
|
||||
_C_LABEL(x): ; \
|
||||
.frame sp, 0, ra
|
||||
#define LEAF_NOPROFILE(x) \
|
||||
.globl _C_LABEL(x); \
|
||||
.ent _C_LABEL(x), 0; \
|
||||
_C_LABEL(x): ; \
|
||||
.frame sp, 0, ra
|
||||
|
||||
/*
|
||||
* ALEAF -- declare alternate entry to a leaf routine.
|
||||
* XLEAF
|
||||
* declare alternate entry to leaf routine
|
||||
*/
|
||||
#ifdef USE_AENT
|
||||
#define AENT(x) \
|
||||
.aent x, 0
|
||||
#else
|
||||
#define AENT(x)
|
||||
#endif
|
||||
#define ALEAF(x) \
|
||||
.globl _C_LABEL(x); \
|
||||
AENT (_C_LABEL(x)) \
|
||||
#define XLEAF(x) \
|
||||
.globl _C_LABEL(x); \
|
||||
.aent _C_LABEL(x),0; \
|
||||
_C_LABEL(x):
|
||||
|
||||
/*
|
||||
* NON_LEAF(x)
|
||||
*
|
||||
* Declare a non-leaf routine (a routine that makes other C calls).
|
||||
* NESTED
|
||||
* A function calls other functions and needs
|
||||
* therefore stack space to save/restore registers.
|
||||
*/
|
||||
#define NON_LEAF(x, fsize, retpc) \
|
||||
.globl _C_LABEL(x); \
|
||||
.ent _C_LABEL(x), 0; \
|
||||
_C_LABEL(x): ; \
|
||||
.frame sp, fsize, retpc; \
|
||||
#define NESTED(x, fsize, retpc) \
|
||||
.globl _C_LABEL(x); \
|
||||
.ent _C_LABEL(x), 0; \
|
||||
_C_LABEL(x): ; \
|
||||
.frame sp, fsize, retpc; \
|
||||
MCOUNT
|
||||
|
||||
/*
|
||||
* NNON_LEAF(x)
|
||||
*
|
||||
* Declare a non-profiled non-leaf routine
|
||||
* (a routine that makes other C calls).
|
||||
* NESTED_NOPROFILE(x)
|
||||
* No profilable nested routine.
|
||||
*/
|
||||
#define NNON_LEAF(x, fsize, retpc) \
|
||||
.globl _C_LABEL(x); \
|
||||
.ent _C_LABEL(x), 0; \
|
||||
_C_LABEL(x): ; \
|
||||
.frame sp, fsize, retpc
|
||||
#define NESTED_NOPROFILE(x, fsize, retpc) \
|
||||
.globl _C_LABEL(x); \
|
||||
.ent _C_LABEL(x), 0; \
|
||||
_C_LABEL(x): ; \
|
||||
.frame sp, fsize, retpc
|
||||
|
||||
/*
|
||||
* END(x)
|
||||
*
|
||||
* XNESTED
|
||||
* declare alternate entry point to nested routine.
|
||||
*/
|
||||
#define XNESTED(x) \
|
||||
.globl _C_LABEL(x); \
|
||||
.aent _C_LABEL(x),0; \
|
||||
_C_LABEL(x):
|
||||
|
||||
/*
|
||||
* END
|
||||
* Mark end of a procedure.
|
||||
*/
|
||||
#define END(x) \
|
||||
.end _C_LABEL(x)
|
||||
|
||||
#define STAND_FRAME_SIZE 24
|
||||
#define STAND_RA_OFFSET 20
|
||||
/*
|
||||
* IMPORT -- import external symbol
|
||||
*/
|
||||
#define IMPORT(sym, size) \
|
||||
.extern sym,size
|
||||
|
||||
/*
|
||||
* EXPORT -- export definition of symbol
|
||||
*/
|
||||
#define EXPORT(x) \
|
||||
.globl _C_LABEL(x); \
|
||||
_C_LABEL(x):
|
||||
|
||||
/*
|
||||
* ALIAS
|
||||
* Global alias for a function, or alternate entry point
|
||||
*/
|
||||
#define ALIAS(x) \
|
||||
.globl _C_LABEL(x); \
|
||||
_C_LABEL(x):
|
||||
|
||||
/*
|
||||
* Macros to panic and printf from assembly language.
|
||||
*/
|
||||
#define PANIC(msg) \
|
||||
la a0, 9f; \
|
||||
jal _C_LABEL(panic); \
|
||||
#define PANIC(msg) \
|
||||
la a0, 9f; \
|
||||
jal _C_LABEL(panic); \
|
||||
MSG(msg)
|
||||
|
||||
#define PRINTF(msg) \
|
||||
la a0, 9f; \
|
||||
jal _C_LABEL(printf); \
|
||||
#define PRINTF(msg) \
|
||||
la a0, 9f; \
|
||||
jal _C_LABEL(printf); \
|
||||
MSG(msg)
|
||||
|
||||
#define MSG(msg) \
|
||||
.rdata; \
|
||||
9: .asciiz msg; \
|
||||
#define MSG(msg) \
|
||||
.rdata; \
|
||||
9: .asciiz msg; \
|
||||
.text
|
||||
|
||||
#define ASMSTR(str) \
|
||||
.asciiz str; \
|
||||
#define ASMSTR(str) \
|
||||
.asciiz str; \
|
||||
.align 3
|
||||
|
||||
/*
|
||||
* XXX retain dialects XXX
|
||||
*/
|
||||
#define ALEAF(x) \
|
||||
.globl _C_LABEL(x); \
|
||||
AENT (_C_LABEL(x)) \
|
||||
_C_LABEL(x):
|
||||
|
||||
#define NLEAF(x) \
|
||||
.globl _C_LABEL(x); \
|
||||
.ent _C_LABEL(x), 0; \
|
||||
_C_LABEL(x): ; \
|
||||
.frame sp, 0, ra
|
||||
|
||||
#define NON_LEAF(x, fsize, retpc) \
|
||||
.globl _C_LABEL(x); \
|
||||
.ent _C_LABEL(x), 0; \
|
||||
_C_LABEL(x): ; \
|
||||
.frame sp, fsize, retpc; \
|
||||
MCOUNT
|
||||
|
||||
#define NNON_LEAF(x, fsize, retpc) \
|
||||
.globl _C_LABEL(x); \
|
||||
.ent _C_LABEL(x), 0; \
|
||||
_C_LABEL(x): ; \
|
||||
.frame sp, fsize, retpc
|
||||
|
||||
/*
|
||||
* While it would be nice to be compatible with the SGI
|
||||
* REG_L and REG_S macros, because they do not take parameters, it
|
||||
* is impossible to use them with the _MIPS_SIM_ABIX32 model.
|
||||
*
|
||||
* These macros hide the use of mips3 instructions from the
|
||||
* assembler to prevent the assembler from generating 64-bit style
|
||||
* ABI calls.
|
||||
*/
|
||||
|
||||
#if defined(_MIPS_BSD_SIM) && _MIPS_BSD_SIM_ != _MIPS_SIM_ABI32
|
||||
#define REG_L ld
|
||||
#define REG_S sd
|
||||
#define REG_LI dli
|
||||
#define REG_PROLOGUE .set push ; .set mips3
|
||||
#define REG_EPILOGUE .set pop
|
||||
#define SZREG 8
|
||||
#else
|
||||
#define REG_L lw
|
||||
#define REG_S sw
|
||||
#define REG_LI li
|
||||
#define REG_PROLOGUE .set push
|
||||
#define REG_EPILOGUE .set pop
|
||||
#define SZREG 4
|
||||
#endif /* _MIPS_BSD_SIM */
|
||||
|
||||
#ifndef _KERNEL
|
||||
#include <machine/pubassym.h>
|
||||
#endif
|
||||
|
||||
#endif /* _MIPS_ASM_H */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: cdefs.h,v 1.7 1997/11/04 23:09:58 thorpej Exp $ */
|
||||
/* $NetBSD: cdefs.h,v 1.8 1999/01/14 18:45:46 castor Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1995 Carnegie-Mellon University.
|
||||
@ -27,8 +27,14 @@
|
||||
* rights to redistribute these changes.
|
||||
*/
|
||||
|
||||
#ifndef _MACHINE_CDEFS_H_
|
||||
#define _MACHINE_CDEFS_H_
|
||||
#ifndef _MIPS_CDEFS_H_
|
||||
#define _MIPS_CDEFS_H_
|
||||
|
||||
/* MIPS Subprogram Interface Model */
|
||||
#define _MIPS_SIM_ABIX32 4 /* 64 bit safe, ILP32 o32 model */
|
||||
#define _MIPS_SIM_ABI64 3
|
||||
#define _MIPS_SIM_NABI32 2 /* 64bit safe, ILP32 n32 model */
|
||||
#define _MIPS_SIM_ABI32 1
|
||||
|
||||
#define _C_LABEL(x) x
|
||||
|
||||
@ -67,4 +73,4 @@
|
||||
|
||||
#endif /* _KERNEL */
|
||||
|
||||
#endif /* !_MACHINE_CDEFS_H_ */
|
||||
#endif /* !_MIPS_CDEFS_H_ */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: cpu.h,v 1.27 1998/11/11 06:41:27 thorpej Exp $ */
|
||||
/* $NetBSD: cpu.h,v 1.28 1999/01/14 18:45:46 castor Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1992, 1993
|
||||
@ -165,13 +165,19 @@ extern u_int32_t mips3_timer_delta;
|
||||
{ "console_device", CTLTYPE_STRUCT }, \
|
||||
}
|
||||
|
||||
#ifdef _KERNEL
|
||||
|
||||
/*
|
||||
* Misc prototypes.
|
||||
*/
|
||||
|
||||
struct user;
|
||||
struct proc;
|
||||
struct user;
|
||||
|
||||
/* trap.c */
|
||||
void child_return __P((void *));
|
||||
int kdbpeek __P((vaddr_t));
|
||||
|
||||
/* mips_machdep.c */
|
||||
caddr_t allocsys __P((caddr_t));
|
||||
void dumpsys __P((void));
|
||||
int savectx __P((struct user *));
|
||||
@ -179,70 +185,14 @@ void mips_init_msgbuf __P((void));
|
||||
void mips_init_proc0 __P((caddr_t));
|
||||
|
||||
/* locore.S */
|
||||
extern void savefpregs __P((struct proc *));
|
||||
void savefpregs __P((struct proc *));
|
||||
void switchfpregs __P((struct proc *, struct proc *));
|
||||
int badaddr __P((void *, size_t));
|
||||
|
||||
/* mips_machdep.c */
|
||||
extern void cpu_identify __P((void));
|
||||
extern void mips_vector_init __P((void));
|
||||
void cpu_identify __P((void));
|
||||
void mips_vector_init __P((void));
|
||||
|
||||
/* trap.c */
|
||||
extern void child_return __P((void *));
|
||||
|
||||
/*
|
||||
* MIPS CPU types (cp_imp).
|
||||
*/
|
||||
#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */
|
||||
#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */
|
||||
#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */
|
||||
#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */
|
||||
#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */
|
||||
#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */
|
||||
#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */
|
||||
#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */
|
||||
#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */
|
||||
#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */
|
||||
#define MIPS_UNKC2 0x0c /* unnanounced product cpu ISA III */
|
||||
#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
|
||||
#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
|
||||
/* ID conflict */
|
||||
#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
|
||||
#define MIPS_R3SONY MIPS_R4700 /* Sony R3000 CPU ISA I CLASH */
|
||||
|
||||
#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */
|
||||
/* ID conflict */
|
||||
#define MIPS_R5000 0x23 /* MIPS R5000 based CPU ISA IV */
|
||||
#define MIPS_R3NKK MIPS_R5000 /* NKK R3000 based CPU ISA I CLASH */
|
||||
|
||||
#define MIPS_RM5230 0x28 /* QED RM5230 based CPU ISA IV */
|
||||
|
||||
|
||||
/*
|
||||
* MIPS FPU types
|
||||
*/
|
||||
#define MIPS_SOFT 0x00 /* Software emulation ISA I */
|
||||
#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
|
||||
#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
|
||||
#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
|
||||
#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
|
||||
#define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */
|
||||
#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
|
||||
#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */
|
||||
#define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */
|
||||
#define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */
|
||||
#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
|
||||
#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
|
||||
#define MIPS_R3SONY MIPS_R4700 /* Sony R3000 based FPU ISA I */
|
||||
#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
|
||||
/* ID conflict */
|
||||
#define MIPS_R3NKK MIPS_R5000 /* NKK R3000 based CPU ISA I CLASH */
|
||||
|
||||
#define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */
|
||||
#define MIPS_RM5230 0x28 /* QED RM5230 based FPU ISA IV */
|
||||
|
||||
|
||||
/*
|
||||
* Enable realtime clock (always enabled).
|
||||
*/
|
||||
#define enablertclock()
|
||||
#endif /* _KERNEL */
|
||||
|
||||
#endif /* _CPU_H_ */
|
||||
|
||||
655
sys/arch/mips/include/cpuarch.h
Normal file
655
sys/arch/mips/include/cpuarch.h
Normal file
@ -0,0 +1,655 @@
|
||||
/* $NetBSD: cpuarch.h,v 1.2 1999/01/14 18:45:46 castor Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
* The Regents of the University of California. All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to Berkeley by
|
||||
* Ralph Campbell and Rick Macklem.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the University of
|
||||
* California, Berkeley and its contributors.
|
||||
* 4. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* @(#)machConst.h 8.1 (Berkeley) 6/10/93
|
||||
*
|
||||
* machConst.h --
|
||||
*
|
||||
* Machine dependent constants.
|
||||
*
|
||||
* Copyright (C) 1989 Digital Equipment Corporation.
|
||||
* Permission to use, copy, modify, and distribute this software and
|
||||
* its documentation for any purpose and without fee is hereby granted,
|
||||
* provided that the above copyright notice appears in all copies.
|
||||
* Digital Equipment Corporation makes no representations about the
|
||||
* suitability of this software for any purpose. It is provided "as is"
|
||||
* without express or implied warranty.
|
||||
*
|
||||
* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
|
||||
* v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
|
||||
* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
|
||||
* v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
|
||||
* from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
|
||||
* v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_CPUARCH_H_
|
||||
#define _MIPS_CPUARCH_H_
|
||||
|
||||
/*
|
||||
* Address space.
|
||||
* 32-bit mips CPUS partition their 32-bit address space into four segments:
|
||||
*
|
||||
* kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
|
||||
* kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
|
||||
* kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
|
||||
* kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
|
||||
*
|
||||
* mips1 physical memory is limited to 512Mbytes, which is
|
||||
* doubly mapped in kseg0 (cached) and kseg1 (uncached.)
|
||||
* Caching of mapped addresses is controlled by bits in the TLB entry.
|
||||
*/
|
||||
|
||||
#define MIPS_KUSEG_START 0x0
|
||||
#define MIPS_KSEG0_START 0x80000000
|
||||
#define MIPS_KSEG1_START 0xa0000000
|
||||
#define MIPS_KSEG2_START 0xc0000000
|
||||
#define MIPS_MAX_MEM_ADDR 0xbe000000
|
||||
#define MIPS_RESERVED_ADDR 0xbfc80000
|
||||
|
||||
#define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
|
||||
#define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START)
|
||||
#define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
|
||||
#define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START)
|
||||
|
||||
/* Map virtual address to index in mips3 r4k virtually-indexed cache */
|
||||
#define MIPS3_VA_TO_CINDEX(x) \
|
||||
((unsigned)(x) & 0xffffff | MIPS_KSEG0_START)
|
||||
|
||||
|
||||
/*
|
||||
* The bits in the cause register.
|
||||
*
|
||||
* Bits common to r3000 and r4000:
|
||||
*
|
||||
* MIPS_CR_BR_DELAY Exception happened in branch delay slot.
|
||||
* MIPS_CR_COP_ERR Coprocessor error.
|
||||
* MIPS_CR_IP Interrupt pending bits defined below.
|
||||
* (same meaning as in CAUSE register).
|
||||
* MIPS_CR_EXC_CODE The exception type (see exception codes below).
|
||||
*
|
||||
* Differences:
|
||||
* r3k has 4 bits of execption type, r4k has 5 bits.
|
||||
*/
|
||||
#define MIPS_CR_BR_DELAY 0x80000000
|
||||
#define MIPS_CR_COP_ERR 0x30000000
|
||||
#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */
|
||||
#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
|
||||
#define MIPS_CR_IP 0x0000FF00
|
||||
#define MIPS_CR_EXC_CODE_SHIFT 2
|
||||
|
||||
/*
|
||||
* The bits in the status register. All bits are active when set to 1.
|
||||
*
|
||||
* R3000 status register fields:
|
||||
* MIPS_SR_CO_USABILITY Control the usability of the four coprocessors.
|
||||
* MIPS_SR_BOOT_EXC_VEC Use alternate exception vectors.
|
||||
* MIPS_SR_TLB_SHUTDOWN TLB disabled.
|
||||
*
|
||||
* MIPS_SR_INT_IE Master (current) interrupt enable bit.
|
||||
*
|
||||
* Differences:
|
||||
* r3k has cache control is via frobbing SR register bits, whereas the
|
||||
* r4k cache control is via explicit instructions.
|
||||
* r3k has a 3-entry stack of kernel/user bits, whereas the
|
||||
* r4k has kernel/supervisor/user.
|
||||
*/
|
||||
#define MIPS_SR_COP_USABILITY 0xf0000000
|
||||
#define MIPS_SR_COP_0_BIT 0x10000000
|
||||
#define MIPS_SR_COP_1_BIT 0x20000000
|
||||
|
||||
/* r4k and r3k differences, see below */
|
||||
|
||||
#define MIPS_SR_BOOT_EXC_VEC 0x00400000
|
||||
#define MIPS_SR_TLB_SHUTDOWN 0x00200000
|
||||
|
||||
/* r4k and r3k differences, see below */
|
||||
|
||||
#define MIPS_SR_INT_IE 0x00000001
|
||||
/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
|
||||
/*#define MIPS_SR_INT_MASK 0x0000ff00*/
|
||||
|
||||
#define MIPS_SR_INT_ENAB MIPS_SR_INT_IE /* backwards compatibility */
|
||||
#define MIPS_SR_INT_ENA_CUR MIPS_SR_INT_IE /* backwards compatibility */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* The R2000/R3000-specific status register bit definitions.
|
||||
* all bits are active when set to 1.
|
||||
*
|
||||
* MIPS_SR_PARITY_ERR Parity error.
|
||||
* MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss.
|
||||
* MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits.
|
||||
* MIPS_SR_SWAP_CACHES Swap I-cache and D-cache.
|
||||
* MIPS_SR_ISOL_CACHES Isolate D-cache from main memory.
|
||||
* Interrupt enable bits defined below.
|
||||
* MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode.
|
||||
* MIPS_SR_INT_ENA_OLD Old interrupt enable bit.
|
||||
* MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode.
|
||||
* MIPS_SR_INT_ENA_PREV Previous interrupt enable bit.
|
||||
* MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
|
||||
*/
|
||||
|
||||
#define MIPS1_PARITY_ERR 0x00100000
|
||||
#define MIPS1_CACHE_MISS 0x00080000
|
||||
#define MIPS1_PARITY_ZERO 0x00040000
|
||||
#define MIPS1_SWAP_CACHES 0x00020000
|
||||
#define MIPS1_ISOL_CACHES 0x00010000
|
||||
|
||||
#define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/
|
||||
#define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/
|
||||
#define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/
|
||||
#define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/
|
||||
#define MIPS1_SR_KU_CUR 0x00000002 /* current KU */
|
||||
|
||||
/* backwards compatibility */
|
||||
#define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR
|
||||
#define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS
|
||||
#define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO
|
||||
#define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES
|
||||
#define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES
|
||||
|
||||
#define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD
|
||||
#define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD
|
||||
#define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV
|
||||
#define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR
|
||||
#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
|
||||
|
||||
/*
|
||||
* R4000 status register bit definitons,
|
||||
* where different from r2000/r3000.
|
||||
*/
|
||||
#define MIPS3_SR_XX 0x80000000
|
||||
#define MIPS3_SR_RP 0x08000000
|
||||
#define MIPS3_SR_FR_32 0x04000000
|
||||
#define MIPS3_SR_RE 0x02000000
|
||||
|
||||
#define MIPS3_SR_SOFT_RESET 0x00100000
|
||||
#define MIPS3_SR_DIAG_CH 0x00040000
|
||||
#define MIPS3_SR_DIAG_CE 0x00020000
|
||||
#define MIPS3_SR_DIAG_PE 0x00010000
|
||||
#define MIPS3_SR_KX 0x00000080
|
||||
#define MIPS3_SR_SX 0x00000040
|
||||
#define MIPS3_SR_UX 0x00000020
|
||||
#define MIPS3_SR_KSU_MASK 0x00000018
|
||||
#define MIPS3_SR_KSU_USER 0x00000010
|
||||
#define MIPS3_SR_KSU_SUPER 0x00000008
|
||||
#define MIPS3_SR_KSU_KERNEL 0x00000000
|
||||
#define MIPS3_SR_ERL 0x00000004
|
||||
#define MIPS3_SR_EXL 0x00000002
|
||||
|
||||
#define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET
|
||||
#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH
|
||||
#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE
|
||||
#define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE
|
||||
#define MIPS_SR_KX MIPS3_SR_KX
|
||||
#define MIPS_SR_SX MIPS3_SR_SX
|
||||
#define MIPS_SR_UX MIPS3_SR_UX
|
||||
|
||||
#define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK
|
||||
#define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER
|
||||
#define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER
|
||||
#define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL
|
||||
#define MIPS_SR_ERL MIPS3_SR_ERL
|
||||
#define MIPS_SR_EXL MIPS3_SR_EXL
|
||||
|
||||
|
||||
/*
|
||||
* The interrupt masks.
|
||||
* If a bit in the mask is 1 then the interrupt is enabled (or pending).
|
||||
*/
|
||||
#define MIPS_INT_MASK 0xff00
|
||||
#define MIPS_INT_MASK_5 0x8000
|
||||
#define MIPS_INT_MASK_4 0x4000
|
||||
#define MIPS_INT_MASK_3 0x2000
|
||||
#define MIPS_INT_MASK_2 0x1000
|
||||
#define MIPS_INT_MASK_1 0x0800
|
||||
#define MIPS_INT_MASK_0 0x0400
|
||||
#define MIPS_HARD_INT_MASK 0xfc00
|
||||
#define MIPS_SOFT_INT_MASK_1 0x0200
|
||||
#define MIPS_SOFT_INT_MASK_0 0x0100
|
||||
|
||||
|
||||
/*
|
||||
* nesting interrupt masks.
|
||||
*/
|
||||
#define MIPS_INT_MASK_SPL_SOFT0 MIPS_SOFT_INT_MASK_0
|
||||
#define MIPS_INT_MASK_SPL_SOFT1 (MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0)
|
||||
#define MIPS_INT_MASK_SPL0 (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1)
|
||||
#define MIPS_INT_MASK_SPL1 (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0)
|
||||
#define MIPS_INT_MASK_SPL2 (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1)
|
||||
#define MIPS_INT_MASK_SPL3 (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2)
|
||||
#define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3)
|
||||
#define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4)
|
||||
|
||||
/*
|
||||
* mips3 CPUs have on-chip timer at INT_MASK_5. We don't support it yet.
|
||||
*/
|
||||
#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
|
||||
#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
|
||||
|
||||
|
||||
/*
|
||||
* The bits in the context register.
|
||||
*/
|
||||
#define MIPS1_CNTXT_PTE_BASE 0xFFE00000
|
||||
#define MIPS1_CNTXT_BAD_VPN 0x001FFFFC
|
||||
|
||||
#define MIPS3_CNTXT_PTE_BASE 0xFF800000
|
||||
#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0
|
||||
|
||||
/*
|
||||
* The bits in the MIPS3 config register.
|
||||
*
|
||||
* bit 0..5: R/W, Bit 6..31: R/O
|
||||
*/
|
||||
|
||||
/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
|
||||
#define MIPS3_CONFIG_K0_MASK 0x00000007
|
||||
|
||||
/*
|
||||
* R/W Update on Store Conditional
|
||||
* 0: Store Conditional uses coherency algorithm specified by TLB
|
||||
* 1: Store Conditional uses cacheable coherent update on write
|
||||
*/
|
||||
#define MIPS3_CONFIG_CU 0x00000008
|
||||
|
||||
#define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */
|
||||
#define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */
|
||||
#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \
|
||||
(((config) & (bit)) ? 32 : 16)
|
||||
|
||||
#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
|
||||
#define MIPS3_CONFIG_DC_SHIFT 6
|
||||
#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
|
||||
#define MIPS3_CONFIG_IC_SHIFT 9
|
||||
#define MIPS3_CONFIG_CACHE_SIZE(config, mask, shift) \
|
||||
(0x1000 << (((config) & (mask)) >> (shift)))
|
||||
|
||||
/* Block ordering: 0: sequential, 1: sub-block */
|
||||
#define MIPS3_CONFIG_EB 0x00002000
|
||||
|
||||
/* ECC mode - 0: ECC mode, 1: parity mode */
|
||||
#define MIPS3_CONFIG_EM 0x00004000
|
||||
|
||||
/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
|
||||
#define MIPS3_CONFIG_BE 0x00008000
|
||||
|
||||
/* Dirty Shared coherency state - 0: enabled, 1: disabled */
|
||||
#define MIPS3_CONFIG_SM 0x00010000
|
||||
|
||||
/* Secondary Cache - 0: present, 1: not present */
|
||||
#define MIPS3_CONFIG_SC 0x00020000
|
||||
|
||||
/* System Port width - 0: 64-bit, 1,2,3: reserved */
|
||||
#define MIPS3_CONFIG_EW_MASK 0x000c0000
|
||||
#define MIPS3_CONFIG_EW_SHIFT 18
|
||||
|
||||
/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
|
||||
#define MIPS3_CONFIG_SW 0x00100000
|
||||
|
||||
/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
|
||||
#define MIPS3_CONFIG_SS 0x00200000
|
||||
|
||||
/* Secondary Cache line size */
|
||||
#define MIPS3_CONFIG_SB_MASK 0x00c00000
|
||||
#define MIPS3_CONFIG_SB_SHIFT 22
|
||||
#define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \
|
||||
(0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
|
||||
|
||||
/* write back data rate */
|
||||
#define MIPS3_CONFIG_EP_MASK 0x0f000000
|
||||
#define MIPS3_CONFIG_EP_SHIFT 24
|
||||
|
||||
/* System clock ratio - this value is CPU dependent */
|
||||
#define MIPS3_CONFIG_EC_MASK 0x70000000
|
||||
#define MIPS3_CONFIG_EC_SHIFT 28
|
||||
|
||||
/* Master-Checker Mode - 1: enabled */
|
||||
#define MIPS3_CONFIG_CM 0x80000000
|
||||
|
||||
/*
|
||||
* Location of exception vectors.
|
||||
*
|
||||
* Common vectors: reset and UTLB miss.
|
||||
*/
|
||||
#define MIPS_RESET_EXC_VEC 0xBFC00000
|
||||
#define MIPS_UTLB_MISS_EXC_VEC 0x80000000
|
||||
|
||||
/*
|
||||
* R3000 general exception vector (everything else)
|
||||
*/
|
||||
#define MIPS1_GEN_EXC_VEC 0x80000080
|
||||
|
||||
/*
|
||||
* R4000 MIPS-III exception vectors
|
||||
*/
|
||||
#define MIPS3_XTLB_MISS_EXC_VEC 0x80000080
|
||||
#define MIPS3_CACHE_ERR_EXC_VEC 0x80000100
|
||||
#define MIPS3_GEN_EXC_VEC 0x80000180
|
||||
|
||||
/*
|
||||
* Coprocessor 0 registers:
|
||||
*
|
||||
* MIPS_COP_0_TLB_INDEX TLB index.
|
||||
* MIPS_COP_0_TLB_RANDOM TLB random.
|
||||
* MIPS_COP_0_TLB_LOW r3k TLB entry low.
|
||||
* MIPS_COP_0_TLB_LO0 r4k TLB entry low.
|
||||
* MIPS_COP_0_TLB_LO1 r4k TLB entry low, extended.
|
||||
* MIPS_COP_0_TLB_CONTEXT TLB context.
|
||||
* MIPS_COP_0_BAD_VADDR Bad virtual address.
|
||||
* MIPS_COP_0_TLB_HI TLB entry high.
|
||||
* MIPS_COP_0_STATUS Status register.
|
||||
* MIPS_COP_0_CAUSE Exception cause register.
|
||||
* MIPS_COP_0_EXC_PC Exception PC.
|
||||
* MIPS_COP_0_PRID Processor revision identifier.
|
||||
*/
|
||||
#define MIPS_COP_0_TLB_INDEX $0
|
||||
#define MIPS_COP_0_TLB_RANDOM $1
|
||||
/* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
|
||||
|
||||
#define MIPS_COP_0_TLB_CONTEXT $4
|
||||
/* $5 and $6 new with MIPS-III */
|
||||
#define MIPS_COP_0_BAD_VADDR $8
|
||||
#define MIPS_COP_0_TLB_HI $10
|
||||
#define MIPS_COP_0_STATUS $12
|
||||
#define MIPS_COP_0_CAUSE $13
|
||||
#define MIPS_COP_0_EXC_PC $14
|
||||
#define MIPS_COP_0_PRID $15
|
||||
|
||||
#define MIPS_COP_O_STATUS_REG $12 /* XXX retain compatibility XXX */
|
||||
#define MIPS_COP_O_CAUSE_REG $13 /* XXX retain compatibility XXX */
|
||||
|
||||
/* ISA-I */
|
||||
#define MIPS_COP_0_TLB_LOW $2
|
||||
|
||||
/* ISA-III */
|
||||
#define MIPS_COP_0_TLB_LO0 $2
|
||||
#define MIPS_COP_0_TLB_LO1 $3
|
||||
|
||||
#define MIPS_COP_0_TLB_PG_MASK $5
|
||||
#define MIPS_COP_0_TLB_WIRED $6
|
||||
|
||||
#define MIPS_COP_0_COUNT $9
|
||||
#define MIPS_COP_0_COMPARE $11
|
||||
|
||||
#define MIPS_COP_0_CONFIG $16
|
||||
#define MIPS_COP_0_LLADDR $17
|
||||
#define MIPS_COP_0_WATCH_LO $18
|
||||
#define MIPS_COP_0_WATCH_HI $19
|
||||
#define MIPS_COP_0_TLB_XCONTEXT $20
|
||||
#define MIPS_COP_0_ECC $26
|
||||
#define MIPS_COP_0_CACHE_ERR $27
|
||||
#define MIPS_COP_0_TAG_LO $28
|
||||
#define MIPS_COP_0_TAG_HI $29
|
||||
#define MIPS_COP_0_ERROR_PC $30
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Values for the code field in a break instruction.
|
||||
*/
|
||||
#define MIPS_BREAK_INSTR 0x0000000d
|
||||
#define MIPS_BREAK_VAL_MASK 0x03ff0000
|
||||
#define MIPS_BREAK_VAL_SHIFT 16
|
||||
#define MIPS_BREAK_KDB_VAL 512
|
||||
#define MIPS_BREAK_SSTEP_VAL 513
|
||||
#define MIPS_BREAK_BRKPT_VAL 514
|
||||
#define MIPS_BREAK_SOVER_VAL 515
|
||||
#define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \
|
||||
(MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
|
||||
#define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \
|
||||
(MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
|
||||
#define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \
|
||||
(MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
|
||||
#define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \
|
||||
(MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
|
||||
|
||||
/*
|
||||
* Mininum and maximum cache sizes.
|
||||
*/
|
||||
#define MIPS_MIN_CACHE_SIZE (16 * 1024)
|
||||
#define MIPS_MAX_CACHE_SIZE (256 * 1024)
|
||||
|
||||
/*
|
||||
* The floating point version and status registers.
|
||||
*/
|
||||
#define MIPS_FPU_ID $0
|
||||
#define MIPS_FPU_CSR $31
|
||||
|
||||
/*
|
||||
* The floating point coprocessor status register bits.
|
||||
*/
|
||||
#define MIPS_FPU_ROUNDING_BITS 0x00000003
|
||||
#define MIPS_FPU_ROUND_RN 0x00000000
|
||||
#define MIPS_FPU_ROUND_RZ 0x00000001
|
||||
#define MIPS_FPU_ROUND_RP 0x00000002
|
||||
#define MIPS_FPU_ROUND_RM 0x00000003
|
||||
#define MIPS_FPU_STICKY_BITS 0x0000007c
|
||||
#define MIPS_FPU_STICKY_INEXACT 0x00000004
|
||||
#define MIPS_FPU_STICKY_UNDERFLOW 0x00000008
|
||||
#define MIPS_FPU_STICKY_OVERFLOW 0x00000010
|
||||
#define MIPS_FPU_STICKY_DIV0 0x00000020
|
||||
#define MIPS_FPU_STICKY_INVALID 0x00000040
|
||||
#define MIPS_FPU_ENABLE_BITS 0x00000f80
|
||||
#define MIPS_FPU_ENABLE_INEXACT 0x00000080
|
||||
#define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100
|
||||
#define MIPS_FPU_ENABLE_OVERFLOW 0x00000200
|
||||
#define MIPS_FPU_ENABLE_DIV0 0x00000400
|
||||
#define MIPS_FPU_ENABLE_INVALID 0x00000800
|
||||
#define MIPS_FPU_EXCEPTION_BITS 0x0003f000
|
||||
#define MIPS_FPU_EXCEPTION_INEXACT 0x00001000
|
||||
#define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000
|
||||
#define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000
|
||||
#define MIPS_FPU_EXCEPTION_DIV0 0x00008000
|
||||
#define MIPS_FPU_EXCEPTION_INVALID 0x00010000
|
||||
#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
|
||||
#define MIPS_FPU_COND_BIT 0x00800000
|
||||
#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
|
||||
#define MIPS1_FPC_MBZ_BITS 0xff7c0000
|
||||
#define MIPS3_FPC_MBZ_BITS 0xfe7c0000
|
||||
|
||||
|
||||
/*
|
||||
* Constants to determine if have a floating point instruction.
|
||||
*/
|
||||
#define MIPS_OPCODE_SHIFT 26
|
||||
#define MIPS_OPCODE_C1 0x11
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* The low part of the TLB entry.
|
||||
*/
|
||||
#define MIPS1_TLB_PHYS_PAGE_SHIFT 12
|
||||
#define MIPS1_TLB_PF_NUM 0xfffff000
|
||||
#define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800
|
||||
#define MIPS1_TLB_MOD_BIT 0x00000400
|
||||
#define MIPS1_TLB_VALID_BIT 0x00000200
|
||||
#define MIPS1_TLB_GLOBAL_BIT 0x00000100
|
||||
|
||||
#define MIPS3_TLB_PHYS_PAGE_SHIFT 6
|
||||
#define MIPS3_TLB_PF_NUM 0x3fffffc0
|
||||
|
||||
#define MIPS3_TLB_MOD_BIT 0x00000004
|
||||
#define MIPS3_TLB_VALID_BIT 0x00000002
|
||||
#define MIPS3_TLB_GLOBAL_BIT 0x00000001
|
||||
|
||||
/*
|
||||
* MIPS3_TLB_ATTR values - coherency algorithm:
|
||||
* 0: cacheable, noncoherent, write-through, no write allocate
|
||||
* 1: cacheable, noncoherent, write-through, write allocate
|
||||
* 2: uncached
|
||||
* 3: cacheable, noncoherent, write-back (noncoherent)
|
||||
* 4: cacheable, coherent, write-back, exclusive (exclusive)
|
||||
* 5: cacheable, coherent, write-back, exclusive on write (sharable)
|
||||
* 6: cacheable, coherent, write-back, update on write (update)
|
||||
* 7: cacheable, ?, ?, ?, ?
|
||||
*/
|
||||
#define MIPS3_TLB_ATTR_WT 0 /* IDT */
|
||||
#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
|
||||
#define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */
|
||||
#define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */
|
||||
#define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */
|
||||
#define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */
|
||||
#define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */
|
||||
|
||||
|
||||
/*
|
||||
* The high part of the TLB entry.
|
||||
*/
|
||||
#define MIPS_TLB_VIRT_PAGE_SHIFT 12
|
||||
|
||||
#define MIPS1_TLB_VIRT_PAGE_NUM 0xfffff000
|
||||
#define MIPS1_TLB_PID 0x00000fc0
|
||||
#define MIPS1_TLB_PID_SHIFT 6
|
||||
|
||||
#define MIPS3_TLB_VIRT_PAGE_NUM 0xffffe000
|
||||
#define MIPS3_TLB_PID 0x000000ff
|
||||
#define MIPS3_TLB_PID_SHIFT 0
|
||||
|
||||
|
||||
/*
|
||||
* r3000: shift count to put the index in the right spot.
|
||||
* (zero on r4000?)
|
||||
*/
|
||||
#define MIPS1_TLB_INDEX_SHIFT 8
|
||||
|
||||
|
||||
/*
|
||||
* The number of TLB entries and the first one that write random hits.
|
||||
*/
|
||||
#define MIPS1_TLB_NUM_TLB_ENTRIES 64
|
||||
#define MIPS1_TLB_FIRST_RAND_ENTRY 8
|
||||
|
||||
#define MIPS3_TLB_NUM_TLB_ENTRIES 48
|
||||
#define MIPS_R4300_TLB_NUM_TLB_ENTRIES 32
|
||||
#define MIPS3_TLB_WIRED_ENTRIES 2
|
||||
|
||||
|
||||
/*
|
||||
* The number of process id entries.
|
||||
*/
|
||||
#define MIPS1_TLB_NUM_PIDS 64
|
||||
#define MIPS3_TLB_NUM_PIDS 256
|
||||
|
||||
/*
|
||||
* backwards compatibility with existing locore and compile-time
|
||||
* mips1/mips3 binding.
|
||||
*
|
||||
* XXX INT_MASK and HARD_INT_MASK are here only because we dont
|
||||
* support the mips3 on-chip timer which is tied to INT_5.
|
||||
*/
|
||||
|
||||
#if defined(MIPS3) && !defined(MIPS1)
|
||||
#define MIPS_TLB_PID_SHIFT MIPS3_TLB_PID_SHIFT
|
||||
#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_PIDS
|
||||
#endif
|
||||
|
||||
#if !defined(MIPS3) && defined(MIPS1)
|
||||
#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
|
||||
#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(MIPS1) && defined(MIPS3)
|
||||
#define MIPS_TLB_PID_SHIFT \
|
||||
((CPUISMIPS3)? MIPS3_TLB_PID_SHIFT : MIPS1_TLB_PID_SHIFT)
|
||||
|
||||
#define MIPS_TLB_NUM_PIDS \
|
||||
((CPUISMIPS3)? MIPS3_TLB_NUM_PIDS : MIPS1_TLB_NUM_PIDS)
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* TLB probe return codes.
|
||||
*/
|
||||
#define MIPS_TLB_NOT_FOUND 0
|
||||
#define MIPS_TLB_FOUND 1
|
||||
#define MIPS_TLB_FOUND_WITH_PATCH 2
|
||||
#define MIPS_TLB_PROBE_ERROR 3
|
||||
|
||||
/*
|
||||
* CPU processor revision ID
|
||||
*/
|
||||
#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */
|
||||
#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */
|
||||
#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */
|
||||
#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */
|
||||
#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */
|
||||
#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */
|
||||
#define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 CPU ISA I */
|
||||
#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */
|
||||
#define MIPS_R4200 0x0a /* NEC VR4200 CPU ISA III */
|
||||
#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */
|
||||
#define MIPS_R4100 0x0c /* NEC VR4100 CPU ISA III */
|
||||
#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
|
||||
#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
|
||||
#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
|
||||
#define MIPS_R4650 0x22 /* !ID crash! QED R4650 CPU ISA III */
|
||||
#define MIPS_TX3900 0x22 /* !ID crash! Toshiba R3000 CPU ISA I */
|
||||
#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */
|
||||
#define MIPS_RC32364 0x26 /* IDT RC32364 CPU ISA II */
|
||||
#define MIPS_RM5230 0x28 /* QED RM5230 CPU ISA IV */
|
||||
#define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 CPU ISA III */
|
||||
#define MIPS_R3SONY 0x21 /* ? Sony R3000 based CPU ISA I */
|
||||
#define MIPS_R3NKK 0x23 /* ? NKK R3000 based CPU ISA I */
|
||||
|
||||
/*
|
||||
* FPU processor revision ID
|
||||
*/
|
||||
#define MIPS_SOFT 0x00 /* Software emulation ISA I */
|
||||
#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
|
||||
#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
|
||||
#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
|
||||
#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
|
||||
#define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */
|
||||
#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
|
||||
#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */
|
||||
#define MIPS_R4210 0x0a /* NEC VR4210 FPC ISA III */
|
||||
#define MIPS_R4300 0x0b /* NEC VR4300 FPC ISA III */
|
||||
#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
|
||||
#define MIPS_R4600 0x20 /* QED R4600 Orion FPU ISA III */
|
||||
#define MIPS_R5010 0x23 /* MIPS R5000 FPU ISA IV */
|
||||
#define MIPS_RC32364 0x26 /* IDT RC32364 FPU ISA II */
|
||||
#define MIPS_RM5230 0x28 /* QED RM5230 FPU ISA IV */
|
||||
#define MIPS_R3SONY 0x21 /* ? Sony R3000 based FPU ISA I */
|
||||
#define MIPS_R3TOSH 0x22 /* ? Toshiba R3000 based FPU ISA I */
|
||||
#define MIPS_R3NKK 0x23 /* ? NKK R3000 based FPU ISA I */
|
||||
|
||||
#endif /* _MIPS_CPUARCH_H_ */
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: db_machdep.h,v 1.5 1999/01/06 04:11:28 nisimura Exp $ */
|
||||
/* $NetBSD: db_machdep.h,v 1.6 1999/01/14 18:45:45 castor Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
|
||||
@ -78,11 +78,10 @@ db_addr_t db_disasm_insn __P((int insn, db_addr_t loc, boolean_t altfmt));
|
||||
/*
|
||||
* Entrypoints to DDB for kernel, keyboard drivers, init hook
|
||||
*/
|
||||
void kdb_kbd_trap __P((int *));
|
||||
int kdb_trap __P((int type, int *));
|
||||
void kdb_kbd_trap __P((db_regs_t *));
|
||||
int kdb_trap __P((int type, mips_reg_t *));
|
||||
void db_machine_init __P((void));
|
||||
|
||||
|
||||
/*
|
||||
* We use ELF symbols in DDB.
|
||||
*
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: locore.h,v 1.15 1999/01/06 04:11:27 nisimura Exp $ */
|
||||
/* $NetBSD: locore.h,v 1.16 1999/01/14 18:45:46 castor Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright 1996 The Board of Trustees of The Leland Stanford
|
||||
@ -20,18 +20,16 @@
|
||||
* The following functions must be provided for each mips ISA level:
|
||||
*
|
||||
*
|
||||
* MachConfigCache
|
||||
* MachFlushCache
|
||||
* MachFlushDCache
|
||||
* MachFlushICache
|
||||
* MachForceCacheUpdate
|
||||
* MachSetPID
|
||||
* MachTLBFlush
|
||||
* MachTLBFlushAddr __P()
|
||||
* MachTLBUpdate (u_int, (pt_entry_t?) u_int);
|
||||
* MachTLBFlushAddr
|
||||
* MachTLBUpdate
|
||||
* wbflush
|
||||
* proc_trampoline()
|
||||
* switch_exit()
|
||||
* cpu_switch_resume()
|
||||
*
|
||||
* We currently provide support for:
|
||||
@ -43,29 +41,20 @@
|
||||
#ifndef _MIPS_LOCORE_H
|
||||
#define _MIPS_LOCORE_H
|
||||
|
||||
#include "opt_mips_cache.h"
|
||||
|
||||
/*
|
||||
* locore service routine for exeception vectors. Used outside locore
|
||||
* locore service routine for exception vectors. Used outside locore
|
||||
* only to print them by name in stack tracebacks
|
||||
*/
|
||||
|
||||
/* Block out one hardware interrupt-enable bit. */
|
||||
extern int Mach_spl0 __P((void)), Mach_spl1 __P((void));
|
||||
extern int Mach_spl2 __P((void)), Mach_spl3 __P((void));
|
||||
extern int Mach_spl4 __P((void)), Mach_spl5 __P((void));
|
||||
|
||||
/* Block out nested interrupt-enable bits. */
|
||||
extern int cpu_spl0 __P((void)), cpu_spl1 __P((void));
|
||||
extern int cpu_spl2 __P((void)), cpu_spl3 __P((void));
|
||||
extern int cpu_spl4 __P((void)), cpu_spl5 __P((void));
|
||||
extern int splhigh __P((void));
|
||||
|
||||
extern u_int32_t mips_read_causereg __P((void));
|
||||
extern u_int32_t mips_read_statusreg __P((void));
|
||||
|
||||
extern void mips1_ConfigCache __P((void));
|
||||
extern void mips1_FlushCache __P((void));
|
||||
extern void mips1_FlushDCache __P((vaddr_t addr, vaddr_t len));
|
||||
extern void mips1_FlushICache __P((vaddr_t addr, vaddr_t len));
|
||||
extern void mips1_FlushDCache __P((vaddr_t addr, vsize_t len));
|
||||
extern void mips1_FlushICache __P((vaddr_t addr, vsize_t len));
|
||||
extern void mips1_ForceCacheUpdate __P((void));
|
||||
extern void mips1_SetPID __P((int pid));
|
||||
extern void mips1_TLBFlush __P((int numtlb));
|
||||
@ -76,12 +65,14 @@ extern void mips1_TLBWriteIndexed __P((u_int index, u_int high,
|
||||
u_int low));
|
||||
extern void mips1_wbflush __P((void));
|
||||
extern void mips1_proc_trampoline __P((void));
|
||||
extern void mips1_switch_exit __P((struct proc *));
|
||||
extern void mips1_cpu_switch_resume __P((void));
|
||||
|
||||
extern void mips3_ConfigCache __P((void));
|
||||
extern void mips3_FlushCache __P((void));
|
||||
extern void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len));
|
||||
#ifdef MIPS3_L2CACHE_ABSENT
|
||||
extern void mips52xx_FlushDCache __P((vaddr_t addr, vaddr_t len));
|
||||
#endif
|
||||
extern void mips3_FlushICache __P((vaddr_t addr, vaddr_t len));
|
||||
extern void mips3_ForceCacheUpdate __P((void));
|
||||
extern void mips3_HitFlushDCache __P((vaddr_t, int));
|
||||
@ -92,20 +83,23 @@ extern void mips3_TLBFlushAddr __P( /* XXX Really pte highpart ? */
|
||||
extern int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int));
|
||||
struct tlb;
|
||||
extern void mips3_TLBRead __P((int, struct tlb *));
|
||||
#if 0
|
||||
extern void mips3_TLBWriteIndexedVPS __P((u_int index, struct tlb *tlb));
|
||||
extern void mips3_TLBWriteIndexed __P((u_int index, u_int high,
|
||||
u_int lo0, u_int lo1));
|
||||
#endif
|
||||
extern void mips3_wbflush __P((void));
|
||||
extern void mips3_proc_trampoline __P((void));
|
||||
extern void mips3_switch_exit __P((struct proc *));
|
||||
extern void mips3_cpu_switch_resume __P((void));
|
||||
|
||||
extern void mips3_SetWIRED __P((int));
|
||||
|
||||
extern u_int32_t mips3_cycle_count __P((void));
|
||||
extern u_int32_t mips3_write_count __P((u_int32_t));
|
||||
extern u_int32_t mips3_read_compare __P((void));
|
||||
extern u_int32_t mips3_read_config __P((void));
|
||||
extern void mips3_write_compare __P((u_int32_t));
|
||||
extern void mips3_write_xcontext_upper __P((u_int32_t));
|
||||
|
||||
/*
|
||||
* A vector with an entry for each mips-ISA-level dependent
|
||||
@ -114,10 +108,9 @@ extern void mips3_write_compare __P((u_int32_t));
|
||||
* Sprite coding-convention names used in 4.4bsd/pmax.
|
||||
*/
|
||||
typedef struct {
|
||||
void (*configCache) __P((void));
|
||||
void (*flushCache) __P((void));
|
||||
void (*flushDCache) __P((vaddr_t addr, vaddr_t len));
|
||||
void (*flushICache) __P((vaddr_t addr, vaddr_t len));
|
||||
void (*flushDCache) __P((vaddr_t addr, vsize_t len));
|
||||
void (*flushICache) __P((vaddr_t addr, vsize_t len));
|
||||
void (*forceCacheUpdate) __P((void));
|
||||
void (*setTLBpid) __P((int pid));
|
||||
void (*tlbFlush) __P((int numtlb));
|
||||
@ -125,7 +118,6 @@ typedef struct {
|
||||
int (*tlbUpdate) __P((u_int highreg, u_int lowreg));
|
||||
void (*wbflush) __P((void));
|
||||
void (*proc_trampoline) __P((void));
|
||||
void (*mips_switch_exit) __P((struct proc *));
|
||||
void (*cpu_switch_resume) __P((void));
|
||||
} mips_locore_jumpvec_t;
|
||||
|
||||
@ -142,9 +134,14 @@ extern mips_locore_jumpvec_t r2000_locore_vec;
|
||||
extern mips_locore_jumpvec_t r4000_locore_vec;
|
||||
|
||||
#if defined(MIPS3) && !defined (MIPS1)
|
||||
#define MachConfigCache mips3_ConfigCache
|
||||
#define MachFlushCache mips3_FlushCache
|
||||
#if defined(MIPS3_L2CACHE_ABSENT) && !defined(MIPS3_L2CACHE_PRESENT)
|
||||
#define MachFlushDCache mips52xx_FlushDCache
|
||||
#elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT)
|
||||
#define MachFlushDCache mips3_FlushDCache
|
||||
#else
|
||||
#define MachFlushDCache (*(mips_locore_jumpvec.flushDCache))
|
||||
#endif
|
||||
#define MachFlushICache mips3_FlushICache
|
||||
#define MachForceCacheUpdate mips3_ForceCacheUpdate
|
||||
#define MachSetPID mips3_SetPID
|
||||
@ -153,11 +150,9 @@ extern mips_locore_jumpvec_t r4000_locore_vec;
|
||||
#define MachTLBUpdate mips3_TLBUpdate
|
||||
#define wbflush mips3_wbflush
|
||||
#define proc_trampoline mips3_proc_trampoline
|
||||
#define switch_exit mips3_switch_exit
|
||||
#endif
|
||||
|
||||
#if !defined(MIPS3) && defined (MIPS1)
|
||||
#define MachConfigCache mips1_ConfigCache
|
||||
#define MachFlushCache mips1_FlushCache
|
||||
#define MachFlushDCache mips1_FlushDCache
|
||||
#define MachFlushICache mips1_FlushICache
|
||||
@ -168,13 +163,11 @@ extern mips_locore_jumpvec_t r4000_locore_vec;
|
||||
#define MachTLBUpdate mips1_TLBUpdate
|
||||
#define wbflush mips1_wbflush
|
||||
#define proc_trampoline mips1_proc_trampoline
|
||||
#define switch_exit mips1_switch_exit
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined(MIPS3) && defined (MIPS1)
|
||||
#define MachConfigCache (*(mips_locore_jumpvec.configCache))
|
||||
#define MachFlushCache (*(mips_locore_jumpvec.flushCache))
|
||||
#define MachFlushDCache (*(mips_locore_jumpvec.flushDCache))
|
||||
#define MachFlushICache (*(mips_locore_jumpvec.flushICache))
|
||||
@ -185,11 +178,9 @@ extern mips_locore_jumpvec_t r4000_locore_vec;
|
||||
#define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate))
|
||||
#define wbflush (*(mips_locore_jumpvec.wbflush))
|
||||
#define proc_trampoline (mips_locore_jumpvec.proc_trampoline)
|
||||
#define switch_exit (*(mips_locore_jumpvec.mips_switch_exit))
|
||||
#endif
|
||||
|
||||
/* cpu_switch_resume not called directly */
|
||||
|
||||
/* cpu_switch_resume is called inside locore.S */
|
||||
|
||||
/*
|
||||
* CPU identification, from PRID register.
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: mips_param.h,v 1.10 1998/09/11 16:46:31 jonathan Exp $ */
|
||||
/* $NetBSD: mips_param.h,v 1.11 1999/01/14 18:45:45 castor Exp $ */
|
||||
|
||||
/*
|
||||
* Architecture name.
|
||||
@ -16,10 +16,7 @@
|
||||
#define SINCR 1 /* increment of stack/NBPG */
|
||||
|
||||
#define UPAGES 2 /* pages of u-area */
|
||||
#define UADDR 0xffffc000 /* address of u */
|
||||
#define USPACE (UPAGES*NBPG) /* size of u-area in bytes */
|
||||
#define UVPN (UADDR>>PGSHIFT)/* virtual page number of u */
|
||||
#define KERNELSTACK (UADDR+UPAGES*NBPG) /* top of kernel stack */
|
||||
|
||||
#ifndef MSGBUFSIZE
|
||||
#define MSGBUFSIZE NBPG /* default message buffer size */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: pcb.h,v 1.7 1997/06/15 17:36:24 mhitch Exp $ */
|
||||
/* $NetBSD: pcb.h,v 1.8 1999/01/14 18:45:45 castor Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1988 University of Utah.
|
||||
@ -49,9 +49,9 @@
|
||||
*/
|
||||
struct pcb
|
||||
{
|
||||
int pcb_regs[38]; /* XXX saved general registers */
|
||||
mips_reg_t pcb_regs[38]; /* XXX saved general registers */
|
||||
struct fpreg pcb_fpregs; /* saved floating point registers */
|
||||
int pcb_context[12]; /* kernel context for resume */
|
||||
mips_reg_t pcb_context[12]; /* kernel context for resume */
|
||||
caddr_t pcb_onfault; /* for copyin/copyout faults */
|
||||
void *pcb_segtab; /* XXX copy of pmap pm_segtab */
|
||||
};
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: pmap.h,v 1.22 1999/01/06 04:11:25 nisimura Exp $ */
|
||||
/* $NetBSD: pmap.h,v 1.23 1999/01/14 18:45:45 castor Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1987 Carnegie-Mellon University
|
||||
@ -42,7 +42,7 @@
|
||||
#ifndef _PMAP_MACHINE_
|
||||
#define _PMAP_MACHINE_
|
||||
|
||||
#include <mips/cpuregs.h> /* for KSEG0 below */
|
||||
#include <mips/cpuarch.h> /* for KSEG0 below */
|
||||
|
||||
/*
|
||||
* The user address space is 2Gb (0x0 - 0x80000000).
|
||||
@ -98,7 +98,7 @@ typedef struct pmap {
|
||||
typedef struct pv_entry {
|
||||
struct pv_entry *pv_next; /* next pv_entry */
|
||||
struct pmap *pv_pmap; /* pmap where mapping lies */
|
||||
vaddr_t pv_va; /* virtual address for mapping */
|
||||
vaddr_t pv_va; /* virtual address for mapping */
|
||||
int pv_flags; /* some flags for the mapping */
|
||||
} *pv_entry_t;
|
||||
|
||||
@ -122,7 +122,6 @@ struct pmap kernel_pmap_store;
|
||||
void pmap_bootstrap __P((void));
|
||||
|
||||
void pmap_set_modified __P((paddr_t));
|
||||
void pmap_set_referenced __P((paddr_t));
|
||||
|
||||
/*
|
||||
* pmap_prefer() helps reduce virtual-coherency exceptions in
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: proc.h,v 1.8 1997/07/07 03:54:29 jonathan Exp $ */
|
||||
/* $NetBSD: proc.h,v 1.9 1999/01/14 18:45:45 castor Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
@ -44,7 +44,7 @@
|
||||
* Machine-dependent part of the proc structure for MIPS
|
||||
*/
|
||||
struct mdproc {
|
||||
int *md_regs; /* registers on current frame */
|
||||
void *md_regs; /* registers on current frame */
|
||||
int md_flags; /* machine-dependent flags */
|
||||
int md_upte[UPAGES]; /* ptes for mapping u page */
|
||||
int md_ss_addr; /* single step address for ptrace */
|
||||
@ -58,7 +58,7 @@ struct mdproc {
|
||||
* MIPS trapframe
|
||||
*/
|
||||
struct frame {
|
||||
int f_regs[38];
|
||||
mips_reg_t f_regs[38];
|
||||
};
|
||||
|
||||
#ifdef _KERNEL
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: psl.h,v 1.9 1998/09/11 16:46:32 jonathan Exp $ */
|
||||
/* $NetBSD: psl.h,v 1.10 1999/01/14 18:45:45 castor Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
@ -44,15 +44,23 @@
|
||||
* configured CPU types.
|
||||
*/
|
||||
|
||||
#include <mips/cpuregs.h>
|
||||
#include <mips/cpuarch.h>
|
||||
|
||||
/*
|
||||
* mips3-specific definitions
|
||||
*/
|
||||
#define MIPS3_PSL_LOWIPL (MIPS3_INT_MASK | MIPS_SR_INT_IE)
|
||||
|
||||
#if defined(_MIPS_BSD_SIM) && _MIPS_BSD_SIM != _MIPS_SIM_ABI32
|
||||
#define MIPS3_PSL_XFLAGS \
|
||||
(MIPS3_SR_XX | MIPS3_SR_KX | MIPS3_SR_UX | MIPS3_SR_SX)
|
||||
#else
|
||||
#define MIPS3_PSL_XFLAGS (0)
|
||||
#endif
|
||||
|
||||
#define MIPS3_PSL_USERSET \
|
||||
(MIPS3_SR_KSU_USER | \
|
||||
MIPS3_PSL_XFLAGS | \
|
||||
MIPS_SR_INT_IE | \
|
||||
MIPS3_SR_EXL | \
|
||||
MIPS3_INT_MASK)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: reg.h,v 1.8 1997/07/19 09:54:23 jonathan Exp $ */
|
||||
/* $NetBSD: reg.h,v 1.9 1999/01/14 18:45:45 castor Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1988 University of Utah.
|
||||
@ -45,12 +45,13 @@
|
||||
#ifndef _MACHINE_REG_H_
|
||||
#define _MACHINE_REG_H_
|
||||
|
||||
|
||||
struct reg {
|
||||
int r_regs[38];
|
||||
mips_reg_t r_regs[38];
|
||||
};
|
||||
|
||||
struct fpreg {
|
||||
int r_regs[33];
|
||||
mips_fpreg_t r_regs[33];
|
||||
};
|
||||
|
||||
#endif /*_MACHINE_REG_H_*/
|
||||
|
||||
@ -1,7 +1,14 @@
|
||||
/* $NetBSD: setjmp.h,v 1.2 1998/09/16 23:15:08 thorpej Exp $ */
|
||||
/* $NetBSD: setjmp.h,v 1.3 1999/01/14 18:45:45 castor Exp $ */
|
||||
|
||||
/*
|
||||
* machine/setjmp.h: machine dependent setjmp-related information.
|
||||
* mips/setjmp.h: machine dependent setjmp-related information.
|
||||
*
|
||||
* For the size of this, refer to <machine/signal.h> as this uses the
|
||||
* struct sigcontext to restore it.
|
||||
*/
|
||||
|
||||
#define _JBLEN 87 /* size, in longs, of a jmp_buf */
|
||||
#ifndef __JBLEN
|
||||
#include <machine/pubassym.h>
|
||||
#endif
|
||||
|
||||
#define _JBLEN __JBLEN /* Size in longs of jmp_buf */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: signal.h,v 1.11 1998/09/14 02:48:34 thorpej Exp $ */
|
||||
/* $NetBSD: signal.h,v 1.12 1999/01/14 18:45:45 castor Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
@ -55,14 +55,16 @@ typedef int sig_atomic_t;
|
||||
* execution of the signal handler. It is also made available
|
||||
* to the handler to allow it to restore state properly if
|
||||
* a non-standard exit is performed.
|
||||
*
|
||||
* sizeof(sigcontext) = 45 * sizeof(int) + 35 * sizeof(mips_reg_t)
|
||||
*/
|
||||
#if defined(__LIBC12_SOURCE__) || defined(_KERNEL)
|
||||
struct sigcontext13 {
|
||||
int sc_onstack; /* sigstack state to restore */
|
||||
int sc_mask; /* signal mask to restore (old style) */
|
||||
int sc_pc; /* pc at time of signal */
|
||||
int sc_regs[32]; /* processor regs 0 to 31 */
|
||||
int mullo, mulhi; /* mullo and mulhi registers... */
|
||||
mips_reg_t sc_pc; /* pc at time of signal */
|
||||
mips_reg_t sc_regs[32]; /* processor regs 0 to 31 */
|
||||
mips_reg_t mullo, mulhi;/* mullo and mulhi registers... */
|
||||
int sc_fpused; /* fp has been used */
|
||||
int sc_fpregs[33]; /* fp regs 0 to 31 and csr */
|
||||
int sc_fpc_eir; /* floating point exception instruction reg */
|
||||
@ -73,9 +75,9 @@ struct sigcontext13 {
|
||||
struct sigcontext {
|
||||
int sc_onstack; /* sigstack state to restore */
|
||||
int __sc_mask13; /* signal mask to restore (old style) */
|
||||
int sc_pc; /* pc at time of signal */
|
||||
int sc_regs[32]; /* processor regs 0 to 31 */
|
||||
int mullo, mulhi; /* mullo and mulhi registers... */
|
||||
mips_reg_t sc_pc; /* pc at time of signal */
|
||||
mips_reg_t sc_regs[32]; /* processor regs 0 to 31 */
|
||||
mips_reg_t mullo, mulhi;/* mullo and mulhi registers... */
|
||||
int sc_fpused; /* fp has been used */
|
||||
int sc_fpregs[33]; /* fp regs 0 to 31 and csr */
|
||||
int sc_fpc_eir; /* floating point exception instruction reg */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: trap.h,v 1.11 1999/01/06 04:11:27 nisimura Exp $ */
|
||||
/* $NetBSD: trap.h,v 1.12 1999/01/14 18:45:45 castor Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1988 University of Utah.
|
||||
@ -71,11 +71,3 @@
|
||||
#define T_VCED 31 /* Virtual coherency data */
|
||||
|
||||
#define T_USER 0x20 /* user-mode flag or'ed with type */
|
||||
|
||||
|
||||
#ifdef DEBUG
|
||||
extern int cpu_singlestep __P((struct proc *));
|
||||
#endif
|
||||
#if defined(DEBUG) || defined(DDB)
|
||||
extern int kdbpeek __P((vaddr_t addr));
|
||||
#endif
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: types.h,v 1.17 1999/01/06 04:11:26 nisimura Exp $ */
|
||||
/* $NetBSD: types.h,v 1.18 1999/01/14 18:45:45 castor Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1992, 1993
|
||||
@ -43,18 +43,42 @@
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
/*
|
||||
* Note that mips_reg_t is distinct from the register_t defined
|
||||
* in <types.h> to allow these structures to be as hidden from
|
||||
* the rest of the operating system as possible.
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined(_MIPS_BSD_SIM) && _MIPS_BSD_SIM != _MIPS_SIM_ABI32
|
||||
typedef long long mips_reg_t;
|
||||
typedef unsigned long long mips_ureg_t;
|
||||
#if _MIPS_BSD_SIM != _MIPS_SIM_ABI32 && _MIPS_BSD_SIM != _MIPS_SIM_ABIX32
|
||||
typedef long long mips_fpreg_t;
|
||||
#else
|
||||
typedef int mips_fpreg_t;
|
||||
#endif
|
||||
#else
|
||||
typedef long mips_reg_t;
|
||||
typedef unsigned long mips_ureg_t;
|
||||
typedef long mips_fpreg_t;
|
||||
#endif
|
||||
|
||||
#if defined(_KERNEL)
|
||||
typedef struct label_t {
|
||||
int val[12];
|
||||
mips_reg_t val[12];
|
||||
} label_t;
|
||||
#endif
|
||||
|
||||
/* NB: This should probably be if defined(_KERNEL) */
|
||||
#if !defined(_POSIX_C_SOURCE) && !defined(_XOPEN_SOURCE)
|
||||
typedef unsigned long paddr_t;
|
||||
typedef unsigned long psize_t;
|
||||
typedef unsigned long vaddr_t;
|
||||
typedef unsigned long vsize_t;
|
||||
typedef unsigned long vm_offset_t;
|
||||
typedef unsigned long vm_size_t;
|
||||
|
||||
typedef vm_offset_t paddr_t;
|
||||
typedef vm_size_t psize_t;
|
||||
typedef vm_offset_t vaddr_t;
|
||||
typedef vm_size_t vsize_t;
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user