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Add defines for increasing SPL levels, assuming devices are wired up 

in to CPU interrupt pins in order of increasing priority.
This commit is contained in:
jonathan 1997-05-18 03:19:41 +00:00
parent 8d6f509439
commit ac99526674
1 changed files with 14 additions and 1 deletions
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15
sys/arch/mips/include/cpuregs.h
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@ -1,4 +1,4 @@
/* $NetBSD: cpuregs.h,v 1.5 1996/03/28 11:34:05 jonathan Exp $ */
/* $NetBSD: cpuregs.h,v 1.6 1997/05/18 03:19:41 jonathan Exp $ */
/*
* Copyright (c) 1992, 1993
@ -265,6 +265,19 @@
#define MACH_SOFT_INT_MASK_1 0x0200
#define MACH_SOFT_INT_MASK_0 0x0100
/*
* nesting interrupt masks.
*/
#define MACH_INT_MASK_SPL_SOFT0 MACH_SOFT_INT_MASK_0
#define MACH_INT_MASK_SPL_SOFT1 (MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_1)
#define MACH_INT_MASK_SPL0 (MACH_INT_MASK_0|MACH_INT_MASK_SPL_SOFT1)
#define MACH_INT_MASK_SPL1 (MACH_INT_MASK_1|MACH_INT_MASK_SPL0)
#define MACH_INT_MASK_SPL2 (MACH_INT_MASK_2|MACH_INT_MASK_SPL1)
#define MACH_INT_MASK_SPL3 (MACH_INT_MASK_3|MACH_INT_MASK_SPL2)
#define MACH_INT_MASK_SPL4 (MACH_INT_MASK_4|MACH_INT_MASK_SPL3)
#define MACH_INT_MASK_SPL5 (MACH_INT_MASK_5|MACH_INT_MASK_SPL4)
#ifdef pmax
#define MACH_INT_MASK MIPS_INT_MASK
#define MACH_HARD_INT_MASK MIPS_HARD_INT_MASK