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Set the PID before setting up the wired TLB entries for proc0. The 

mips3_HitFlushDCache() fails with a TLB miss otherwise.
This commit is contained in:
mhitch 1998-03-22 06:31:40 +00:00
parent 9db8ae93c8
commit a10657ae4f
1 changed files with 4 additions and 4 deletions
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8
sys/arch/mips/mips/mips_machdep.c
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@ -1,4 +1,4 @@
/* $NetBSD: mips_machdep.c,v 1.24 1998/03/12 05:45:06 thorpej Exp $ */
/* $NetBSD: mips_machdep.c,v 1.25 1998/03/22 06:31:40 mhitch Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@ -52,7 +52,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.24 1998/03/12 05:45:06 thorpej Exp $");
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.25 1998/03/22 06:31:40 mhitch Exp $");
#include "opt_uvm.h"
@ -1086,6 +1086,8 @@ mips_init_proc0(space)
pa = MIPS_KSEG0_TO_PHYS(proc0.p_addr);
MachSetPID(1);
if (CPUISMIPS3) {
for (i = 0; i < UPAGES; i += 2) {
tlb.tlb_mask = MIPS3_PG_SIZE_4K;
@ -1115,8 +1117,6 @@ mips_init_proc0(space)
}
}
MachSetPID(1);
nullproc.p_addr = (struct user *)(space + (UPAGES * PAGE_SIZE));
nullproc.p_md.md_regs = nullproc.p_addr->u_pcb.pcb_regs;