Add locore assembler functions to read mips3 cycle counter, and
read and write compare register (controls cycle-driven periodic interrupt).
Use cycle counter for microsecond time on mips3, but for now only on
3min motherboards (5000/150). the MAXINE baseboard microsecond
counter is more stable and I don't ave no 5000/260 to test.
XXX clkread() is a mess, it should be rewritten.
XXX should add nanotime() to give inkernel nanosecond resolution,
and then microtime() reworked to use nanotime().
This commit is contained in:
jonathan
parent
4ea6444493
commit
53c671e26c
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@ -1,4 +1,4 @@
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/* $NetBSD: locore_r4000.S,v 1.42 1998/03/12 05:45:06 thorpej Exp $ */
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/* $NetBSD: locore_r4000.S,v 1.43 1998/04/19 01:48:34 jonathan Exp $ */
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/*
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* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
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@ -2282,6 +2282,62 @@ NLEAF(mips3_cpu_switch_resume)
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li v0, 1 # possible return to 'savectx()'
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END(mips3_cpu_switch_resume)
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/*----------------------------------------------------------------------------
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*
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* mips3_cycle_count --
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*
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* u_int32_t mips3_cycle_count(void)
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*
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* read 32-bit cycle-counter clock in coprocessor 0.
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*
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* Results:
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* returns 32-bit clock value, incremented automatically by CPU
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* at nominal cycle rate (i.e., half the maximum issue rate.)
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*
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* Side effects:
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* none.
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*
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*----------------------------------------------------------------------------
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*/
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LEAF(mips3_cycle_count)
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mfc0 v0, MIPS_COP_0_COUNT
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nop
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nop
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j ra
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nop
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END(mips3_cycle_count)
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/*
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* Read compare register.
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*
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* On mips3, generates a hardint 5 interrupt request is generated
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* each time the COUNT register increments past the COMPARE register.
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*
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* (The mips interrupt mask defintions currently leaves this interrupt
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* unconditionally masked out on mips3 CPUs.)
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*/
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LEAF(mips3_read_compare)
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mfc0 v0, MIPS_COP_0_COMPARE
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nop
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j ra
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nop
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END(mips3_read_compare)
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/*
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* Write value to compare register.
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*
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* Side Effects:
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* Clears interrupt request from cycle-counter clock.
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*/
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LEAF(mips3_write_compare)
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mtc0 a0, MIPS_COP_0_COMPARE
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nop
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j ra
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nop
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END(mips3_write_compare)
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/*----------------------------------------------------------------------------
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*
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* XXX END of r4000-specific code XXX
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_3min.c,v 1.5 1998/03/30 06:45:37 jonathan Exp $ */
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/* $NetBSD: dec_3min.c,v 1.6 1998/04/19 01:48:35 jonathan Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -73,7 +73,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.5 1998/03/30 06:45:37 jonathan Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.6 1998/04/19 01:48:35 jonathan Exp $");
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#include <sys/types.h>
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@ -380,9 +380,16 @@ dec_3min_intr(mask, pc, statusReg, causeReg)
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kn02ba_errintr();
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if (intr & KMIN_INTR_CLOCK) {
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extern u_int32_t mips3_cycle_count __P((void));
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temp = c->regc; /* XXX clear interrupt bits */
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cf.pc = pc;
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cf.sr = statusReg;
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#ifdef MIPS3
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if (CPUISMIPS3) {
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latched_cycle_cnt = mips3_cycle_count();
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}
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#endif
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hardclock(&cf);
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intrcnt[HARDCLOCK]++;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.113 1998/03/31 11:32:52 jonathan Exp $ */
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/* $NetBSD: machdep.c,v 1.114 1998/04/19 01:48:35 jonathan Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -43,7 +43,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.113 1998/03/31 11:32:52 jonathan Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.114 1998/04/19 01:48:35 jonathan Exp $");
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/* from: Utah Hdr: machdep.c 1.63 91/04/24 */
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@ -857,6 +857,14 @@ clkread()
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register u_long usec, cycles; /* really 32 bits? */
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#endif
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#if defined(DEC_3MIN)
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if (systype == DS_3MIN && CPUISMIPS3) {
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extern u_int32_t mips3_cycle_count __P((void));
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register u_int32_t mips3_cycles =
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mips3_cycle_count() - (u_int32_t)latched_cycle_cnt;
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return ((mips3_cycles / cpu_mhz);
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else
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#endif
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#ifdef DEC_MAXINE
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if (systype == DS_MAXINE)
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return (*(u_long*)(MIPS_PHYS_TO_KSEG1(XINE_REG_FCTR)) -
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@ -972,6 +980,7 @@ initcpu()
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#endif
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}
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/*
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* Convert an ASCII string into an integer.
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*/
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