From 53c671e26ccda83ab83961286d953b00af470675 Mon Sep 17 00:00:00 2001
From: jonathan <jonathan@NetBSD.org>
Date: Sun, 19 Apr 1998 01:48:34 +0000
Subject: [PATCH] Add locore assembler functions to read mips3 cycle counter,
 and read and write compare register (controls cycle-driven periodic
 interrupt).

Use cycle counter for microsecond time on mips3, but for now only on
3min motherboards (5000/150).  the MAXINE baseboard microsecond
counter is more stable and I don't ave no 5000/260 to test.

XXX clkread() is a mess, it should be rewritten.
XXX should add nanotime() to give inkernel nanosecond resolution,
    and then microtime() reworked to use nanotime().
---
 sys/arch/mips/mips/locore_r4000.S | 58 ++++++++++++++++++++++++++++++-
 sys/arch/pmax/pmax/dec_3min.c     | 11 ++++--
 sys/arch/pmax/pmax/machdep.c      | 13 +++++--
 3 files changed, 77 insertions(+), 5 deletions(-)

diff --git a/sys/arch/mips/mips/locore_r4000.S b/sys/arch/mips/mips/locore_r4000.S
index 959e9c023762..7825d47b7644 100644
--- a/sys/arch/mips/mips/locore_r4000.S
+++ b/sys/arch/mips/mips/locore_r4000.S
@@ -1,4 +1,4 @@
-/*	$NetBSD: locore_r4000.S,v 1.42 1998/03/12 05:45:06 thorpej Exp $	*/
+/*	$NetBSD: locore_r4000.S,v 1.43 1998/04/19 01:48:34 jonathan Exp $	*/
 
 /*
  * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@@ -2282,6 +2282,62 @@ NLEAF(mips3_cpu_switch_resume)
 	li	v0, 1				# possible return to 'savectx()'
 END(mips3_cpu_switch_resume)
 
+
+/*----------------------------------------------------------------------------
+ *
+ * mips3_cycle_count --
+ *
+ *	u_int32_t mips3_cycle_count(void)
+ *
+ *	read 32-bit cycle-counter clock in coprocessor 0.
+ *
+ * Results:
+ *	returns 32-bit clock value, incremented automatically by CPU 
+ *	at nominal cycle rate (i.e., half the maximum issue rate.)
+ *
+ * Side effects:
+ *	none.
+ *
+ *----------------------------------------------------------------------------
+ */
+LEAF(mips3_cycle_count)
+	mfc0	v0,	MIPS_COP_0_COUNT
+	nop
+	nop
+	j	ra
+	nop
+END(mips3_cycle_count)
+
+/*
+ * Read compare register.
+ *
+ * On mips3, generates a hardint 5 interrupt request is generated
+ * each time the COUNT register increments past the COMPARE register.
+ *
+ * (The mips interrupt mask defintions currently leaves this interrupt
+ * unconditionally  masked out on mips3 CPUs.)
+ */
+LEAF(mips3_read_compare)
+	mfc0	v0,	MIPS_COP_0_COMPARE
+	nop
+	j	ra
+	nop
+END(mips3_read_compare)
+
+
+/*
+ * Write value to compare register.
+ *
+ * Side Effects:	
+ *	Clears interrupt request from cycle-counter clock.
+ */
+LEAF(mips3_write_compare)
+	mtc0	a0,	MIPS_COP_0_COMPARE
+	nop
+	j	ra
+	nop
+END(mips3_write_compare)
+
 /*----------------------------------------------------------------------------
  *
  *			XXX  END of r4000-specific code  XXX 
diff --git a/sys/arch/pmax/pmax/dec_3min.c b/sys/arch/pmax/pmax/dec_3min.c
index 05297e4c41b3..8c49b1109070 100644
--- a/sys/arch/pmax/pmax/dec_3min.c
+++ b/sys/arch/pmax/pmax/dec_3min.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: dec_3min.c,v 1.5 1998/03/30 06:45:37 jonathan Exp $	*/
+/*	$NetBSD: dec_3min.c,v 1.6 1998/04/19 01:48:35 jonathan Exp $	*/
 
 /*
  * Copyright (c) 1998 Jonathan Stone.  All rights reserved.
@@ -73,7 +73,7 @@
 
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
 
-__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.5 1998/03/30 06:45:37 jonathan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.6 1998/04/19 01:48:35 jonathan Exp $");
 
 
 #include <sys/types.h>
@@ -380,9 +380,16 @@ dec_3min_intr(mask, pc, statusReg, causeReg)
 			kn02ba_errintr();
 	
 		if (intr & KMIN_INTR_CLOCK) {
+			extern u_int32_t mips3_cycle_count __P((void));
+
 			temp = c->regc;	/* XXX clear interrupt bits */
 			cf.pc = pc;
 			cf.sr = statusReg;
+#ifdef MIPS3
+			if (CPUISMIPS3) {
+				latched_cycle_cnt = mips3_cycle_count();
+			}
+#endif
 			hardclock(&cf);
 			intrcnt[HARDCLOCK]++;
 		}
diff --git a/sys/arch/pmax/pmax/machdep.c b/sys/arch/pmax/pmax/machdep.c
index 5b2ac138285f..58097dbd93ef 100644
--- a/sys/arch/pmax/pmax/machdep.c
+++ b/sys/arch/pmax/pmax/machdep.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 1.113 1998/03/31 11:32:52 jonathan Exp $	*/
+/*	$NetBSD: machdep.c,v 1.114 1998/04/19 01:48:35 jonathan Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -43,7 +43,7 @@
 
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
 
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.113 1998/03/31 11:32:52 jonathan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.114 1998/04/19 01:48:35 jonathan Exp $");
 
 /* from: Utah Hdr: machdep.c 1.63 91/04/24 */
 
@@ -857,6 +857,14 @@ clkread()
 	register u_long usec, cycles;	/* really 32 bits? */
 #endif
 
+#if defined(DEC_3MIN)
+	if (systype == DS_3MIN && CPUISMIPS3) {
+		extern u_int32_t mips3_cycle_count __P((void));
+		register u_int32_t mips3_cycles =
+		    mips3_cycle_count() - (u_int32_t)latched_cycle_cnt;
+		return ((mips3_cycles / cpu_mhz);
+	else
+#endif
 #ifdef DEC_MAXINE
 	if (systype == DS_MAXINE)
 		return (*(u_long*)(MIPS_PHYS_TO_KSEG1(XINE_REG_FCTR)) -
@@ -972,6 +980,7 @@ initcpu()
 #endif
 }
 
+
 /*
  * Convert an ASCII string into an integer.
  */