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* Change Sprite MACH_xxx prefix to MIPS_xxx.

Browse Source 
* Use standard mips terminology (xxx_KSEG0, xxx_KSEG1) instead of the
  (more meaningful) Sprite names (xxx_CACHED, xxx_UNCACHED).
This commit is contained in:
jonathan 1997-06-22 07:42:25 +00:00
parent 3bdba8b419
commit 1f44934407
36 changed files with 1092 additions and 1085 deletions
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10
sys/arch/mips/include/cpu.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.21 1997/06/21 04:18:11 jonathan Exp $ */
/* $NetBSD: cpu.h,v 1.22 1997/06/22 07:42:48 jonathan Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -88,14 +88,14 @@ struct clockframe {
*/
/* mips1 versions */
#define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MACH_SR_KU_PREV)
#define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV)
#define MIPS1_CLKF_BASEPRI(framep) \
((~(framep)->sr & (MACH_INT_MASK | MACH_SR_INT_ENA_PREV)) == 0)
((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV)) == 0)
/* mips3 versions */
#define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MACH_SR_KSU_USER)
#define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER)
#define MIPS3_CLKF_BASEPRI(framep) \
((~(framep)->sr & (MACH_INT_MASK | MACH_SR_INT_ENAB)) == 0)
((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENAB)) == 0)
#define CLKF_PC(framep) ((framep)->pc)
#define CLKF_INTR(framep) (0)

367
sys/arch/mips/include/cpuregs.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpuregs.h,v 1.12 1997/06/22 03:17:40 jonathan Exp $ */
/* $NetBSD: cpuregs.h,v 1.13 1997/06/22 07:42:49 jonathan Exp $ */
/*
* Copyright (c) 1992, 1993
@ -60,24 +60,35 @@
#ifndef _MIPS_CPUREGS_H_
#define _MIPS_CPUREGS_H_
#define MACH_KUSEG_ADDR 0x0
#define MACH_CACHED_MEMORY_ADDR 0x80000000
#define MACH_UNCACHED_MEMORY_ADDR 0xa0000000
#define MACH_KSEG2_ADDR 0xc0000000
#define MACH_MAX_MEM_ADDR 0xbe000000
#define MACH_RESERVED_ADDR 0xbfc80000
/*
* Address space.
* 32-bit mips CPUS partition their 32-bit address space into four segments:
*
* kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
* kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
* kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
* kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
*
* mips1 physical memory is limited to 512Mbytes, which is
* doubly mapped in kseg0 (cached) and kseg1 (uncached.)
* Caching of mapped addresses is controlled by bits in the TLB entry.
*/
#define MACH_CACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
#define MACH_PHYS_TO_CACHED(x) ((unsigned)(x) | MACH_CACHED_MEMORY_ADDR)
#define MACH_UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
#define MACH_PHYS_TO_UNCACHED(x) ((unsigned)(x) | MACH_UNCACHED_MEMORY_ADDR)
#define MIPS_KUSEG_START 0x0
#define MIPS_KSEG0_START 0x80000000
#define MIPS_KSEG1_START 0xa0000000
#define MIPS_KSEG2_START 0xc0000000
#define MIPS_MAX_MEM_ADDR 0xbe000000
#define MIPS_RESERVED_ADDR 0xbfc80000
/* Map virtual address to index in r4k virtually-indexed cache */
#define MIPS_R4K_VA_TO_CINDEX(x) \
((unsigned)(x) & 0xffffff | MACH_CACHED_MEMORY_ADDR)
#define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
#define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START)
#define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
#define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START)
/* XXX compatibility with Pica port */
#define MACH_VA_TO_CINDEX(x) MIPS_R4K_VA_TO_CINDEX(x)
/* Map virtual address to index in mips3 r4k virtually-indexed cache */
#define MIPS3_VA_TO_CINDEX(x) \
((unsigned)(x) & 0xffffff | MIPS_KSEG0_START)
/*
@ -85,29 +96,29 @@
*
* Bits common to r3000 and r4000:
*
* MACH_CR_BR_DELAY Exception happened in branch delay slot.
* MACH_CR_COP_ERR Coprocessor error.
* MACH_CR_IP Interrupt pending bits defined below.
* MIPS_CR_BR_DELAY Exception happened in branch delay slot.
* MIPS_CR_COP_ERR Coprocessor error.
* MIPS_CR_IP Interrupt pending bits defined below.
* (same meaning as in CAUSE register).
* MACH_CR_EXC_CODE The exception type (see exception codes below).
* MIPS_CR_EXC_CODE The exception type (see exception codes below).
*
* Differences:
* r3k has 4 bits of execption type, r4k has 5 bits.
*/
#define MACH_CR_BR_DELAY 0x80000000
#define MACH_CR_COP_ERR 0x30000000
#define MIPS_CR_BR_DELAY 0x80000000
#define MIPS_CR_COP_ERR 0x30000000
#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */
#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
#define MACH_CR_IP 0x0000FF00
#define MACH_CR_EXC_CODE_SHIFT 2
#define MIPS_CR_IP 0x0000FF00
#define MIPS_CR_EXC_CODE_SHIFT 2
/*
* The bits in the status register. All bits are active when set to 1.
*
* R3000 status register fields:
* MACH_SR_CO_USABILITY Control the usability of the four coprocessors.
* MACH_SR_BOOT_EXC_VEC Use alternate exception vectors.
* MACH_SR_TLB_SHUTDOWN TLB disabled.
* MIPS_SR_CO_USABILITY Control the usability of the four coprocessors.
* MIPS_SR_BOOT_EXC_VEC Use alternate exception vectors.
* MIPS_SR_TLB_SHUTDOWN TLB disabled.
*
* MIPS_SR_INT_IE Master (current) interrupt enable bit.
*
@ -117,23 +128,23 @@
* r3k has a 3-entry stack of kernel/user bits, whereas the
* r4k has kernel/supervisor/user.
*/
#define MACH_SR_COP_USABILITY 0xf0000000
#define MACH_SR_COP_0_BIT 0x10000000
#define MACH_SR_COP_1_BIT 0x20000000
#define MIPS_SR_COP_USABILITY 0xf0000000
#define MIPS_SR_COP_0_BIT 0x10000000
#define MIPS_SR_COP_1_BIT 0x20000000
/* r4k and r3k differences, see below */
#define MACH_SR_BOOT_EXC_VEC 0x00400000
#define MACH_SR_TLB_SHUTDOWN 0x00200000
#define MIPS_SR_BOOT_EXC_VEC 0x00400000
#define MIPS_SR_TLB_SHUTDOWN 0x00200000
/* r4k and r3k differences, see below */
#define MIPS_SR_INT_IE 0x00000001
/*#define MACH_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
/*#define MACH_SR_INT_MASK 0x0000ff00*/
/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
/*#define MIPS_SR_INT_MASK 0x0000ff00*/
#define MACH_SR_INT_ENAB MIPS_SR_INT_IE /* backwards compatibility */
#define MACH_SR_INT_ENA_CUR MIPS_SR_INT_IE /* backwards compatibility */
#define MIPS_SR_INT_ENAB MIPS_SR_INT_IE /* backwards compatibility */
#define MIPS_SR_INT_ENA_CUR MIPS_SR_INT_IE /* backwards compatibility */
@ -141,17 +152,17 @@
* The R2000/R3000-specific status register bit definitions.
* all bits are active when set to 1.
*
* MACH_SR_PARITY_ERR Parity error.
* MACH_SR_CACHE_MISS Most recent D-cache load resulted in a miss.
* MACH_SR_PARITY_ZERO Zero replaces outgoing parity bits.
* MACH_SR_SWAP_CACHES Swap I-cache and D-cache.
* MACH_SR_ISOL_CACHES Isolate D-cache from main memory.
* MIPS_SR_PARITY_ERR Parity error.
* MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss.
* MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits.
* MIPS_SR_SWAP_CACHES Swap I-cache and D-cache.
* MIPS_SR_ISOL_CACHES Isolate D-cache from main memory.
* Interrupt enable bits defined below.
* MACH_SR_KU_OLD Old kernel/user mode bit. 1 => user mode.
* MACH_SR_INT_ENA_OLD Old interrupt enable bit.
* MACH_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode.
* MACH_SR_INT_ENA_PREV Previous interrupt enable bit.
* MACH_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
* MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode.
* MIPS_SR_INT_ENA_OLD Old interrupt enable bit.
* MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode.
* MIPS_SR_INT_ENA_PREV Previous interrupt enable bit.
* MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
*/
#define MIPS1_PARITY_ERR 0x00100000
@ -167,17 +178,17 @@
#define MIPS1_SR_KU_CUR 0x00000002 /* current KU */
/* backwards compatibility */
#define MACH_SR_PARITY_ERR MIPS1_PARITY_ERR
#define MACH_SR_CACHE_MISS MIPS1_CACHE_MISS
#define MACH_SR_PARITY_ZERO MIPS1_PARITY_ZERO
#define MACH_SR_SWAP_CACHES MIPS1_SWAP_CACHES
#define MACH_SR_ISOL_CACHES MIPS1_ISOL_CACHES
#define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR
#define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS
#define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO
#define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES
#define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES
#define MACH_SR_KU_OLD MIPS1_SR_KU_OLD
#define MACH_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD
#define MACH_SR_KU_PREV MIPS1_SR_KU_PREV
#define MACH_SR_KU_CUR MIPS1_SR_KU_CUR
#define MACH_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
#define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD
#define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD
#define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV
#define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR
#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
/*
* R4000 status register bit definitons,
@ -202,24 +213,24 @@
#define MIPS3_SR_EXL 0x00000002
/* backwards compatibility with names used in Pica port */
#define MACH_SR_RP MIPS3_SR_RP
#define MACH_SR_FR_32 MIPS3_SR_FR_32
#define MACH_SR_RE MIPS3_SR_RE
#define MIPS_SR_RP MIPS3_SR_RP
#define MIPS_SR_FR_32 MIPS3_SR_FR_32
#define MIPS_SR_RE MIPS3_SR_RE
#define MACH_SR_SOFT_RESET MIPS3_SR_SOFT_RESET
#define MACH_SR_DIAG_CH MIPS3_SR_DIAG_CH
#define MACH_SR_DIAG_CE MIPS3_SR_DIAG_CE
#define MACH_SR_DIAG_PE MIPS3_SR_DIAG_PE
#define MACH_SR_KX MIPS3_SR_KX
#define MACH_SR_SX MIPS3_SR_SX
#define MACH_SR_UX MIPS3_SR_UX
#define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET
#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH
#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE
#define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE
#define MIPS_SR_KX MIPS3_SR_KX
#define MIPS_SR_SX MIPS3_SR_SX
#define MIPS_SR_UX MIPS3_SR_UX
#define MACH_SR_KSU_MASK MIPS3_SR_KSU_MASK
#define MACH_SR_KSU_USER MIPS3_SR_KSU_USER
#define MACH_SR_KSU_SUPER MIPS3_SR_KSU_SUPER
#define MACH_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL
#define MACH_SR_ERL MIPS3_SR_ERL
#define MACH_SR_EXL MIPS3_SR_EXL
#define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK
#define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER
#define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER
#define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL
#define MIPS_SR_ERL MIPS3_SR_ERL
#define MIPS_SR_EXL MIPS3_SR_EXL
/*
@ -227,34 +238,34 @@
* If a bit in the mask is 1 then the interrupt is enabled (or pending).
*/
#define MIPS_INT_MASK 0xff00
#define MACH_INT_MASK_5 0x8000
#define MACH_INT_MASK_4 0x4000
#define MACH_INT_MASK_3 0x2000
#define MACH_INT_MASK_2 0x1000
#define MACH_INT_MASK_1 0x0800
#define MACH_INT_MASK_0 0x0400
#define MIPS_INT_MASK_5 0x8000
#define MIPS_INT_MASK_4 0x4000
#define MIPS_INT_MASK_3 0x2000
#define MIPS_INT_MASK_2 0x1000
#define MIPS_INT_MASK_1 0x0800
#define MIPS_INT_MASK_0 0x0400
#define MIPS_HARD_INT_MASK 0xfc00
#define MACH_SOFT_INT_MASK_1 0x0200
#define MACH_SOFT_INT_MASK_0 0x0100
#define MIPS_SOFT_INT_MASK_1 0x0200
#define MIPS_SOFT_INT_MASK_0 0x0100
/*
* nesting interrupt masks.
*/
#define MACH_INT_MASK_SPL_SOFT0 MACH_SOFT_INT_MASK_0
#define MACH_INT_MASK_SPL_SOFT1 (MACH_SOFT_INT_MASK_1|MACH_INT_MASK_SPL_SOFT0)
#define MACH_INT_MASK_SPL0 (MACH_INT_MASK_0|MACH_INT_MASK_SPL_SOFT1)
#define MACH_INT_MASK_SPL1 (MACH_INT_MASK_1|MACH_INT_MASK_SPL0)
#define MACH_INT_MASK_SPL2 (MACH_INT_MASK_2|MACH_INT_MASK_SPL1)
#define MACH_INT_MASK_SPL3 (MACH_INT_MASK_3|MACH_INT_MASK_SPL2)
#define MACH_INT_MASK_SPL4 (MACH_INT_MASK_4|MACH_INT_MASK_SPL3)
#define MACH_INT_MASK_SPL5 (MACH_INT_MASK_5|MACH_INT_MASK_SPL4)
#define MIPS_INT_MASK_SPL_SOFT0 MIPS_SOFT_INT_MASK_0
#define MIPS_INT_MASK_SPL_SOFT1 (MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0)
#define MIPS_INT_MASK_SPL0 (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1)
#define MIPS_INT_MASK_SPL1 (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0)
#define MIPS_INT_MASK_SPL2 (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1)
#define MIPS_INT_MASK_SPL3 (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2)
#define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3)
#define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4)
/*
* mips3 CPUs have on-chip timer at INT_MASK_5. We don't support it yet.
*/
#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MACH_INT_MASK_5)
#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MACH_INT_MASK_5)
#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
/*
@ -271,8 +282,8 @@
*
* Common vectors: reset and UTLB miss.
*/
#define MACH_RESET_EXC_VEC 0xBFC00000
#define MACH_UTLB_MISS_EXC_VEC 0x80000000
#define MIPS_RESET_EXC_VEC 0xBFC00000
#define MIPS_UTLB_MISS_EXC_VEC 0x80000000
/*
* R3000 general exception vector (everything else)
@ -289,116 +300,116 @@
/*
* Coprocessor 0 registers:
*
* MACH_COP_0_TLB_INDEX TLB index.
* MACH_COP_0_TLB_RANDOM TLB random.
* MACH_COP_0_TLB_LOW r3k TLB entry low.
* MACH_COP_0_TLB_LO0 r4k TLB entry low.
* MACH_COP_0_TLB_LO1 r4k TLB entry low, extended.
* MACH_COP_0_TLB_CONTEXT TLB context.
* MACH_COP_0_BAD_VADDR Bad virtual address.
* MACH_COP_0_TLB_HI TLB entry high.
* MACH_COP_0_STATUS_REG Status register.
* MACH_COP_0_CAUSE_REG Exception cause register.
* MACH_COP_0_EXC_PC Exception PC.
* MACH_COP_0_PRID Processor revision identifier.
* MIPS_COP_0_TLB_INDEX TLB index.
* MIPS_COP_0_TLB_RANDOM TLB random.
* MIPS_COP_0_TLB_LOW r3k TLB entry low.
* MIPS_COP_0_TLB_LO0 r4k TLB entry low.
* MIPS_COP_0_TLB_LO1 r4k TLB entry low, extended.
* MIPS_COP_0_TLB_CONTEXT TLB context.
* MIPS_COP_0_BAD_VADDR Bad virtual address.
* MIPS_COP_0_TLB_HI TLB entry high.
* MIPS_COP_0_STATUS_REG Status register.
* MIPS_COP_0_CAUSE_REG Exception cause register.
* MIPS_COP_0_EXC_PC Exception PC.
* MIPS_COP_0_PRID Processor revision identifier.
*/
#define MACH_COP_0_TLB_INDEX $0
#define MACH_COP_0_TLB_RANDOM $1
#define MIPS_COP_0_TLB_INDEX $0
#define MIPS_COP_0_TLB_RANDOM $1
/* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
#define MACH_COP_0_TLB_CONTEXT $4
#define MIPS_COP_0_TLB_CONTEXT $4
/* $5 and $6 new with MIPS-III */
#define MACH_COP_0_BAD_VADDR $8
#define MACH_COP_0_TLB_HI $10
#define MACH_COP_0_STATUS_REG $12
#define MACH_COP_0_CAUSE_REG $13
#define MACH_COP_0_EXC_PC $14
#define MACH_COP_0_PRID $15
#define MIPS_COP_0_BAD_VADDR $8
#define MIPS_COP_0_TLB_HI $10
#define MIPS_COP_0_STATUS_REG $12
#define MIPS_COP_0_CAUSE_REG $13
#define MIPS_COP_0_EXC_PC $14
#define MIPS_COP_0_PRID $15
/* r3k-specific */
#define MACH_COP_0_TLB_LOW $2
#define MIPS_COP_0_TLB_LOW $2
/* MIPS-III additions */
#define MACH_COP_0_TLB_LO0 $2
#define MACH_COP_0_TLB_LO1 $3
#define MIPS_COP_0_TLB_LO0 $2
#define MIPS_COP_0_TLB_LO1 $3
#define MACH_COP_0_TLB_PG_MASK $5
#define MACH_COP_0_TLB_WIRED $6
#define MIPS_COP_0_TLB_PG_MASK $5
#define MIPS_COP_0_TLB_WIRED $6
#define MACH_COP_0_CONFIG $16
#define MACH_COP_0_LLADDR $17
#define MACH_COP_0_WATCH_LO $18
#define MACH_COP_0_WATCH_HI $19
#define MACH_COP_0_TLB_XCONTEXT $20
#define MACH_COP_0_ECC $26
#define MACH_COP_0_CACHE_ERR $27
#define MACH_COP_0_TAG_LO $28
#define MACH_COP_0_TAG_HI $29
#define MACH_COP_0_ERROR_PC $30
#define MIPS_COP_0_CONFIG $16
#define MIPS_COP_0_LLADDR $17
#define MIPS_COP_0_WATCH_LO $18
#define MIPS_COP_0_WATCH_HI $19
#define MIPS_COP_0_TLB_XCONTEXT $20
#define MIPS_COP_0_ECC $26
#define MIPS_COP_0_CACHE_ERR $27
#define MIPS_COP_0_TAG_LO $28
#define MIPS_COP_0_TAG_HI $29
#define MIPS_COP_0_ERROR_PC $30
/*
* Values for the code field in a break instruction.
*/
#define MACH_BREAK_INSTR 0x0000000d
#define MACH_BREAK_VAL_MASK 0x03ff0000
#define MACH_BREAK_VAL_SHIFT 16
#define MACH_BREAK_KDB_VAL 512
#define MACH_BREAK_SSTEP_VAL 513
#define MACH_BREAK_BRKPT_VAL 514
#define MACH_BREAK_SOVER_VAL 515
#define MACH_BREAK_KDB (MACH_BREAK_INSTR | \
(MACH_BREAK_KDB_VAL << MACH_BREAK_VAL_SHIFT))
#define MACH_BREAK_SSTEP (MACH_BREAK_INSTR | \
(MACH_BREAK_SSTEP_VAL << MACH_BREAK_VAL_SHIFT))
#define MACH_BREAK_BRKPT (MACH_BREAK_INSTR | \
(MACH_BREAK_BRKPT_VAL << MACH_BREAK_VAL_SHIFT))
#define MACH_BREAK_SOVER (MACH_BREAK_INSTR | \
(MACH_BREAK_SOVER_VAL << MACH_BREAK_VAL_SHIFT))
#define MIPS_BREAK_INSTR 0x0000000d
#define MIPS_BREAK_VAL_MASK 0x03ff0000
#define MIPS_BREAK_VAL_SHIFT 16
#define MIPS_BREAK_KDB_VAL 512
#define MIPS_BREAK_SSTEP_VAL 513
#define MIPS_BREAK_BRKPT_VAL 514
#define MIPS_BREAK_SOVER_VAL 515
#define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \
(MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
#define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \
(MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
#define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \
(MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
#define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \
(MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
/*
* Mininum and maximum cache sizes.
*/
#define MACH_MIN_CACHE_SIZE (16 * 1024)
#define MACH_MAX_CACHE_SIZE (256 * 1024)
#define MIPS_MIN_CACHE_SIZE (16 * 1024)
#define MIPS_MAX_CACHE_SIZE (256 * 1024)
/*
* The floating point version and status registers.
*/
#define MACH_FPC_ID $0
#define MACH_FPC_CSR $31
#define MIPS_FPU_ID $0
#define MIPS_FPU_CSR $31
/*
* The floating point coprocessor status register bits.
*/
#define MACH_FPC_ROUNDING_BITS 0x00000003
#define MACH_FPC_ROUND_RN 0x00000000
#define MACH_FPC_ROUND_RZ 0x00000001
#define MACH_FPC_ROUND_RP 0x00000002
#define MACH_FPC_ROUND_RM 0x00000003
#define MACH_FPC_STICKY_BITS 0x0000007c
#define MACH_FPC_STICKY_INEXACT 0x00000004
#define MACH_FPC_STICKY_UNDERFLOW 0x00000008
#define MACH_FPC_STICKY_OVERFLOW 0x00000010
#define MACH_FPC_STICKY_DIV0 0x00000020
#define MACH_FPC_STICKY_INVALID 0x00000040
#define MACH_FPC_ENABLE_BITS 0x00000f80
#define MACH_FPC_ENABLE_INEXACT 0x00000080
#define MACH_FPC_ENABLE_UNDERFLOW 0x00000100
#define MACH_FPC_ENABLE_OVERFLOW 0x00000200
#define MACH_FPC_ENABLE_DIV0 0x00000400
#define MACH_FPC_ENABLE_INVALID 0x00000800
#define MACH_FPC_EXCEPTION_BITS 0x0003f000
#define MACH_FPC_EXCEPTION_INEXACT 0x00001000
#define MACH_FPC_EXCEPTION_UNDERFLOW 0x00002000
#define MACH_FPC_EXCEPTION_OVERFLOW 0x00004000
#define MACH_FPC_EXCEPTION_DIV0 0x00008000
#define MACH_FPC_EXCEPTION_INVALID 0x00010000
#define MACH_FPC_EXCEPTION_UNIMPL 0x00020000
#define MACH_FPC_COND_BIT 0x00800000
#define MACH_FPC_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
#define MIPS_FPU_ROUNDING_BITS 0x00000003
#define MIPS_FPU_ROUND_RN 0x00000000
#define MIPS_FPU_ROUND_RZ 0x00000001
#define MIPS_FPU_ROUND_RP 0x00000002
#define MIPS_FPU_ROUND_RM 0x00000003
#define MIPS_FPU_STICKY_BITS 0x0000007c
#define MIPS_FPU_STICKY_INEXACT 0x00000004
#define MIPS_FPU_STICKY_UNDERFLOW 0x00000008
#define MIPS_FPU_STICKY_OVERFLOW 0x00000010
#define MIPS_FPU_STICKY_DIV0 0x00000020
#define MIPS_FPU_STICKY_INVALID 0x00000040
#define MIPS_FPU_ENABLE_BITS 0x00000f80
#define MIPS_FPU_ENABLE_INEXACT 0x00000080
#define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100
#define MIPS_FPU_ENABLE_OVERFLOW 0x00000200
#define MIPS_FPU_ENABLE_DIV0 0x00000400
#define MIPS_FPU_ENABLE_INVALID 0x00000800
#define MIPS_FPU_EXCEPTION_BITS 0x0003f000
#define MIPS_FPU_EXCEPTION_INEXACT 0x00001000
#define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000
#define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000
#define MIPS_FPU_EXCEPTION_DIV0 0x00008000
#define MIPS_FPU_EXCEPTION_INVALID 0x00010000
#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
#define MIPS_FPU_COND_BIT 0x00800000
#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
#define MIPS1_FPC_MBZ_BITS 0xff7c0000
#define MIPS3_FPC_MBZ_BITS 0xfe7c0000
@ -406,8 +417,8 @@
/*
* Constants to determine if have a floating point instruction.
*/
#define MACH_OPCODE_SHIFT 26
#define MACH_OPCODE_C1 0x11
#define MIPS_OPCODE_SHIFT 26
#define MIPS_OPCODE_C1 0x11
@ -475,23 +486,17 @@
*/
#if defined(MIPS3) && !defined(MIPS1)
#define MACH_INT_MASK MIPS3_INT_MASK
#define MACH_HARD_INT_MASK MIPS3_HARD_INT_MASK
#define MIPS_TLB_PID_SHIFT MIPS3_TLB_PID_SHIFT
#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_PIDS
#endif
#if !defined(MIPS3) && defined(MIPS1)
#define MACH_INT_MASK MIPS_INT_MASK
#define MACH_HARD_INT_MASK MIPS_HARD_INT_MASK
#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
#endif
#if defined(MIPS1) && defined(MIPS3)
#define MACH_INT_MASK MIPS_INT_MASK /* XXX */
#define MACH_HARD_INT_MASK MIPS_HARD_INT_MASK /* XXX */
#define MIPS_TLB_PID_SHIFT \
((CPUISMIPS3)? MIPS3_TLB_PID_SHIFT : MIPS1_TLB_PID_SHIFT)

6
sys/arch/mips/include/kdbparam.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: kdbparam.h,v 1.4 1994/10/26 21:09:42 cgd Exp $ */
/* $NetBSD: kdbparam.h,v 1.5 1997/06/22 07:42:50 jonathan Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -52,13 +52,13 @@
#define LPRMODE "%R"
#define OFFMODE "+%R"
#define SETBP(ins) MACH_BREAK_BRKPT
#define SETBP(ins) MIPS_BREAK_BRKPT
/* return the program counter value modified if we are in a delay slot */
#define kdbgetpc(pcb) (kdbvar[kdbvarchk('t')] < 0 ? \
(pcb).pcb_regs[34] + 4 : (pcb).pcb_regs[34])
#define kdbishiddenreg(p) ((p) >= &kdbreglist[33])
#define kdbisbreak(type) (((type) & MACH_CR_EXC_CODE) == 0x24)
#define kdbisbreak(type) (((type) & MIPS_CR_EXC_CODE) == 0x24)
/* check for address wrap around */
#define kdbaddrwrap(addr,newaddr) (((addr)^(newaddr)) >> 31)

46
sys/arch/mips/include/psl.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: psl.h,v 1.7 1997/06/21 04:18:13 jonathan Exp $ */
/* $NetBSD: psl.h,v 1.8 1997/06/22 07:42:52 jonathan Exp $ */
/*
* Copyright (c) 1992, 1993
@ -58,24 +58,24 @@
MIPS3_INT_MASK)
#define MIPS3_PSL_USERCLR \
(MACH_SR_COP_USABILITY |\
MACH_SR_BOOT_EXC_VEC | \
MACH_SR_TLB_SHUTDOWN | \
MACH_SR_PARITY_ERR | \
MACH_SR_CACHE_MISS | \
MACH_SR_PARITY_ZERO | \
MACH_SR_SWAP_CACHES | \
MACH_SR_ISOL_CACHES | \
MACH_SR_KU_CUR | \
(MIPS_SR_COP_USABILITY |\
MIPS_SR_BOOT_EXC_VEC | \
MIPS_SR_TLB_SHUTDOWN | \
MIPS_SR_PARITY_ERR | \
MIPS_SR_CACHE_MISS | \
MIPS_SR_PARITY_ZERO | \
MIPS_SR_SWAP_CACHES | \
MIPS_SR_ISOL_CACHES | \
MIPS_SR_KU_CUR | \
MIPS_SR_INT_IE | \
MACH_SR_MBZ)
MIPS_SR_MBZ)
#define MIPS3_USERMODE(ps) \
(((ps) & MIPS3_SR_KSU_MASK) == MIPS3_SR_KSU_USER)
#define MIPS3_BASEPRI(ps) \
(((ps) & (MIPS3_INT_MASK | MACH_SR_INT_ENA_PREV)) \
== (MIPS3_INT_MASK | MACH_SR_INT_ENA_PREV))
(((ps) & (MIPS3_INT_MASK | MIPS_SR_INT_ENA_PREV)) \
== (MIPS3_INT_MASK | MIPS_SR_INT_ENA_PREV))
/*
@ -91,17 +91,17 @@
MIPS_INT_MASK)
#define MIPS1_PSL_USERCLR \
(MACH_SR_COP_USABILITY |\
MACH_SR_BOOT_EXC_VEC | \
MACH_SR_TLB_SHUTDOWN | \
MACH_SR_PARITY_ERR | \
MACH_SR_CACHE_MISS | \
MACH_SR_PARITY_ZERO | \
MACH_SR_SWAP_CACHES | \
MACH_SR_ISOL_CACHES | \
MACH_SR_KU_CUR | \
(MIPS_SR_COP_USABILITY |\
MIPS_SR_BOOT_EXC_VEC | \
MIPS_SR_TLB_SHUTDOWN | \
MIPS_SR_PARITY_ERR | \
MIPS_SR_CACHE_MISS | \
MIPS_SR_PARITY_ZERO | \
MIPS_SR_SWAP_CACHES | \
MIPS_SR_ISOL_CACHES | \
MIPS_SR_KU_CUR | \
MIPS_SR_INT_IE | \
MACH_SR_MBZ)
MIPS_SR_MBZ)
#define MIPS1_USERMODE(ps) \
((ps) & MIPS1_SR_KU_PREV)

212
sys/arch/mips/mips/fp.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: fp.S,v 1.9 1997/06/16 01:24:05 jonathan Exp $ */
/* $NetBSD: fp.S,v 1.10 1997/06/22 07:42:54 jonathan Exp $ */
/*
* Copyright (c) 1992, 1993
@ -110,10 +110,10 @@ NON_LEAF(MachEmulateFP, STAND_FRAME_SIZE, ra)
bgt v0, 4 << 2, ill # illegal format
or v1, v1, v0
cfc1 a1, MACH_FPC_CSR # get exception register
cfc1 a1, MIPS_FPU_CSR # get exception register
lw a3, func_fmt_tbl(v1) # switch on FUNC & FMT
and a1, a1, ~MACH_FPC_EXCEPTION_UNIMPL # clear exception
ctc1 a1, MACH_FPC_CSR
and a1, a1, ~MIPS_FPU_EXCEPTION_UNIMPL # clear exception
ctc1 a1, MIPS_FPU_CSR
j a3
.rdata
@ -668,8 +668,8 @@ add_sub_s:
3:
bne t5, zero, result_ft_s # if FT != 0, result=FT
bne t6, zero, result_ft_s
and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode
bne v0, MACH_FPC_ROUND_RM, 1f # round to -infinity?
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity?
or t0, t0, t4 # compute result sign
b result_fs_s
1:
@ -727,8 +727,8 @@ add_sub_s:
bne t2, t6, 2f # if same, result=0
move t1, zero # result=0
move t2, zero
and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode
bne v0, MACH_FPC_ROUND_RM, 1f # round to -infinity?
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity?
or t0, t0, t4 # compute result sign
b result_fs_s
1:
@ -791,8 +791,8 @@ add_sub_d:
bne t5, zero, result_ft_d # if FT != 0, result=FT
bne t6, zero, result_ft_d
bne t7, zero, result_ft_d
and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode
bne v0, MACH_FPC_ROUND_RM, 1f # round to -infinity?
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity?
or t0, t0, t4 # compute result sign
b result_fs_d
1:
@ -885,8 +885,8 @@ add_sub_d:
move t1, zero # result=0
move t2, zero
move t3, zero
and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode
bne v0, MACH_FPC_ROUND_RM, 1f # round to -infinity?
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity?
or t0, t0, t4 # compute result sign
b result_fs_d
1:
@ -1081,10 +1081,10 @@ div_s:
3:
bne t5, zero, 2f # is FT zero?
bne t6, zero, 1f
or a1, a1, MACH_FPC_EXCEPTION_DIV0 | MACH_FPC_STICKY_DIV0
and v0, a1, MACH_FPC_ENABLE_DIV0 # trap enabled?
or a1, a1, MIPS_FPU_EXCEPTION_DIV0 | MIPS_FPU_STICKY_DIV0
and v0, a1, MIPS_FPU_ENABLE_DIV0 # trap enabled?
bne v0, zero, fpe_trap
ctc1 a1, MACH_FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
li t1, SEXP_INF # result is infinity
move t2, zero
b result_fs_s
@ -1155,10 +1155,10 @@ div_d:
bne t5, zero, 2f # is FT zero?
bne t6, zero, 1f
bne t7, zero, 1f
or a1, a1, MACH_FPC_EXCEPTION_DIV0 | MACH_FPC_STICKY_DIV0
and v0, a1, MACH_FPC_ENABLE_DIV0 # trap enabled?
or a1, a1, MIPS_FPU_EXCEPTION_DIV0 | MIPS_FPU_STICKY_DIV0
and v0, a1, MIPS_FPU_ENABLE_DIV0 # trap enabled?
bne v0, zero, fpe_trap
ctc1 a1, MACH_FPC_CSR # Save exceptions
ctc1 a1, MIPS_FPU_CSR # Save exceptions
li t1, DEXP_INF # result is infinity
move t2, zero
move t3, zero
@ -1507,10 +1507,10 @@ cvt_w:
* round result (t0 is sign, t2 is integer part, t3 is fractional part).
*/
2:
and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode
beq v0, MACH_FPC_ROUND_RN, 3f # round to nearest
beq v0, MACH_FPC_ROUND_RZ, 5f # round to zero (truncate)
beq v0, MACH_FPC_ROUND_RP, 1f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
beq t0, zero, 5f # if sign is positive, truncate
b 2f
1:
@ -1539,10 +1539,10 @@ cvt_w:
* Handle inexact exception.
*/
inexact_w:
or a1, a1, MACH_FPC_EXCEPTION_INEXACT | MACH_FPC_STICKY_INEXACT
and v0, a1, MACH_FPC_ENABLE_INEXACT
or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
and v0, a1, MIPS_FPU_ENABLE_INEXACT
bne v0, zero, fpe_trap
ctc1 a1, MACH_FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
b result_fs_w
/*
@ -1551,10 +1551,10 @@ inexact_w:
* or generate an invalid exception.
*/
overflow_w:
or a1, a1, MACH_FPC_EXCEPTION_OVERFLOW | MACH_FPC_STICKY_OVERFLOW
and v0, a1, MACH_FPC_ENABLE_OVERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW
and v0, a1, MIPS_FPU_ENABLE_OVERFLOW
bne v0, zero, fpe_trap
and v0, a1, MACH_FPC_ENABLE_INEXACT
and v0, a1, MIPS_FPU_ENABLE_INEXACT
bne v0, zero, inexact_w # inexact traps enabled?
b invalid_w
@ -1564,10 +1564,10 @@ overflow_w:
* or generate an invalid exception.
*/
underflow_w:
or a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW
and v0, a1, MACH_FPC_ENABLE_UNDERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
and v0, a1, MIPS_FPU_ENABLE_UNDERFLOW
bne v0, zero, fpe_trap
and v0, a1, MACH_FPC_ENABLE_INEXACT
and v0, a1, MIPS_FPU_ENABLE_INEXACT
bne v0, zero, inexact_w # inexact traps enabled?
b invalid_w
@ -1643,29 +1643,29 @@ test_cond:
and v0, v0, a0 # condition match instruction?
set_cond:
bne v0, zero, 1f
and a1, a1, ~MACH_FPC_COND_BIT # clear condition bit
and a1, a1, ~MIPS_FPU_COND_BIT # clear condition bit
b 2f
1:
or a1, a1, MACH_FPC_COND_BIT # set condition bit
or a1, a1, MIPS_FPU_COND_BIT # set condition bit
2:
ctc1 a1, MACH_FPC_CSR # save condition bit
ctc1 a1, MIPS_FPU_CSR # save condition bit
b done
unordered:
and v0, a0, COND_UNORDERED # this cmp match unordered?
bne v0, zero, 1f
and a1, a1, ~MACH_FPC_COND_BIT # clear condition bit
and a1, a1, ~MIPS_FPU_COND_BIT # clear condition bit
b 2f
1:
or a1, a1, MACH_FPC_COND_BIT # set condition bit
or a1, a1, MIPS_FPU_COND_BIT # set condition bit
2:
and v0, a0, COND_SIGNAL
beq v0, zero, 1f # is this a signaling cmp?
or a1, a1, MACH_FPC_EXCEPTION_INVALID | MACH_FPC_STICKY_INVALID
and v0, a1, MACH_FPC_ENABLE_INVALID
or a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
and v0, a1, MIPS_FPU_ENABLE_INVALID
bne v0, zero, fpe_trap
1:
ctc1 a1, MACH_FPC_CSR # save condition bit
ctc1 a1, MIPS_FPU_CSR # save condition bit
b done
/*
@ -1730,10 +1730,10 @@ norm_s:
norm_noshift_s:
move t5, t1 # save unrounded exponent
move t6, t2 # save unrounded fraction
and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode
beq v0, MACH_FPC_ROUND_RN, 3f # round to nearest
beq v0, MACH_FPC_ROUND_RZ, 5f # round to zero (truncate)
beq v0, MACH_FPC_ROUND_RP, 1f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
beq t0, zero, 5f # if sign is positive, truncate
b 2f
1:
@ -1773,10 +1773,10 @@ inexact_s:
and t2, t2, ~SIMPL_ONE # clear implied one bit
inexact_nobias_s:
jal _C_LABEL(set_fd_s) # save result
or a1, a1, MACH_FPC_EXCEPTION_INEXACT | MACH_FPC_STICKY_INEXACT
and v0, a1, MACH_FPC_ENABLE_INEXACT
or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
and v0, a1, MIPS_FPU_ENABLE_INEXACT
bne v0, zero, fpe_trap
ctc1 a1, MACH_FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
b done
/*
@ -1785,18 +1785,18 @@ inexact_nobias_s:
* or generate an infinity.
*/
overflow_s:
or a1, a1, MACH_FPC_EXCEPTION_OVERFLOW | MACH_FPC_STICKY_OVERFLOW
and v0, a1, MACH_FPC_ENABLE_OVERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW
and v0, a1, MIPS_FPU_ENABLE_OVERFLOW
beq v0, zero, 1f
subu t1, t1, 192 # bias exponent
and t2, t2, ~SIMPL_ONE # clear implied one bit
jal _C_LABEL(set_fd_s) # save result
b fpe_trap
1:
and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode
beq v0, MACH_FPC_ROUND_RN, 3f # round to nearest
beq v0, MACH_FPC_ROUND_RZ, 1f # round to zero (truncate)
beq v0, MACH_FPC_ROUND_RP, 2f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, 1f # round to zero (truncate)
beq v0, MIPS_FPU_ROUND_RP, 2f # round to +infinity
bne t0, zero, 3f
1:
li t1, SEXP_MAX # result is max finite
@ -1814,7 +1814,7 @@ overflow_s:
* "loss of accuracy" is detected as "an inexact result".
*/
underflow_s:
and v0, a1, MACH_FPC_ENABLE_UNDERFLOW
and v0, a1, MIPS_FPU_ENABLE_UNDERFLOW
beq v0, zero, 1f
/*
* Underflow is enabled so compute the result and trap.
@ -1822,7 +1822,7 @@ underflow_s:
addu t1, t1, 192 # bias exponent
and t2, t2, ~SIMPL_ONE # clear implied one bit
jal _C_LABEL(set_fd_s) # save result
or a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
b fpe_trap
/*
* Underflow is not enabled so compute the result,
@ -1836,15 +1836,15 @@ underflow_s:
blt t9, SFRAC_BITS+2, 3f # shift all the bits out?
move t1, zero # result is inexact zero
move t2, zero
or a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
/*
* Now round the zero result.
* Only need to worry about rounding to +- infinity when the sign matches.
*/
and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode
beq v0, MACH_FPC_ROUND_RN, inexact_nobias_s # round to nearest
beq v0, MACH_FPC_ROUND_RZ, inexact_nobias_s # round to zero
beq v0, MACH_FPC_ROUND_RP, 1f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, inexact_nobias_s # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, inexact_nobias_s # round to zero
beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
beq t0, zero, inexact_nobias_s # if sign is positive, truncate
b 2f
1:
@ -1862,10 +1862,10 @@ underflow_s:
/*
* Now round the denormalized result.
*/
and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode
beq v0, MACH_FPC_ROUND_RN, 3f # round to nearest
beq v0, MACH_FPC_ROUND_RZ, 5f # round to zero (truncate)
beq v0, MACH_FPC_ROUND_RP, 1f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
beq t0, zero, 5f # if sign is positive, truncate
b 2f
1:
@ -1887,11 +1887,11 @@ underflow_s:
move t1, zero # denorm or zero exponent
jal _C_LABEL(set_fd_s) # save result
beq t8, zero, done # check for exact result
or a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW
or a1, a1, MACH_FPC_EXCEPTION_INEXACT | MACH_FPC_STICKY_INEXACT
and v0, a1, MACH_FPC_ENABLE_INEXACT
or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
and v0, a1, MIPS_FPU_ENABLE_INEXACT
bne v0, zero, fpe_trap
ctc1 a1, MACH_FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
b done
/*
@ -1976,10 +1976,10 @@ norm_noshift_d:
move t5, t1 # save unrounded exponent
move t6, t2 # save unrounded fraction (MS)
move t7, t3 # save unrounded fraction (LS)
and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode
beq v0, MACH_FPC_ROUND_RN, 3f # round to nearest
beq v0, MACH_FPC_ROUND_RZ, 5f # round to zero (truncate)
beq v0, MACH_FPC_ROUND_RP, 1f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
beq t0, zero, 5f # if sign is positive, truncate
b 2f
1:
@ -2023,10 +2023,10 @@ inexact_d:
and t2, t2, ~DIMPL_ONE # clear implied one bit
inexact_nobias_d:
jal _C_LABEL(set_fd_d) # save result
or a1, a1, MACH_FPC_EXCEPTION_INEXACT | MACH_FPC_STICKY_INEXACT
and v0, a1, MACH_FPC_ENABLE_INEXACT
or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
and v0, a1, MIPS_FPU_ENABLE_INEXACT
bne v0, zero, fpe_trap
ctc1 a1, MACH_FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
b done
/*
@ -2035,18 +2035,18 @@ inexact_nobias_d:
* or generate an infinity.
*/
overflow_d:
or a1, a1, MACH_FPC_EXCEPTION_OVERFLOW | MACH_FPC_STICKY_OVERFLOW
and v0, a1, MACH_FPC_ENABLE_OVERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW
and v0, a1, MIPS_FPU_ENABLE_OVERFLOW
beq v0, zero, 1f
subu t1, t1, 1536 # bias exponent
and t2, t2, ~DIMPL_ONE # clear implied one bit
jal _C_LABEL(set_fd_d) # save result
b fpe_trap
1:
and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode
beq v0, MACH_FPC_ROUND_RN, 3f # round to nearest
beq v0, MACH_FPC_ROUND_RZ, 1f # round to zero (truncate)
beq v0, MACH_FPC_ROUND_RP, 2f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, 1f # round to zero (truncate)
beq v0, MIPS_FPU_ROUND_RP, 2f # round to +infinity
bne t0, zero, 3f
1:
li t1, DEXP_MAX # result is max finite
@ -2066,7 +2066,7 @@ overflow_d:
* "loss of accuracy" is detected as "an inexact result".
*/
underflow_d:
and v0, a1, MACH_FPC_ENABLE_UNDERFLOW
and v0, a1, MIPS_FPU_ENABLE_UNDERFLOW
beq v0, zero, 1f
/*
* Underflow is enabled so compute the result and trap.
@ -2074,7 +2074,7 @@ underflow_d:
addu t1, t1, 1536 # bias exponent
and t2, t2, ~DIMPL_ONE # clear implied one bit
jal _C_LABEL(set_fd_d) # save result
or a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
b fpe_trap
/*
* Underflow is not enabled so compute the result,
@ -2090,15 +2090,15 @@ underflow_d:
move t1, zero # result is inexact zero
move t2, zero
move t3, zero
or a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
/*
* Now round the zero result.
* Only need to worry about rounding to +- infinity when the sign matches.
*/
and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode
beq v0, MACH_FPC_ROUND_RN, inexact_nobias_d # round to nearest
beq v0, MACH_FPC_ROUND_RZ, inexact_nobias_d # round to zero
beq v0, MACH_FPC_ROUND_RP, 1f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, inexact_nobias_d # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, inexact_nobias_d # round to zero
beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
beq t0, zero, inexact_nobias_d # if sign is positive, truncate
b 2f
1:
@ -2130,10 +2130,10 @@ underflow_d:
* Now round the denormalized result.
*/
2:
and v0, a1, MACH_FPC_ROUNDING_BITS # get rounding mode
beq v0, MACH_FPC_ROUND_RN, 3f # round to nearest
beq v0, MACH_FPC_ROUND_RZ, 5f # round to zero (truncate)
beq v0, MACH_FPC_ROUND_RP, 1f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
beq t0, zero, 5f # if sign is positive, truncate
b 2f
1:
@ -2159,11 +2159,11 @@ underflow_d:
move t1, zero # denorm or zero exponent
jal _C_LABEL(set_fd_d) # save result
beq t8, zero, done # check for exact result
or a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW
or a1, a1, MACH_FPC_EXCEPTION_INEXACT | MACH_FPC_STICKY_INEXACT
and v0, a1, MACH_FPC_ENABLE_INEXACT
or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
and v0, a1, MIPS_FPU_ENABLE_INEXACT
bne v0, zero, fpe_trap
ctc1 a1, MACH_FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
b done
/*
@ -2171,10 +2171,10 @@ underflow_d:
* the result is a quiet NAN.
*/
invalid_s: # trap invalid operation
or a1, a1, MACH_FPC_EXCEPTION_INVALID | MACH_FPC_STICKY_INVALID
and v0, a1, MACH_FPC_ENABLE_INVALID
or a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
and v0, a1, MIPS_FPU_ENABLE_INVALID
bne v0, zero, fpe_trap
ctc1 a1, MACH_FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
move t0, zero # result is a quiet NAN
li t1, SEXP_INF
li t2, SQUIET_NAN
@ -2186,10 +2186,10 @@ invalid_s: # trap invalid operation
* the result is a quiet NAN.
*/
invalid_d: # trap invalid operation
or a1, a1, MACH_FPC_EXCEPTION_INVALID | MACH_FPC_STICKY_INVALID
and v0, a1, MACH_FPC_ENABLE_INVALID
or a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
and v0, a1, MIPS_FPU_ENABLE_INVALID
bne v0, zero, fpe_trap
ctc1 a1, MACH_FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
move t0, zero # result is a quiet NAN
li t1, DEXP_INF
li t2, DQUIET_NAN0
@ -2202,10 +2202,10 @@ invalid_d: # trap invalid operation
* the result is INT_MAX or INT_MIN.
*/
invalid_w: # trap invalid operation
or a1, a1, MACH_FPC_EXCEPTION_INVALID | MACH_FPC_STICKY_INVALID
and v0, a1, MACH_FPC_ENABLE_INVALID
or a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
and v0, a1, MIPS_FPU_ENABLE_INVALID
bne v0, zero, fpe_trap
ctc1 a1, MACH_FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
bne t0, zero, 1f
li t2, INT_MAX # result is INT_MAX
b result_fs_w
@ -2218,14 +2218,14 @@ invalid_w: # trap invalid operation
*/
fpe_trap:
move a2, a1 # code = FP CSR
ctc1 a1, MACH_FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
break 0
/*
* Send an illegal instruction signal to the current process.
*/
ill:
ctc1 a1, MACH_FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
move a2, a0 # code = FP instruction
break 0

272
sys/arch/mips/mips/locore.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.35 1997/06/21 06:32:22 mhitch Exp $ */
/* $NetBSD: locore.S,v 1.36 1997/06/22 07:42:56 jonathan Exp $ */
/*
* Copyright (c) 1992, 1993
@ -170,7 +170,7 @@
.globl _C_LABEL(kernel_text)
start:
_C_LABEL(kernel_text):
mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts
/*
* Initialize stack and call machine startup.
*/
@ -178,17 +178,17 @@ _C_LABEL(kernel_text):
#ifdef __GP_SUPPORT__
la gp, _C_LABEL(_gp)
#endif
li t0, MACH_SR_COP_1_BIT # Disable interrupts and
mtc0 t0, MACH_COP_0_STATUS_REG # enable the fp coprocessor
li t0, MIPS_SR_COP_1_BIT # Disable interrupts and
mtc0 t0, MIPS_COP_0_STATUS_REG # enable the fp coprocessor
nop
nop
mfc0 t0, MACH_COP_0_PRID # read processor ID register
mfc0 t0, MIPS_COP_0_PRID # read processor ID register
nop # XXX r4000 pipeline:
nop # wait for new status to
nop # to be effective
nop
cfc1 t1, MACH_FPC_ID # read FPU ID register
cfc1 t1, MIPS_FPU_ID # read FPU ID register
sw t0, _C_LABEL(cpu_id) # save PRID register
sw t1, _C_LABEL(fpu_id) # save FPU ID register
sw zero, START_FRAME - 4(sp) # Zero out old ra for debugger
@ -601,8 +601,8 @@ END(remrunqueue)
* profiling.
*/
LEAF(idle)
li t0, (MACH_INT_MASK | MIPS_SR_INT_IE)
mtc0 t0, MACH_COP_0_STATUS_REG # enable all interrupts
li t0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
mtc0 t0, MIPS_COP_0_STATUS_REG # enable all interrupts
nop
sw zero, _C_LABEL(curproc) # set curproc NULL for stats
1:
@ -611,7 +611,7 @@ LEAF(idle)
beq t0, zero, 1b
nop
b sw1
mtc0 zero, MACH_COP_0_STATUS_REG # Disable all interrupts
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable all interrupts
END(idle)
/*
@ -620,7 +620,7 @@ END(idle)
*/
NON_LEAF(cpu_switch, STAND_FRAME_SIZE, ra)
lw a0, _C_LABEL(curpcb)
mfc0 t0, MACH_COP_0_STATUS_REG
mfc0 t0, MIPS_COP_0_STATUS_REG
sw s0, U_PCB_CONTEXT+0(a0)
sw s1, U_PCB_CONTEXT+4(a0)
sw s2, U_PCB_CONTEXT+8(a0)
@ -641,7 +641,7 @@ NON_LEAF(cpu_switch, STAND_FRAME_SIZE, ra)
addu t0, t0, 1
sw t0, cnt+V_SWTCH
beq t1, zero, idle
mtc0 zero, MACH_COP_0_STATUS_REG
mtc0 zero, MIPS_COP_0_STATUS_REG
/*
* Entered here from idle() and switch_exit().
*/
@ -701,7 +701,7 @@ END(cpu_switch)
* savectx(struct user *up)
*/
LEAF(savectx)
mfc0 v0, MACH_COP_0_STATUS_REG
mfc0 v0, MIPS_COP_0_STATUS_REG
sw s0, U_PCB_CONTEXT+0(a0)
sw s1, U_PCB_CONTEXT+4(a0)
sw s2, U_PCB_CONTEXT+8(a0)
@ -724,7 +724,7 @@ END(savectx)
* longjmp(label_t *)
*/
LEAF(setjmp)
mfc0 v0, MACH_COP_0_STATUS_REG
mfc0 v0, MIPS_COP_0_STATUS_REG
sw s0, 0(a0)
sw s1, 4(a0)
sw s2, 8(a0)
@ -754,7 +754,7 @@ LEAF(longjmp)
lw s7, 28(a0)
lw sp, 32(a0)
lw s8, 36(a0)
mtc0 v0, MACH_COP_0_STATUS_REG
mtc0 v0, MIPS_COP_0_STATUS_REG
j ra
li v0, 1
END(longjmp)
@ -1142,56 +1142,56 @@ END(fswintrberr)
*/
LEAF(setsoftclock)
mfc0 v1, MACH_COP_0_STATUS_REG # save status register
mtc0 zero, MACH_COP_0_STATUS_REG # disable interrupts (2 cycles)
mfc0 v1, MIPS_COP_0_STATUS_REG # save status register
mtc0 zero, MIPS_COP_0_STATUS_REG # disable interrupts (2 cycles)
nop
mfc0 v0, MACH_COP_0_CAUSE_REG # read cause register
mfc0 v0, MIPS_COP_0_CAUSE_REG # read cause register
nop
or v0, v0, MACH_SOFT_INT_MASK_0 # set soft clock interrupt
mtc0 v0, MACH_COP_0_CAUSE_REG # save it
mtc0 v1, MACH_COP_0_STATUS_REG
or v0, v0, MIPS_SOFT_INT_MASK_0 # set soft clock interrupt
mtc0 v0, MIPS_COP_0_CAUSE_REG # save it
mtc0 v1, MIPS_COP_0_STATUS_REG
j ra
nop
END(setsoftclock)
LEAF(clearsoftclock)
mfc0 v1, MACH_COP_0_STATUS_REG # save status register
mtc0 zero, MACH_COP_0_STATUS_REG # disable interrupts (2 cycles)
mfc0 v1, MIPS_COP_0_STATUS_REG # save status register
mtc0 zero, MIPS_COP_0_STATUS_REG # disable interrupts (2 cycles)
nop
nop
mfc0 v0, MACH_COP_0_CAUSE_REG # read cause register
mfc0 v0, MIPS_COP_0_CAUSE_REG # read cause register
nop
and v0, v0, ~MACH_SOFT_INT_MASK_0 # clear soft clock interrupt
mtc0 v0, MACH_COP_0_CAUSE_REG # save it
mtc0 v1, MACH_COP_0_STATUS_REG
and v0, v0, ~MIPS_SOFT_INT_MASK_0 # clear soft clock interrupt
mtc0 v0, MIPS_COP_0_CAUSE_REG # save it
mtc0 v1, MIPS_COP_0_STATUS_REG
j ra
nop
END(clearsoftclock)
LEAF(setsoftnet)
mfc0 v1, MACH_COP_0_STATUS_REG # save status register
mtc0 zero, MACH_COP_0_STATUS_REG # disable interrupts (2 cycles)
mfc0 v1, MIPS_COP_0_STATUS_REG # save status register
mtc0 zero, MIPS_COP_0_STATUS_REG # disable interrupts (2 cycles)
nop
nop
mfc0 v0, MACH_COP_0_CAUSE_REG # read cause register
mfc0 v0, MIPS_COP_0_CAUSE_REG # read cause register
nop
or v0, v0, MACH_SOFT_INT_MASK_1 # set soft net interrupt
mtc0 v0, MACH_COP_0_CAUSE_REG # save it
mtc0 v1, MACH_COP_0_STATUS_REG
or v0, v0, MIPS_SOFT_INT_MASK_1 # set soft net interrupt
mtc0 v0, MIPS_COP_0_CAUSE_REG # save it
mtc0 v1, MIPS_COP_0_STATUS_REG
j ra
nop
END(setsoftnet)
LEAF(clearsoftnet)
mfc0 v1, MACH_COP_0_STATUS_REG # save status register
mtc0 zero, MACH_COP_0_STATUS_REG # disable interrupts (2 cycles)
mfc0 v1, MIPS_COP_0_STATUS_REG # save status register
mtc0 zero, MIPS_COP_0_STATUS_REG # disable interrupts (2 cycles)
nop
nop
mfc0 v0, MACH_COP_0_CAUSE_REG # read cause register
mfc0 v0, MIPS_COP_0_CAUSE_REG # read cause register
nop
and v0, v0, ~MACH_SOFT_INT_MASK_1 # clear soft net interrupt
mtc0 v0, MACH_COP_0_CAUSE_REG # save it
mtc0 v1, MACH_COP_0_STATUS_REG
and v0, v0, ~MIPS_SOFT_INT_MASK_1 # clear soft net interrupt
mtc0 v0, MIPS_COP_0_CAUSE_REG # save it
mtc0 v1, MIPS_COP_0_STATUS_REG
j ra
nop
END(clearsoftnet)
@ -1202,10 +1202,10 @@ END(clearsoftnet)
#if 0 /* NOTUSED */
LEAF(MachEnableIntr)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
nop
or v0, v0, MIPS_SR_INT_IE
mtc0 v0, MACH_COP_0_STATUS_REG # enable all interrupts
mtc0 v0, MIPS_COP_0_STATUS_REG # enable all interrupts
j ra
nop
END(MachEnableIntr)
@ -1213,31 +1213,31 @@ END(MachEnableIntr)
LEAF(spl0)
ALEAF(spllow)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
nop
or t0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
mtc0 t0, MACH_COP_0_STATUS_REG # enable all interrupts
or t0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
mtc0 t0, MIPS_COP_0_STATUS_REG # enable all interrupts
j ra
and v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(spl0)
LEAF(splsoftclock)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
li t0, ~MACH_SOFT_INT_MASK_0 # disable soft clock
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
li t0, ~MIPS_SOFT_INT_MASK_0 # disable soft clock
and t0, t0, v0
mtc0 t0, MACH_COP_0_STATUS_REG # save it
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
nop # 3 ins to disable on r4x00
j ra
and v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(splsoftclock)
LEAF(splsoftnet)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
li t0, ~(MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0)
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
li t0, ~(MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
and t0, t0, v0
mtc0 t0, MACH_COP_0_STATUS_REG # save it
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
j ra
and v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(splsoftnet)
/*
@ -1250,67 +1250,67 @@ END(splsoftnet)
* Block out int2 (hardware interrupt 0) and lower mips levels.
*/
LEAF(cpu_spl0)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
li t0, ~(MACH_INT_MASK_SPL0)
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
li t0, ~(MIPS_INT_MASK_SPL0)
and t0, t0, v0
mtc0 t0, MACH_COP_0_STATUS_REG # save it
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
nop # 3 ins to disable on r4x00
j ra
and v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(cpu_spl0)
/*
* Block out Int3 (hardware interrupt 1) and lower mips levels.
*/
LEAF(cpu_spl1)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
li t0, ~(MACH_INT_MASK_SPL1)
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
li t0, ~(MIPS_INT_MASK_SPL1)
and t0, t0, v0
mtc0 t0, MACH_COP_0_STATUS_REG # save it
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
nop # 3 ins to disable on r4x00
j ra
and v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(cpu_spl1)
LEAF(cpu_spl2)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
li t0, ~(MACH_INT_MASK_SPL2)
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
li t0, ~(MIPS_INT_MASK_SPL2)
and t0, t0, v0
mtc0 t0, MACH_COP_0_STATUS_REG # save it
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
nop # 3 ins to disable on r4x00
j ra
and v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(cpu_spl2)
LEAF(cpu_spl3)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
li t0, ~(MACH_INT_MASK_SPL3)
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
li t0, ~(MIPS_INT_MASK_SPL3)
and t0, t0, v0
mtc0 t0, MACH_COP_0_STATUS_REG # save it
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
nop # 3 ins to disable on r4x00
j ra
and v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(cpu_spl3)
LEAF(cpu_spl4)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
li t0, ~(MACH_INT_MASK_SPL4)
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
li t0, ~(MIPS_INT_MASK_SPL4)
and t0, t0, v0
mtc0 t0, MACH_COP_0_STATUS_REG # save it
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
nop # 3 ins to disable
j ra
and v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(cpu_spl4)
LEAF(cpu_spl5)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
li t0, ~(MACH_INT_MASK_SPL5)
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
li t0, ~(MIPS_INT_MASK_SPL5)
and t0, t0, v0
mtc0 t0, MACH_COP_0_STATUS_REG # save it
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
nop # 3 ins to disable
j ra
and v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(cpu_spl5)
/*
@ -1323,63 +1323,63 @@ END(cpu_spl5)
* XXX the spl handling really needs re-writing from scratch.
*/
LEAF(Mach_spl0)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
li t0, ~(MACH_INT_MASK_0|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0)
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
li t0, ~(MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
and t0, t0, v0
mtc0 t0, MACH_COP_0_STATUS_REG # save it
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
nop # 3 ins to disable on r4x00
j ra
and v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(Mach_spl0)
LEAF(Mach_spl1)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
li t0, ~(MACH_INT_MASK_1|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0)
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
li t0, ~(MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
and t0, t0, v0
mtc0 t0, MACH_COP_0_STATUS_REG # save it
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
nop # 3 ins to disable on r4x00
j ra
and v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(Mach_spl1)
LEAF(Mach_spl2)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
li t0, ~(MACH_INT_MASK_2|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0)
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
li t0, ~(MIPS_INT_MASK_2|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
and t0, t0, v0
mtc0 t0, MACH_COP_0_STATUS_REG # save it
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
nop # 3 ins to disable on r4x00
j ra
and v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(Mach_spl2)
LEAF(Mach_spl3)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
li t0, ~(MACH_INT_MASK_3|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0)
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
li t0, ~(MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
and t0, t0, v0
mtc0 t0, MACH_COP_0_STATUS_REG # save it
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
nop # 3 ins to disable on r4x00
j ra
and v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(Mach_spl3)
LEAF(Mach_spl4)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
li t0, ~(MACH_INT_MASK_4|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0)
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
li t0, ~(MIPS_INT_MASK_4|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
and t0, t0, v0
mtc0 t0, MACH_COP_0_STATUS_REG # save it
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
nop # 3 ins to disable
j ra
and v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(Mach_spl4)
LEAF(Mach_spl5)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
li t0, ~(MACH_INT_MASK_5|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0)
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
li t0, ~(MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
and t0, t0, v0
mtc0 t0, MACH_COP_0_STATUS_REG # save it
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
nop # 3 ins to disable
j ra
and v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(Mach_spl5)
@ -1389,13 +1389,13 @@ END(Mach_spl5)
*/
LEAF(splhigh)
ALEAF(_splhigh)
mfc0 v0, MACH_COP_0_STATUS_REG # read status register
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
li t0, ~MIPS_SR_INT_IE # disable all interrupts
and t0, t0, v0
mtc0 t0, MACH_COP_0_STATUS_REG # save it
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
nop # 3 ins to disable on r4x00
j ra
and v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
END(splhigh)
/*
@ -1403,11 +1403,11 @@ END(splhigh)
*/
LEAF(splx)
ALEAF(_splx)
mfc0 v0, MACH_COP_0_STATUS_REG
li t0, ~(MACH_INT_MASK | MIPS_SR_INT_IE)
mfc0 v0, MIPS_COP_0_STATUS_REG
li t0, ~(MIPS_INT_MASK | MIPS_SR_INT_IE)
and t0, t0, v0
or t0, t0, a0
mtc0 t0, MACH_COP_0_STATUS_REG
mtc0 t0, MIPS_COP_0_STATUS_REG
nop # 3 ins to disable
j ra
nop
@ -1433,7 +1433,7 @@ END(splx)
*----------------------------------------------------------------------------
*/
LEAF(MachGetCauseReg)
mfc0 v0, MACH_COP_0_CAUSE_REG
mfc0 v0, MIPS_COP_0_CAUSE_REG
j ra
nop
END(MachGetCauseReg)
@ -1458,9 +1458,9 @@ END(MachGetCauseReg)
*----------------------------------------------------------------------------
*/
LEAF(switchfpregs)
mfc0 v0, MACH_COP_0_STATUS_REG # Disable interrupt and
li t0, MACH_SR_COP_1_BIT # enable the coprocessor
mtc0 t0, MACH_COP_0_STATUS_REG # old SR is saved in v0
mfc0 v0, MIPS_COP_0_STATUS_REG # Disable interrupt and
li t0, MIPS_SR_COP_1_BIT # enable the coprocessor
mtc0 t0, MIPS_COP_0_STATUS_REG # old SR is saved in v0
beq a0, zero, 1f # skip save if NULL pointer
nop
@ -1469,10 +1469,10 @@ LEAF(switchfpregs)
* have completed.
*/
lw a0, P_ADDR(a0) # get pointer to pcb for proc
cfc1 t0, MACH_FPC_CSR # stall til FP done
cfc1 t0, MACH_FPC_CSR # now get status
cfc1 t0, MIPS_FPU_CSR # stall til FP done
cfc1 t0, MIPS_FPU_CSR # now get status
lw t1, U_PCB_REGS+(SR * 4)(a0) # get CPU status register
li t2, ~MACH_SR_COP_1_BIT
li t2, ~MIPS_SR_COP_1_BIT
and t1, t1, t2 # clear COP_1 enable bit
sw t1, U_PCB_REGS+(SR * 4)(a0) # save new status register
/*
@ -1552,12 +1552,12 @@ LEAF(switchfpregs)
lwc1 $f30, U_PCB_FPREGS+(30 * 4)(a1)
lwc1 $f31, U_PCB_FPREGS+(31 * 4)(a1)
and t0, t0, ~MACH_FPC_EXCEPTION_BITS
ctc1 t0, MACH_FPC_CSR
and t0, t0, ~MIPS_FPU_EXCEPTION_BITS
ctc1 t0, MIPS_FPU_CSR
nop
j ra
mtc0 v0, MACH_COP_0_STATUS_REG # Restore the status register.
mtc0 v0, MIPS_COP_0_STATUS_REG # Restore the status register.
END(switchfpregs)
/*----------------------------------------------------------------------------
@ -1578,19 +1578,19 @@ END(switchfpregs)
*----------------------------------------------------------------------------
*/
LEAF(savefpregs)
mfc0 v0, MACH_COP_0_STATUS_REG # Disable interrupts and
li t0, MACH_SR_COP_1_BIT # enable the coprocessor
mtc0 t0, MACH_COP_0_STATUS_REG
mfc0 v0, MIPS_COP_0_STATUS_REG # Disable interrupts and
li t0, MIPS_SR_COP_1_BIT # enable the coprocessor
mtc0 t0, MIPS_COP_0_STATUS_REG
sw zero, _C_LABEL(fpcurproc) # indicate state has been saved
/*
* First read out the status register to make sure that all FP operations
* have completed.
*/
lw a0, P_ADDR(a0) # get pointer to pcb for proc
cfc1 t0, MACH_FPC_CSR # stall til FP done
cfc1 t0, MACH_FPC_CSR # now get status
cfc1 t0, MIPS_FPU_CSR # stall til FP done
cfc1 t0, MIPS_FPU_CSR # now get status
lw t1, U_PCB_REGS+(SR * 4)(a0) # get CPU status register
li t2, ~MACH_SR_COP_1_BIT
li t2, ~MIPS_SR_COP_1_BIT
and t1, t1, t2 # clear COP_1 enable bit
sw t1, U_PCB_REGS+(SR * 4)(a0) # save new status register
/*
@ -1631,7 +1631,7 @@ LEAF(savefpregs)
swc1 $f31, U_PCB_FPREGS+(31 * 4)(a0)
j ra
mtc0 v0, MACH_COP_0_STATUS_REG # Restore the status register.
mtc0 v0, MIPS_COP_0_STATUS_REG # Restore the status register.
END(savefpregs)
/*----------------------------------------------------------------------------
@ -1667,19 +1667,19 @@ NON_LEAF(MachFPInterrupt, STAND_FRAME_SIZE, ra)
ALEAF(MachFPTrap)
subu sp, sp, STAND_FRAME_SIZE
mfc0 t0, MACH_COP_0_STATUS_REG
mfc0 t0, MIPS_COP_0_STATUS_REG
sw ra, STAND_RA_OFFSET(sp)
.mask 0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE)
or t0, t0, MACH_SR_COP_1_BIT
mtc0 t0, MACH_COP_0_STATUS_REG
or t0, t0, MIPS_SR_COP_1_BIT
mtc0 t0, MIPS_COP_0_STATUS_REG
nop
nop
nop # 1st extra nop for r4k
nop # 2nd extra nop for r4k
cfc1 t0, MACH_FPC_CSR # stall til FP done
cfc1 t0, MACH_FPC_CSR # now get status
cfc1 t0, MIPS_FPU_CSR # stall til FP done
cfc1 t0, MIPS_FPU_CSR # now get status
nop
sll t2, t0, (31 - 17) # unimplemented operation?
bgez t2, 3f # no, normal trap
@ -1722,16 +1722,16 @@ ALEAF(MachFPTrap)
* Check to see if the instruction to be emulated is a floating-point
* instruction.
*/
srl t0, a0, MACH_OPCODE_SHIFT
beq t0, MACH_OPCODE_C1, 4f # this should never fail
srl t0, a0, MIPS_OPCODE_SHIFT
beq t0, MIPS_OPCODE_C1, 4f # this should never fail
nop
/*
* Send a floating point exception signal to the current process.
*/
3:
lw a0, _C_LABEL(curproc) # get current process
cfc1 a2, MACH_FPC_CSR # code = FP execptions
ctc1 zero, MACH_FPC_CSR # Clear exceptions
cfc1 a2, MIPS_FPU_CSR # code = FP execptions
ctc1 zero, MIPS_FPU_CSR # Clear exceptions
jal _C_LABEL(trapsignal)
li a1, SIGFPE
b FPReturn
@ -1748,10 +1748,10 @@ ALEAF(MachFPTrap)
* Turn off the floating point coprocessor and return.
*/
FPReturn:
mfc0 t0, MACH_COP_0_STATUS_REG
mfc0 t0, MIPS_COP_0_STATUS_REG
lw ra, STAND_RA_OFFSET(sp)
and t0, t0, ~MACH_SR_COP_1_BIT
mtc0 t0, MACH_COP_0_STATUS_REG
and t0, t0, ~MIPS_SR_COP_1_BIT
mtc0 t0, MIPS_COP_0_STATUS_REG
j ra
addu sp, sp, STAND_FRAME_SIZE
END(MachFPInterrupt)
@ -1766,7 +1766,7 @@ L* {
L* }
*/
LEAF(mdbpanic)
break MACH_BREAK_SOVER_VAL
break MIPS_BREAK_SOVER_VAL
j ra
nop
END(mdbpanic)

392
sys/arch/mips/mips/locore_r2000.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore_r2000.S,v 1.34 1997/06/21 06:32:24 mhitch Exp $ */
/* $NetBSD: locore_r2000.S,v 1.35 1997/06/22 07:42:57 jonathan Exp $ */
/*
* Copyright (c) 1992, 1993
@ -76,14 +76,14 @@
.globl _C_LABEL(mips1_UTLBMiss)
_C_LABEL(mips1_UTLBMiss):
.set noat
mfc0 k0, MACH_COP_0_BAD_VADDR # get the virtual address
mfc0 k0, MIPS_COP_0_BAD_VADDR # get the virtual address
lw k1, _C_LABEL(curpcb)
bltz k0, 1f # R3000 chip bug
lw k1, U_PCB_SEGTAB(k1) # get the current segment table
srl k0, k0, SEGSHIFT # compute segment table index
sll k0, k0, 2
addu k1, k1, k0
mfc0 k0, MACH_COP_0_BAD_VADDR # get the virtual address
mfc0 k0, MIPS_COP_0_BAD_VADDR # get the virtual address
lw k1, 0(k1) # get pointer to segment map
srl k0, k0, PGSHIFT - 2 # compute segment map index
andi k0, k0, (NPTEPG - 1) << 2
@ -92,13 +92,13 @@ _C_LABEL(mips1_UTLBMiss):
lw k0, 0(k1) # get page PTE
nop
beq k0, zero, 2f # dont load invalid entries
mtc0 k0, MACH_COP_0_TLB_LOW
mfc0 k1, MACH_COP_0_EXC_PC # get return address
mtc0 k0, MIPS_COP_0_TLB_LOW
mfc0 k1, MIPS_COP_0_EXC_PC # get return address
tlbwr # update TLB
j k1
rfe
1:
mfc0 k1, MACH_COP_0_EXC_PC # get return address
mfc0 k1, MIPS_COP_0_EXC_PC # get return address
nop
j k1
rfe
@ -130,8 +130,8 @@ _C_LABEL(mips1_exception):
* Find out what mode we came from and jump to the proper handler.
*/
.set noat
mfc0 k0, MACH_COP_0_STATUS_REG # Get the status register
mfc0 k1, MACH_COP_0_CAUSE_REG # Get the cause register value.
mfc0 k0, MIPS_COP_0_STATUS_REG # Get the status register
mfc0 k1, MIPS_COP_0_CAUSE_REG # Get the cause register value.
and k0, k0, MIPS1_SR_KU_PREV # test for user mode
sll k0, k0, 4 # shift user bit for cause index
and k1, k1, MIPS1_CR_EXC_CODE # Mask out the cause bits.
@ -166,7 +166,7 @@ _C_LABEL(mips1_exceptionEnd):
*/
mips1_SlowFault:
.set noat
mfc0 k0, MACH_COP_0_STATUS_REG
mfc0 k0, MIPS_COP_0_STATUS_REG
nop
and k0, k0, MIPS1_SR_KU_PREV
bne k0, zero, _C_LABEL(mips1_UserGenException)
@ -204,22 +204,22 @@ NNON_LEAF(mips1_KernGenException, TRAP_FRAME_SIZE, ra)
sw a2, TRAP_FRAME_OFFSET+(A2 * 4)(sp)
sw a3, TRAP_FRAME_OFFSET+(A3 * 4)(sp)
sw t0, TRAP_FRAME_OFFSET+(T0 * 4)(sp)
mfc0 a0, MACH_COP_0_STATUS_REG # 1st arg is STATUS
mfc0 a0, MIPS_COP_0_STATUS_REG # 1st arg is STATUS
sw t1, TRAP_FRAME_OFFSET+(T1 * 4)(sp)
sw t2, TRAP_FRAME_OFFSET+(T2 * 4)(sp)
sw t3, TRAP_FRAME_OFFSET+(T3 * 4)(sp)
sw t4, TRAP_FRAME_OFFSET+(T4 * 4)(sp)
mfc0 a1, MACH_COP_0_CAUSE_REG # 2nd arg is CAUSE
mfc0 a1, MIPS_COP_0_CAUSE_REG # 2nd arg is CAUSE
sw t5, TRAP_FRAME_OFFSET+(T5 * 4)(sp)
sw t6, TRAP_FRAME_OFFSET+(T6 * 4)(sp)
sw t7, TRAP_FRAME_OFFSET+(T7 * 4)(sp)
sw t8, TRAP_FRAME_OFFSET+(T8 * 4)(sp)
mfc0 a2, MACH_COP_0_BAD_VADDR # 3rd arg is fault address
mfc0 a2, MIPS_COP_0_BAD_VADDR # 3rd arg is fault address
sw t9, TRAP_FRAME_OFFSET+(T9 * 4)(sp)
sw ra, TRAP_FRAME_OFFSET+(RA * 4)(sp)
sw a0, TRAP_FRAME_OFFSET+(SR * 4)(sp)
sw v0, TRAP_FRAME_OFFSET+(MULLO * 4)(sp)
mfc0 a3, MACH_COP_0_EXC_PC # 4th arg is PC
mfc0 a3, MIPS_COP_0_EXC_PC # 4th arg is PC
sw v1, TRAP_FRAME_OFFSET+(MULHI * 4)(sp)
sw a3, TRAP_FRAME_OFFSET+(PC * 4)(sp)
@ -229,7 +229,7 @@ NNON_LEAF(mips1_KernGenException, TRAP_FRAME_SIZE, ra)
lw a0, TRAP_FRAME_OFFSET+(SR * 4)(sp)
lw t0, TRAP_FRAME_OFFSET+(MULLO * 4)(sp)
lw t1, TRAP_FRAME_OFFSET+(MULHI * 4)(sp)
mtc0 a0, MACH_COP_0_STATUS_REG
mtc0 a0, MIPS_COP_0_STATUS_REG
mtlo t0
mthi t1
lw k0, TRAP_FRAME_OFFSET+(PC * 4)(sp) # might be changed inside trap
@ -290,22 +290,22 @@ NNON_LEAF(mips1_UserGenException, STAND_FRAME_SIZE, ra)
sw t2, U_PCB_REGS+(T2 * 4)(k1)
sw t3, U_PCB_REGS+(T3 * 4)(k1)
sw t4, U_PCB_REGS+(T4 * 4)(k1)
mfc0 a0, MACH_COP_0_STATUS_REG # 1st arg is STATUS
mfc0 a0, MIPS_COP_0_STATUS_REG # 1st arg is STATUS
sw t5, U_PCB_REGS+(T5 * 4)(k1)
sw t6, U_PCB_REGS+(T6 * 4)(k1)
sw t7, U_PCB_REGS+(T7 * 4)(k1)
sw s0, U_PCB_REGS+(S0 * 4)(k1)
mfc0 a1, MACH_COP_0_CAUSE_REG # 2nd arg is CAUSE
mfc0 a1, MIPS_COP_0_CAUSE_REG # 2nd arg is CAUSE
sw s1, U_PCB_REGS+(S1 * 4)(k1)
sw s2, U_PCB_REGS+(S2 * 4)(k1)
sw s3, U_PCB_REGS+(S3 * 4)(k1)
sw s4, U_PCB_REGS+(S4 * 4)(k1)
mfc0 a2, MACH_COP_0_BAD_VADDR # 3rd arg is fault address
mfc0 a2, MIPS_COP_0_BAD_VADDR # 3rd arg is fault address
sw s5, U_PCB_REGS+(S5 * 4)(k1)
sw s6, U_PCB_REGS+(S6 * 4)(k1)
sw s7, U_PCB_REGS+(S7 * 4)(k1)
sw t8, U_PCB_REGS+(T8 * 4)(k1)
mfc0 a3, MACH_COP_0_EXC_PC # 4th arg is PC
mfc0 a3, MIPS_COP_0_EXC_PC # 4th arg is PC
sw t9, U_PCB_REGS+(T9 * 4)(k1)
sw gp, U_PCB_REGS+(GP * 4)(k1)
sw sp, U_PCB_REGS+(SP * 4)(k1)
@ -321,10 +321,10 @@ NNON_LEAF(mips1_UserGenException, STAND_FRAME_SIZE, ra)
la gp, _C_LABEL(_gp) # switch to kernel GP
#endif
.set at
and t0, a0, ~MACH_SR_COP_1_BIT # Turn off the FPU.
and t0, a0, ~MIPS_SR_COP_1_BIT # Turn off the FPU.
.set noat
jal _C_LABEL(trap)
mtc0 t0, MACH_COP_0_STATUS_REG
mtc0 t0, MIPS_COP_0_STATUS_REG
/*
* Restore user registers and return. NOTE: interrupts are enabled.
*/
@ -333,7 +333,7 @@ NNON_LEAF(mips1_UserGenException, STAND_FRAME_SIZE, ra)
lw a0, U_PCB_REGS+(SR * 4)(a1)
lw t0, U_PCB_REGS+(MULLO * 4)(a1)
lw t1, U_PCB_REGS+(MULHI * 4)(a1)
mtc0 a0, MACH_COP_0_STATUS_REG # this should disable interrupts
mtc0 a0, MIPS_COP_0_STATUS_REG # this should disable interrupts
mtlo t0
mthi t1
move k1, a1
@ -394,12 +394,12 @@ NNON_LEAF(mips1_SystemCall, STAND_FRAME_SIZE, ra)
sw t2, U_PCB_REGS+(T2 * 4)(k1)
sw t3, U_PCB_REGS+(T3 * 4)(k1)
sw t4, U_PCB_REGS+(T4 * 4)(k1)
mfc0 a0, MACH_COP_0_STATUS_REG # 1st arg is STATUS
mfc0 a0, MIPS_COP_0_STATUS_REG # 1st arg is STATUS
sw t5, U_PCB_REGS+(T5 * 4)(k1)
sw t6, U_PCB_REGS+(T6 * 4)(k1)
sw t7, U_PCB_REGS+(T7 * 4)(k1)
sw s0, U_PCB_REGS+(S0 * 4)(k1)
mfc0 a1, MACH_COP_0_CAUSE_REG # 2nd arg is CAUSE
mfc0 a1, MIPS_COP_0_CAUSE_REG # 2nd arg is CAUSE
sw s1, U_PCB_REGS+(S1 * 4)(k1)
sw s2, U_PCB_REGS+(S2 * 4)(k1)
sw s3, U_PCB_REGS+(S3 * 4)(k1)
@ -408,7 +408,7 @@ NNON_LEAF(mips1_SystemCall, STAND_FRAME_SIZE, ra)
sw s6, U_PCB_REGS+(S6 * 4)(k1)
sw s7, U_PCB_REGS+(S7 * 4)(k1)
sw t8, U_PCB_REGS+(T8 * 4)(k1)
mfc0 a2, MACH_COP_0_EXC_PC # 3rd arg is PC
mfc0 a2, MIPS_COP_0_EXC_PC # 3rd arg is PC
sw t9, U_PCB_REGS+(T9 * 4)(k1)
sw gp, U_PCB_REGS+(GP * 4)(k1)
sw sp, U_PCB_REGS+(SP * 4)(k1)
@ -425,10 +425,10 @@ NNON_LEAF(mips1_SystemCall, STAND_FRAME_SIZE, ra)
la gp, _C_LABEL(_gp) # switch to kernel GP
#endif
.set at
and t0, a0, ~MACH_SR_COP_1_BIT # Turn off the FPU.
and t0, a0, ~MIPS_SR_COP_1_BIT # Turn off the FPU.
.set noat
jal _C_LABEL(syscall)
mtc0 t0, MACH_COP_0_STATUS_REG
mtc0 t0, MIPS_COP_0_STATUS_REG
/*
* Restore user registers and return. NOTE: interrupts are enabled.
*/
@ -437,7 +437,7 @@ NNON_LEAF(mips1_SystemCall, STAND_FRAME_SIZE, ra)
lw a0, U_PCB_REGS+(SR * 4)(a1)
lw t0, U_PCB_REGS+(MULLO * 4)(a1)
lw t1, U_PCB_REGS+(MULHI * 4)(a1)
mtc0 a0, MACH_COP_0_STATUS_REG # this should disable interrupts
mtc0 a0, MIPS_COP_0_STATUS_REG # this should disable interrupts
mtlo t0
mthi t1
move k1, a1
@ -511,17 +511,17 @@ NNON_LEAF(mips1_KernIntr, INTR_FRAME_SIZE, ra)
sw a2, INTR_FRAME_OFFSET+(A2 * 4)(sp)
sw a3, INTR_FRAME_OFFSET+(A3 * 4)(sp)
sw t0, INTR_FRAME_OFFSET+(T0 * 4)(sp)
mfc0 a0, MACH_COP_0_STATUS_REG # 1st arg is STATUS
mfc0 a0, MIPS_COP_0_STATUS_REG # 1st arg is STATUS
sw t1, INTR_FRAME_OFFSET+(T1 * 4)(sp)
sw t2, INTR_FRAME_OFFSET+(T2 * 4)(sp)
sw t3, INTR_FRAME_OFFSET+(T3 * 4)(sp)
sw t4, INTR_FRAME_OFFSET+(T4 * 4)(sp)
mfc0 a1, MACH_COP_0_CAUSE_REG # Second arg is the cause reg.
mfc0 a1, MIPS_COP_0_CAUSE_REG # Second arg is the cause reg.
sw t5, INTR_FRAME_OFFSET+(T5 * 4)(sp)
sw t6, INTR_FRAME_OFFSET+(T6 * 4)(sp)
sw t7, INTR_FRAME_OFFSET+(T7 * 4)(sp)
sw t8, INTR_FRAME_OFFSET+(T8 * 4)(sp)
mfc0 a2, MACH_COP_0_EXC_PC # 3rd arg is PC
mfc0 a2, MIPS_COP_0_EXC_PC # 3rd arg is PC
sw t9, INTR_FRAME_OFFSET+(T9 * 4)(sp)
sw ra, INTR_FRAME_OFFSET+(RA * 4)(sp)
la a3, INTR_FRAME_OFFSET(sp) # 4th arg is p. to trapframe
@ -538,7 +538,7 @@ NNON_LEAF(mips1_KernIntr, INTR_FRAME_SIZE, ra)
lw a0, INTR_FRAME_OFFSET+(SR * 4)(sp)
lw t0, INTR_FRAME_OFFSET+(MULLO * 4)(sp)
lw t1, INTR_FRAME_OFFSET+(MULHI * 4)(sp)
mtc0 a0, MACH_COP_0_STATUS_REG # Restore the SR, disable intrs
mtc0 a0, MIPS_COP_0_STATUS_REG # Restore the SR, disable intrs
mtlo t0
mthi t1
lw k0, STAND_RA_OFFSET(sp) # restore original PC
@ -604,17 +604,17 @@ NNON_LEAF(mips1_UserIntr, STAND_FRAME_SIZE, ra)
sw a2, U_PCB_REGS+(A2 * 4)(k1)
sw a3, U_PCB_REGS+(A3 * 4)(k1)
sw t0, U_PCB_REGS+(T0 * 4)(k1)
mfc0 a0, MACH_COP_0_STATUS_REG # 1st arg is STATUS
mfc0 a0, MIPS_COP_0_STATUS_REG # 1st arg is STATUS
sw t1, U_PCB_REGS+(T1 * 4)(k1)
sw t2, U_PCB_REGS+(T2 * 4)(k1)
sw t3, U_PCB_REGS+(T3 * 4)(k1)
sw t4, U_PCB_REGS+(T4 * 4)(k1)
mfc0 a1, MACH_COP_0_CAUSE_REG # 2nd arg is CAUSE
mfc0 a1, MIPS_COP_0_CAUSE_REG # 2nd arg is CAUSE
sw t5, U_PCB_REGS+(T5 * 4)(k1)
sw t6, U_PCB_REGS+(T6 * 4)(k1)
sw t7, U_PCB_REGS+(T7 * 4)(k1)
sw t8, U_PCB_REGS+(T8 * 4)(k1)
mfc0 a2, MACH_COP_0_EXC_PC # 3rd arg is PC
mfc0 a2, MIPS_COP_0_EXC_PC # 3rd arg is PC
sw t9, U_PCB_REGS+(T9 * 4)(k1)
sw gp, U_PCB_REGS+(GP * 4)(k1)
sw sp, U_PCB_REGS+(SP * 4)(k1)
@ -633,10 +633,10 @@ NNON_LEAF(mips1_UserIntr, STAND_FRAME_SIZE, ra)
* Call the interrupt handler.
*/
.set at
and t0, a0, ~MACH_SR_COP_1_BIT # Turn off the FPU.
and t0, a0, ~MIPS_SR_COP_1_BIT # Turn off the FPU.
.set noat
jal _C_LABEL(interrupt)
mtc0 t0, MACH_COP_0_STATUS_REG
mtc0 t0, MIPS_COP_0_STATUS_REG
/*
* Check pending asynchoronous traps.
*/
@ -644,7 +644,7 @@ NNON_LEAF(mips1_UserIntr, STAND_FRAME_SIZE, ra)
nop
lw a0, U_PCB_REGS+(SR * 4)(a1)
lw v0, _C_LABEL(astpending) # any pending ast?
mtc0 a0, MACH_COP_0_STATUS_REG # restore SR disabling intrs
mtc0 a0, MIPS_COP_0_STATUS_REG # restore SR disabling intrs
beq v0, zero, 1f # if no, skip ast processing
/*
* We have pending asynchronous traps; save remaining user state in u.u_pcb.
@ -660,15 +660,15 @@ NNON_LEAF(mips1_UserIntr, STAND_FRAME_SIZE, ra)
sw s8, U_PCB_REGS+(S8 * 4)(a1)
lw a0, U_PCB_REGS+(PC * 4)(a1) # argument is interrupted PC
li t0, MACH_HARD_INT_MASK | MIPS_SR_INT_IE
li t0, MIPS_HARD_INT_MASK | MIPS_SR_INT_IE
jal _C_LABEL(ast)
mtc0 t0, MACH_COP_0_STATUS_REG # enable interrupts (spl0)
mtc0 t0, MIPS_COP_0_STATUS_REG # enable interrupts (spl0)
lw a1, _C_LABEL(curpcb)
nop
lw a0, U_PCB_REGS+(SR * 4)(a1)
lw s0, U_PCB_REGS+(S0 * 4)(a1)
mtc0 a0, MACH_COP_0_STATUS_REG # this should disable interrupts
mtc0 a0, MIPS_COP_0_STATUS_REG # this should disable interrupts
lw s1, U_PCB_REGS+(S1 * 4)(a1)
lw s2, U_PCB_REGS+(S2 * 4)(a1)
lw s3, U_PCB_REGS+(S3 * 4)(a1)
@ -748,12 +748,12 @@ _C_LABEL(mips1_exceptionentry_end):
NLEAF(mips1_TLBModException)
.set noat
tlbp # find the TLB entry
mfc0 k0, MACH_COP_0_TLB_LOW # get the physical address
mfc0 k1, MACH_COP_0_TLB_INDEX # check to be sure its valid
mfc0 k0, MIPS_COP_0_TLB_LOW # get the physical address
mfc0 k1, MIPS_COP_0_TLB_INDEX # check to be sure its valid
or k0, k0, MIPS1_TLB_MOD_BIT # update TLB
blt k1, zero, 4f # not found!!!
mtc0 k0, MACH_COP_0_TLB_LOW
li k1, MACH_CACHED_MEMORY_ADDR
mtc0 k0, MIPS_COP_0_TLB_LOW
li k1, MIPS_KSEG0_START
subu k0, k0, k1
srl k0, k0, MIPS1_TLB_PHYS_PAGE_SHIFT
la k1, pmap_attributes
@ -762,7 +762,7 @@ NLEAF(mips1_TLBModException)
nop
or k1, k1, 1 # set modified bit
sb k1, 0(k0) # save new value
mfc0 k0, MACH_COP_0_EXC_PC # get return address
mfc0 k0, MIPS_COP_0_EXC_PC # get return address
nop
j k0
rfe
@ -790,7 +790,7 @@ END(mips1_TLBModException)
*/
NLEAF(mips1_TLBMissException)
.set noat
mfc0 k0, MACH_COP_0_BAD_VADDR # get the fault address
mfc0 k0, MIPS_COP_0_BAD_VADDR # get the fault address
li k1, VM_MIN_KERNEL_ADDRESS # compute index
subu k0, k0, k1
lw k1, _C_LABEL(Sysmapsize) # index within range?
@ -802,8 +802,8 @@ NLEAF(mips1_TLBMissException)
sll k0, k0, 2 # compute offset from index
addu k1, k1, k0
lw k0, 0(k1) # get PTE entry
mfc0 k1, MACH_COP_0_EXC_PC # get return address
mtc0 k0, MACH_COP_0_TLB_LOW # save PTE entry
mfc0 k1, MIPS_COP_0_EXC_PC # get return address
mtc0 k0, MIPS_COP_0_TLB_LOW # save PTE entry
and k0, k0, MIPS1_PG_V # check for valid entry
beq k0, zero, _C_LABEL(mips1_KernGenException) # PTE invalid
nop
@ -821,15 +821,15 @@ NLEAF(mips1_TLBMissException)
sw sp, 24(a0)
move sp, a0
la a0, 1f
mfc0 a2, MACH_COP_0_STATUS_REG
mfc0 a3, MACH_COP_0_CAUSE_REG
mfc0 a1, MACH_COP_0_EXC_PC
mfc0 a2, MIPS_COP_0_STATUS_REG
mfc0 a3, MIPS_COP_0_CAUSE_REG
mfc0 a1, MIPS_COP_0_EXC_PC
sw a2, 16(sp)
sw a3, 20(sp)
sw sp, 24(sp)
move a2, ra
jal _C_LABEL(printf)
mfc0 a3, MACH_COP_0_BAD_VADDR
mfc0 a3, MIPS_COP_0_BAD_VADDR
.data
1:
.asciiz "ktlbmiss: PC %x RA %x ADR %x\nSR %x CR %x SP %x\n"
@ -861,20 +861,20 @@ END(mips1_TLBMissException)
*--------------------------------------------------------------------------
*/
LEAF(mips1_TLBWriteIndexed)
mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts
mfc0 t0, MACH_COP_0_TLB_HI # Save the current PID.
mfc0 v1, MIPS_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts
mfc0 t0, MIPS_COP_0_TLB_HI # Save the current PID.
sll a0, a0, MIPS1_TLB_INDEX_SHIFT
mtc0 a0, MACH_COP_0_TLB_INDEX # Set the index.
mtc0 a1, MACH_COP_0_TLB_HI # Set up entry high.
mtc0 a2, MACH_COP_0_TLB_LOW # Set up entry low.
mtc0 a0, MIPS_COP_0_TLB_INDEX # Set the index.
mtc0 a1, MIPS_COP_0_TLB_HI # Set up entry high.
mtc0 a2, MIPS_COP_0_TLB_LOW # Set up entry low.
nop
tlbwi # Write the TLB
mtc0 t0, MACH_COP_0_TLB_HI # Restore the PID.
mtc0 t0, MIPS_COP_0_TLB_HI # Restore the PID.
j ra
mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register
mtc0 v1, MIPS_COP_0_STATUS_REG # Restore the status register
END(mips1_TLBWriteIndexed)
#if 0
@ -897,19 +897,19 @@ END(mips1_TLBWriteIndexed)
*--------------------------------------------------------------------------
*/
LEAF(mips1_TLBWriteRandom)
mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts
mfc0 v0, MACH_COP_0_TLB_HI # Save the current PID.
mfc0 v1, MIPS_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts
mfc0 v0, MIPS_COP_0_TLB_HI # Save the current PID.
nop
mtc0 a0, MACH_COP_0_TLB_HI # Set up entry high.
mtc0 a1, MACH_COP_0_TLB_LOW # Set up entry low.
mtc0 a0, MIPS_COP_0_TLB_HI # Set up entry high.
mtc0 a1, MIPS_COP_0_TLB_LOW # Set up entry low.
nop
tlbwr # Write the TLB
mtc0 v0, MACH_COP_0_TLB_HI # Restore the PID.
mtc0 v0, MIPS_COP_0_TLB_HI # Restore the PID.
j ra
mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register
mtc0 v1, MIPS_COP_0_STATUS_REG # Restore the status register
END(mips1_TLBWriteRandom)
#endif
@ -932,7 +932,7 @@ END(mips1_TLBWriteRandom)
*/
LEAF(mips1_SetPID)
sll a0, a0, MIPS1_TLB_PID_SHIFT # put PID in right spot
mtc0 a0, MACH_COP_0_TLB_HI # Write the hi reg value
mtc0 a0, MIPS_COP_0_TLB_HI # Write the hi reg value
j ra
nop
END(mips1_SetPID)
@ -954,26 +954,26 @@ END(mips1_SetPID)
*--------------------------------------------------------------------------
*/
LEAF(mips1_TLBFlush)
mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts
mfc0 t0, MACH_COP_0_TLB_HI # Save the PID
li t1, MACH_CACHED_MEMORY_ADDR # invalid address
mtc0 t1, MACH_COP_0_TLB_HI # Mark entry high as invalid
mtc0 zero, MACH_COP_0_TLB_LOW # Zero out low entry.
mfc0 v1, MIPS_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts
mfc0 t0, MIPS_COP_0_TLB_HI # Save the PID
li t1, MIPS_KSEG0_START # invalid address
mtc0 t1, MIPS_COP_0_TLB_HI # Mark entry high as invalid
mtc0 zero, MIPS_COP_0_TLB_LOW # Zero out low entry.
/*
* Align the starting value (t1) and the upper bound (t2).
*/
li t1, MIPS1_TLB_FIRST_RAND_ENTRY << MIPS1_TLB_INDEX_SHIFT
li t2, MIPS1_TLB_NUM_TLB_ENTRIES << MIPS1_TLB_INDEX_SHIFT
1:
mtc0 t1, MACH_COP_0_TLB_INDEX # Set the index register.
mtc0 t1, MIPS_COP_0_TLB_INDEX # Set the index register.
addu t1, t1, 1 << MIPS1_TLB_INDEX_SHIFT # Increment index.
bne t1, t2, 1b
tlbwi # Write the TLB entry.
mtc0 t0, MACH_COP_0_TLB_HI # Restore the PID
mtc0 t0, MIPS_COP_0_TLB_HI # Restore the PID
j ra
mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register
mtc0 v1, MIPS_COP_0_STATUS_REG # Restore the status register
END(mips1_TLBFlush)
#if 0
@ -995,35 +995,35 @@ END(mips1_TLBFlush)
*--------------------------------------------------------------------------
*/
LEAF(mips1_TLBFlushPID)
mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts
mfc0 t0, MACH_COP_0_TLB_HI # Save the current PID
mfc0 v1, MIPS_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts
mfc0 t0, MIPS_COP_0_TLB_HI # Save the current PID
sll a0, a0, MIPS1_TLB_PID_SHIFT # Align the pid to flush.
/*
* Align the starting value (t1) and the upper bound (t2).
*/
li t1, MIPS1_TLB_FIRST_RAND_ENTRY << MIPS1_TLB_INDEX_SHIFT
li t2, MIPS1_TLB_NUM_TLB_ENTRIES << MIPS1_TLB_INDEX_SHIFT
mtc0 t1, MACH_COP_0_TLB_INDEX # Set the index register
mtc0 t1, MIPS_COP_0_TLB_INDEX # Set the index register
1:
addu t1, t1, 1 << MIPS1_TLB_INDEX_SHIFT # Increment index.
tlbr # Read from the TLB
mfc0 t4, MACH_COP_0_TLB_HI # Fetch the hi register.
mfc0 t4, MIPS_COP_0_TLB_HI # Fetch the hi register.
nop
and t4, t4, MIPS1_TLB_PID # compare PIDs
bne t4, a0, 2f
li v0, MACH_CACHED_MEMORY_ADDR # invalid address
mtc0 v0, MACH_COP_0_TLB_HI # Mark entry high as invalid
mtc0 zero, MACH_COP_0_TLB_LOW # Zero out low entry.
li v0, MIPS_KSEG0_START # invalid address
mtc0 v0, MIPS_COP_0_TLB_HI # Mark entry high as invalid
mtc0 zero, MIPS_COP_0_TLB_LOW # Zero out low entry.
nop
tlbwi # Write the entry.
2:
bne t1, t2, 1b
mtc0 t1, MACH_COP_0_TLB_INDEX # Set the index register
mtc0 t1, MIPS_COP_0_TLB_INDEX # Set the index register
mtc0 t0, MACH_COP_0_TLB_HI # restore PID
mtc0 t0, MIPS_COP_0_TLB_HI # restore PID
j ra
mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register
mtc0 v1, MIPS_COP_0_STATUS_REG # Restore the status register
END(mips1_TLBFlushPID)
#endif
@ -1045,25 +1045,25 @@ END(mips1_TLBFlushPID)
*--------------------------------------------------------------------------
*/
LEAF(mips1_TLBFlushAddr)
mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts
mfc0 t0, MACH_COP_0_TLB_HI # Get current PID
mfc0 v1, MIPS_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts
mfc0 t0, MIPS_COP_0_TLB_HI # Get current PID
nop
mtc0 a0, MACH_COP_0_TLB_HI # look for addr & PID
mtc0 a0, MIPS_COP_0_TLB_HI # look for addr & PID
nop
tlbp # Probe for the entry.
mfc0 v0, MACH_COP_0_TLB_INDEX # See what we got
li t1, MACH_CACHED_MEMORY_ADDR # Load invalid entry.
mfc0 v0, MIPS_COP_0_TLB_INDEX # See what we got
li t1, MIPS_KSEG0_START # Load invalid entry.
bltz v0, 1f # index < 0 => !found
mtc0 t1, MACH_COP_0_TLB_HI # Mark entry high as invalid
mtc0 zero, MACH_COP_0_TLB_LOW # Zero out low entry.
mtc0 t1, MIPS_COP_0_TLB_HI # Mark entry high as invalid
mtc0 zero, MIPS_COP_0_TLB_LOW # Zero out low entry.
nop
tlbwi
1:
mtc0 t0, MACH_COP_0_TLB_HI # restore PID
mtc0 t0, MIPS_COP_0_TLB_HI # restore PID
j ra
mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register
mtc0 v1, MIPS_COP_0_STATUS_REG # Restore the status register
END(mips1_TLBFlushAddr)
/*--------------------------------------------------------------------------
@ -1084,27 +1084,27 @@ END(mips1_TLBFlushAddr)
*--------------------------------------------------------------------------
*/
LEAF(mips1_TLBUpdate)
mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts
mfc0 t0, MACH_COP_0_TLB_HI # Save current PID
mfc0 v1, MIPS_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts
mfc0 t0, MIPS_COP_0_TLB_HI # Save current PID
nop # 2 cycles before intr disabled
mtc0 a0, MACH_COP_0_TLB_HI # init high reg.
mtc0 a0, MIPS_COP_0_TLB_HI # init high reg.
nop
tlbp # Probe for the entry.
mfc0 v0, MACH_COP_0_TLB_INDEX # See what we got
mtc0 a1, MACH_COP_0_TLB_LOW # init low reg.
mfc0 v0, MIPS_COP_0_TLB_INDEX # See what we got
mtc0 a1, MIPS_COP_0_TLB_LOW # init low reg.
bltz v0, 1f # index < 0 => !found
sra v0, v0, MIPS1_TLB_INDEX_SHIFT # convert index to regular num
b 2f
tlbwi # update slot found
1:
mtc0 a0, MACH_COP_0_TLB_HI # init high reg.
mtc0 a0, MIPS_COP_0_TLB_HI # init high reg.
nop
tlbwr # enter into a random slot
2:
mtc0 t0, MACH_COP_0_TLB_HI # restore PID
mtc0 t0, MIPS_COP_0_TLB_HI # restore PID
j ra
mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register
mtc0 v1, MIPS_COP_0_STATUS_REG # Restore the status register
END(mips1_TLBUpdate)
/*--------------------------------------------------------------------------
@ -1128,27 +1128,27 @@ END(mips1_TLBUpdate)
.comm tlbhi, 4
.comm tlblo, 4
LEAF(mips1_TLBFind)
mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts
mfc0 t0, MACH_COP_0_TLB_HI # Get current PID
mfc0 v1, MIPS_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts
mfc0 t0, MIPS_COP_0_TLB_HI # Get current PID
nop
mtc0 a0, MACH_COP_0_TLB_HI # Set up entry high.
mtc0 a0, MIPS_COP_0_TLB_HI # Set up entry high.
nop
tlbp # Probe for the entry.
mfc0 v0, MACH_COP_0_TLB_INDEX # See what we got
mfc0 v0, MIPS_COP_0_TLB_INDEX # See what we got
nop
bltz v0, 1f # not found
nop
tlbr # read TLB
mfc0 t1, MACH_COP_0_TLB_HI # See what we got
mfc0 t2, MACH_COP_0_TLB_LOW # See what we got
mfc0 t1, MIPS_COP_0_TLB_HI # See what we got
mfc0 t2, MIPS_COP_0_TLB_LOW # See what we got
sw t1, tlbhi
sw t2, tlblo
srl v0, v0, MIPS1_TLB_INDEX_SHIFT # convert index to regular num
1:
mtc0 t0, MACH_COP_0_TLB_HI # Restore current PID
mtc0 t0, MIPS_COP_0_TLB_HI # Restore current PID
j ra
mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register
mtc0 v1, MIPS_COP_0_STATUS_REG # Restore the status register
END(mips1_TLBFind)
/*--------------------------------------------------------------------------
@ -1169,22 +1169,22 @@ END(mips1_TLBFind)
*--------------------------------------------------------------------------
*/
LEAF(mips1_TLBRead)
mfc0 v1, MACH_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts
mfc0 t0, MACH_COP_0_TLB_HI # Get current PID
mfc0 v1, MIPS_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts
mfc0 t0, MIPS_COP_0_TLB_HI # Get current PID
sll a0, a0, MIPS1_TLB_INDEX_SHIFT
mtc0 a0, MACH_COP_0_TLB_INDEX # Set the index register
mtc0 a0, MIPS_COP_0_TLB_INDEX # Set the index register
nop
tlbr # Read from the TLB
mfc0 t3, MACH_COP_0_TLB_HI # fetch the hi entry
mfc0 t4, MACH_COP_0_TLB_LOW # fetch the low entry
mfc0 t3, MIPS_COP_0_TLB_HI # fetch the hi entry
mfc0 t4, MIPS_COP_0_TLB_LOW # fetch the low entry
sw t3, tlbhi
sw t4, tlblo
mtc0 t0, MACH_COP_0_TLB_HI # restore PID
mtc0 t0, MIPS_COP_0_TLB_HI # restore PID
j ra
mtc0 v1, MACH_COP_0_STATUS_REG # Restore the status register
mtc0 v1, MIPS_COP_0_STATUS_REG # Restore the status register
END(mips1_TLBRead)
/*--------------------------------------------------------------------------
@ -1202,7 +1202,7 @@ END(mips1_TLBRead)
*--------------------------------------------------------------------------
*/
LEAF(mips1_TLBGetPID)
mfc0 v0, MACH_COP_0_TLB_HI # get PID
mfc0 v0, MIPS_COP_0_TLB_HI # get PID
nop
and v0, v0, MIPS1_TLB_PID # mask off PID
j ra
@ -1238,9 +1238,9 @@ NON_LEAF(mips1_ConfigCache, STAND_FRAME_SIZE, ra)
subu sp, sp, STAND_FRAME_SIZE
sw ra, STAND_RA_OFFSET(sp) # Save return address.
.mask 0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE)
mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts.
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts.
la v0, 1f
or v0, MACH_UNCACHED_MEMORY_ADDR # Run uncached.
or v0, MIPS_KSEG1_START # Run uncached.
j v0
nop
1:
@ -1256,15 +1256,15 @@ NON_LEAF(mips1_ConfigCache, STAND_FRAME_SIZE, ra)
nop
nop
nop
li v0, MACH_SR_SWAP_CACHES # Swap caches
mtc0 v0, MACH_COP_0_STATUS_REG
li v0, MIPS_SR_SWAP_CACHES # Swap caches
mtc0 v0, MIPS_COP_0_STATUS_REG
nop # Insure caches stable
nop
nop
nop
jal _C_LABEL(mips1_SizeCache) # Get the size of the i-cache.
nop
mtc0 zero, MACH_COP_0_STATUS_REG # Swap back caches and enable.
mtc0 zero, MIPS_COP_0_STATUS_REG # Swap back caches and enable.
nop
nop
nop
@ -1295,20 +1295,20 @@ END(mips1_ConfigCache)
*----------------------------------------------------------------------------
*/
LEAF(mips1_SizeCache)
mfc0 t0, MACH_COP_0_STATUS_REG # Save the current status reg.
mfc0 t0, MIPS_COP_0_STATUS_REG # Save the current status reg.
nop
or v0, t0, MACH_SR_ISOL_CACHES # Isolate the caches.
or v0, t0, MIPS_SR_ISOL_CACHES # Isolate the caches.
nop # Make sure no stores in pipe
mtc0 v0, MACH_COP_0_STATUS_REG
mtc0 v0, MIPS_COP_0_STATUS_REG
nop # Make sure isolated
nop
nop
/*
* Clear cache size boundaries.
*/
li v0, MACH_MIN_CACHE_SIZE
li v1, MACH_CACHED_MEMORY_ADDR
li t2, MACH_MAX_CACHE_SIZE
li v0, MIPS_MIN_CACHE_SIZE
li v1, MIPS_KSEG0_START
li t2, MIPS_MAX_CACHE_SIZE
1:
addu t1, v0, v1 # Compute address to clear
sw zero, 0(t1) # Clear cache memory
@ -1317,7 +1317,7 @@ LEAF(mips1_SizeCache)
li v0, -1
sw v0, 0(v1) # Store marker in cache
li v0, MACH_MIN_CACHE_SIZE
li v0, MIPS_MIN_CACHE_SIZE
2:
addu t1, v0, v1 # Compute address
lw t3, 0(t1) # Look for marker
@ -1329,7 +1329,7 @@ LEAF(mips1_SizeCache)
move v0, zero # must be no cache
3:
mtc0 t0, MACH_COP_0_STATUS_REG
mtc0 t0, MIPS_COP_0_STATUS_REG
nop # Make sure unisolated
nop
nop
@ -1355,21 +1355,21 @@ END(mips1_SizeCache)
LEAF(mips1_FlushCache)
lw t1, _C_LABEL(mips_L1InstCacheSize) # Must load before isolating
lw t2, _C_LABEL(mips_L1DataCacheSize) # Must load before isolating
mfc0 t3, MACH_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts.
mfc0 t3, MIPS_COP_0_STATUS_REG # Save the status register.
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts.
la v0, 1f
or v0, MACH_UNCACHED_MEMORY_ADDR # Run uncached.
or v0, MIPS_KSEG1_START # Run uncached.
j v0
nop
/*
* Flush the instruction cache.
*/
1:
li v0, MACH_SR_ISOL_CACHES | MACH_SR_SWAP_CACHES
mtc0 v0, MACH_COP_0_STATUS_REG # Isolate and swap caches.
li t0, MACH_UNCACHED_MEMORY_ADDR
li v0, MIPS_SR_ISOL_CACHES | MIPS_SR_SWAP_CACHES
mtc0 v0, MIPS_COP_0_STATUS_REG # Isolate and swap caches.
li t0, MIPS_KSEG1_START
subu t0, t0, t1
li t1, MACH_UNCACHED_MEMORY_ADDR
li t1, MIPS_KSEG1_START
la v0, 1f # Run cached
j v0
nop
@ -1379,16 +1379,16 @@ LEAF(mips1_FlushCache)
sb zero, -4(t0)
la v0, 1f
or v0, MACH_UNCACHED_MEMORY_ADDR
or v0, MIPS_KSEG1_START
j v0 # Run uncached
nop
/*
* Flush the data cache.
*/
1:
li v0, MACH_SR_ISOL_CACHES
mtc0 v0, MACH_COP_0_STATUS_REG # Isolate and swap back caches
li t0, MACH_UNCACHED_MEMORY_ADDR
li v0, MIPS_SR_ISOL_CACHES
mtc0 v0, MIPS_COP_0_STATUS_REG # Isolate and swap back caches
li t0, MIPS_KSEG1_START
subu t0, t0, t2
la v0, 1f
j v0 # Back to cached mode
@ -1402,7 +1402,7 @@ LEAF(mips1_FlushCache)
nop # out of pipe.
nop
nop
mtc0 t3, MACH_COP_0_STATUS_REG # Restore status reg.
mtc0 t3, MIPS_COP_0_STATUS_REG # Restore status reg.
nop # Insure cache unisolated.
nop
nop
@ -1430,17 +1430,17 @@ END(mips1_FlushCache)
*----------------------------------------------------------------------------
*/
LEAF(mips1_FlushICache)
mfc0 t0, MACH_COP_0_STATUS_REG # Save SR
mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts.
mfc0 t0, MIPS_COP_0_STATUS_REG # Save SR
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts.
la v1, 1f
or v1, MACH_UNCACHED_MEMORY_ADDR # Run uncached.
or v1, MIPS_KSEG1_START # Run uncached.
j v1
nop
1:
bc0f 1b # make sure stores are complete
li v1, MACH_SR_ISOL_CACHES | MACH_SR_SWAP_CACHES
mtc0 v1, MACH_COP_0_STATUS_REG
li v1, MIPS_SR_ISOL_CACHES | MIPS_SR_SWAP_CACHES
mtc0 v1, MIPS_COP_0_STATUS_REG
nop
addu a1, a1, a0 # compute ending address
1:
@ -1448,7 +1448,7 @@ LEAF(mips1_FlushICache)
bne a0, a1, 1b
sb zero, -4(a0)
mtc0 t0, MACH_COP_0_STATUS_REG # enable interrupts
mtc0 t0, MIPS_COP_0_STATUS_REG # enable interrupts
j ra # return and run cached
nop
END(mips1_FlushICache)
@ -1472,16 +1472,16 @@ END(mips1_FlushICache)
*----------------------------------------------------------------------------
*/
LEAF(mips1_FlushDCache)
mfc0 t0, MACH_COP_0_STATUS_REG # Save SR
mtc0 zero, MACH_COP_0_STATUS_REG # Disable interrupts.
mfc0 t0, MIPS_COP_0_STATUS_REG # Save SR
mtc0 zero, MIPS_COP_0_STATUS_REG # Disable interrupts.
nop
1:
bc0f 1b # make sure stores are complete
# BUG: should drain write buffer.
# The insn above does not work on some all DEC machines, or all variants
# of the mips architecture.
li v1, MACH_SR_ISOL_CACHES
mtc0 v1, MACH_COP_0_STATUS_REG
li v1, MIPS_SR_ISOL_CACHES
mtc0 v1, MIPS_COP_0_STATUS_REG
nop
addu t1, a1, a0 # compute ending address
1:
@ -1498,7 +1498,7 @@ LEAF(mips1_FlushDCache)
nop # drain pipeline
nop
mtc0 t0, MACH_COP_0_STATUS_REG # enable interrupts
mtc0 t0, MIPS_COP_0_STATUS_REG # enable interrupts
nop
j ra # return and run cached
nop
@ -1547,7 +1547,7 @@ LEAF(mips1_proc_trampoline)
lw a0, U_PCB_REGS + (SR * 4)(a1)
lw t0, U_PCB_REGS + (MULLO * 4)(a1)
lw t1, U_PCB_REGS + (MULHI * 4)(a1)
mtc0 a0, MACH_COP_0_STATUS_REG # this should disable interrupts
mtc0 a0, MIPS_COP_0_STATUS_REG # this should disable interrupts
mtlo t0
mthi t1
nop
@ -1598,28 +1598,28 @@ LEAF(mips1_switch_exit)
la v1, _C_LABEL(nullproc) # !! SP runs on p->p_addr !!
lw t0, P_MD_UPTE+0(v1) # t0 = first u. pte
lw t1, P_MD_UPTE+4(v1) # t1 = 2nd u. pte
li v0, MACH_CACHED_MEMORY_ADDR # clear wired entries for pcb
mtc0 v0, MACH_COP_0_TLB_HI
mtc0 zero, MACH_COP_0_TLB_LOW
li v0, MIPS_KSEG0_START # clear wired entries for pcb
mtc0 v0, MIPS_COP_0_TLB_HI
mtc0 zero, MIPS_COP_0_TLB_LOW
li v0, 2 << MIPS1_TLB_INDEX_SHIFT
mtc0 v0, MACH_COP_0_TLB_INDEX # clear wired entry 2
mtc0 v0, MIPS_COP_0_TLB_INDEX # clear wired entry 2
nop
tlbwi
li v0, 3 << MIPS1_TLB_INDEX_SHIFT
mtc0 v0, MACH_COP_0_TLB_INDEX # clear wired entry 3
mtc0 v0, MIPS_COP_0_TLB_INDEX # clear wired entry 3
nop
tlbwi
li v0, UADDR # still using UADDR for kstack
nop
mtc0 zero, MACH_COP_0_TLB_INDEX # set the index register
mtc0 v0, MACH_COP_0_TLB_HI # init high entry
mtc0 t0, MACH_COP_0_TLB_LOW # init low entry
mtc0 zero, MIPS_COP_0_TLB_INDEX # set the index register
mtc0 v0, MIPS_COP_0_TLB_HI # init high entry
mtc0 t0, MIPS_COP_0_TLB_LOW # init low entry
li t0, 1 << MIPS1_TLB_INDEX_SHIFT
tlbwi # Write the TLB entry.
addu v0, v0, NBPG # 2nd HI entry
mtc0 t0, MACH_COP_0_TLB_INDEX # set the index register
mtc0 v0, MACH_COP_0_TLB_HI # init high entry
mtc0 t1, MACH_COP_0_TLB_LOW # init low entry
mtc0 t0, MIPS_COP_0_TLB_INDEX # set the index register
mtc0 v0, MIPS_COP_0_TLB_HI # init high entry
mtc0 t1, MIPS_COP_0_TLB_LOW # init low entry
subu v0, v0, NBPG # back to start of u-area
tlbwi # Write the TLB entry.
@ -1651,57 +1651,57 @@ END(mips1_switch_exit)
LEAF(mips1_cpu_switch_resume)
sll v0, v0, MIPS1_TLB_PID_SHIFT # v0 = aligned PID
or v0, v0, UADDR # v0 = first HI entry
mtc0 zero, MACH_COP_0_TLB_INDEX # set the index register
mtc0 v0, MACH_COP_0_TLB_HI # init high entry
mtc0 t0, MACH_COP_0_TLB_LOW # init low entry
mtc0 zero, MIPS_COP_0_TLB_INDEX # set the index register
mtc0 v0, MIPS_COP_0_TLB_HI # init high entry
mtc0 t0, MIPS_COP_0_TLB_LOW # init low entry
li s1, 1 << MIPS1_TLB_INDEX_SHIFT
tlbwi # Write the TLB entry.
addu v0, v0, NBPG # 2nd HI entry
mtc0 s1, MACH_COP_0_TLB_INDEX # set the index register
mtc0 v0, MACH_COP_0_TLB_HI # init high entry
mtc0 t1, MACH_COP_0_TLB_LOW # init low entry
mtc0 s1, MIPS_COP_0_TLB_INDEX # set the index register
mtc0 v0, MIPS_COP_0_TLB_HI # init high entry
mtc0 t1, MIPS_COP_0_TLB_LOW # init low entry
nop
tlbwi # Write the TLB entry.
# now map p_addr; may need to flush random TLB entries
andi v0, MIPS1_TLB_PID # mask PID
or v0, s0 # insert p_addr
mtc0 v0, MACH_COP_0_TLB_HI
mtc0 v0, MIPS_COP_0_TLB_HI
nop
tlbp # probe for entry
nop
mfc0 s1, MACH_COP_0_TLB_INDEX # see if we found it
mfc0 s1, MIPS_COP_0_TLB_INDEX # see if we found it
bltz s1, 1f # not found
li s1, MACH_CACHED_MEMORY_ADDR
mtc0 s1, MACH_COP_0_TLB_HI
mtc0 zero, MACH_COP_0_TLB_LOW
li s1, MIPS_KSEG0_START
mtc0 s1, MIPS_COP_0_TLB_HI
mtc0 zero, MIPS_COP_0_TLB_LOW
nop
tlbwi
nop
mtc0 v0, MACH_COP_0_TLB_HI # restore High
mtc0 v0, MIPS_COP_0_TLB_HI # restore High
1:
li s1, 2 << MIPS1_TLB_INDEX_SHIFT
mtc0 s1, MACH_COP_0_TLB_INDEX
mtc0 t0, MACH_COP_0_TLB_LOW
mtc0 s1, MIPS_COP_0_TLB_INDEX
mtc0 t0, MIPS_COP_0_TLB_LOW
nop
tlbwi
addu v0, v0, NBPG
mtc0 v0, MACH_COP_0_TLB_HI
mtc0 v0, MIPS_COP_0_TLB_HI
nop
tlbp # probe for entry
nop
mfc0 s1, MACH_COP_0_TLB_INDEX # see if we found it
mfc0 s1, MIPS_COP_0_TLB_INDEX # see if we found it
bltz s1, 1f # not found
li s1, MACH_CACHED_MEMORY_ADDR
mtc0 s1, MACH_COP_0_TLB_HI
mtc0 zero, MACH_COP_0_TLB_LOW
li s1, MIPS_KSEG0_START
mtc0 s1, MIPS_COP_0_TLB_HI
mtc0 zero, MIPS_COP_0_TLB_LOW
nop
tlbwi
nop
mtc0 v0, MACH_COP_0_TLB_HI # restore High
mtc0 v0, MIPS_COP_0_TLB_HI # restore High
1:
li s1, 3 << MIPS1_TLB_INDEX_SHIFT
mtc0 s1, MACH_COP_0_TLB_INDEX
mtc0 t1, MACH_COP_0_TLB_LOW
mtc0 s1, MIPS_COP_0_TLB_INDEX
mtc0 t1, MIPS_COP_0_TLB_LOW
nop
tlbwi
/*
@ -1723,7 +1723,7 @@ LEAF(mips1_cpu_switch_resume)
lw sp, U_PCB_CONTEXT+32(t0)
lw s8, U_PCB_CONTEXT+36(t0)
nop
mtc0 v0, MACH_COP_0_STATUS_REG
mtc0 v0, MIPS_COP_0_STATUS_REG
j ra
li v0, 1 # possible return to 'savectx()'
END(mips1_cpu_switch_resume)

422
sys/arch/mips/mips/locore_r4000.S
View File

File diff suppressed because it is too large Load Diff

10
sys/arch/mips/mips/mem.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mem.c,v 1.8 1997/05/24 08:57:59 jonathan Exp $ */
/* $NetBSD: mem.c,v 1.9 1997/06/22 07:43:00 jonathan Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -111,7 +111,7 @@ mmrw(dev, uio, flags)
c = iov->iov_len;
if (v + c > ctob(physmem))
return (EFAULT);
v += MACH_CACHED_MEMORY_ADDR;
v += MIPS_KSEG0_START;
error = uiomove((caddr_t)v, c, uio);
continue;
@ -119,11 +119,11 @@ mmrw(dev, uio, flags)
case 1:
v = uio->uio_offset;
c = min(iov->iov_len, MAXPHYS);
if (v < MACH_CACHED_MEMORY_ADDR)
if (v < MIPS_KSEG0_START)
return (EFAULT);
if (v + c > MACH_PHYS_TO_CACHED(avail_end +
if (v + c > MIPS_PHYS_TO_KSEG0(avail_end +
sizeof (struct msgbuf)) &&
(v < MACH_KSEG2_ADDR ||
(v < MIPS_KSEG2_START ||
!kernacc((caddr_t)v, c,
uio->uio_rw == UIO_READ ? B_READ : B_WRITE)))
return (EFAULT);

8
sys/arch/mips/mips/mips_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mips_machdep.c,v 1.14 1997/06/22 03:17:42 jonathan Exp $ */
/* $NetBSD: mips_machdep.c,v 1.15 1997/06/22 07:43:01 jonathan Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@ -72,7 +72,7 @@ mips1_vector_init()
*/
if (mips1_UTLBMissEnd - mips1_UTLBMiss > 0x80)
panic("startup: UTLB code too large");
bcopy(mips1_UTLBMiss, (char *)MACH_UTLB_MISS_EXC_VEC,
bcopy(mips1_UTLBMiss, (char *)MIPS_UTLB_MISS_EXC_VEC,
mips1_UTLBMissEnd - mips1_UTLBMiss);
bcopy(mips1_exception, (char *)MIPS1_GEN_EXC_VEC,
mips1_exceptionEnd - mips1_exception);
@ -137,7 +137,7 @@ mips3_vector_init()
if (mips3_TLBMissEnd - mips3_TLBMiss > 0x80)
panic("startup: UTLB code too large");
#endif
bcopy(mips3_TLBMiss, (char *)MACH_UTLB_MISS_EXC_VEC,
bcopy(mips3_TLBMiss, (char *)MIPS_UTLB_MISS_EXC_VEC,
mips3_TLBMissEnd - mips3_TLBMiss);
bcopy(mips3_exception, (char *)MIPS3_GEN_EXC_VEC,
@ -208,7 +208,7 @@ mips_vector_init()
cpu_arch = 1;
mips1_TLBFlush();
for (i = 0; i < MIPS1_TLB_FIRST_RAND_ENTRY; ++i)
mips1_TLBWriteIndexed(i, MACH_CACHED_MEMORY_ADDR, 0);
mips1_TLBWriteIndexed(i, MIPS_KSEG0_START, 0);
mips1_vector_init();
break;
#endif

22
sys/arch/mips/mips/pmap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.c,v 1.26 1997/06/22 03:17:43 jonathan Exp $ */
/* $NetBSD: pmap.c,v 1.27 1997/06/22 07:43:02 jonathan Exp $ */
/*
* Copyright (c) 1992, 1993
@ -222,7 +222,7 @@ pmap_bootstrap(firstaddr)
* phys_start and phys_end but its better to use kseg0 addresses
* rather than kernel virtual addresses mapped through the TLB.
*/
i = maxmem - mips_btop(MACH_CACHED_TO_PHYS(firstaddr));
i = maxmem - mips_btop(MIPS_KSEG0_TO_PHYS(firstaddr));
valloc(pv_table, struct pv_entry, i);
/*
@ -231,7 +231,7 @@ pmap_bootstrap(firstaddr)
firstaddr = mips_round_page(firstaddr);
bzero((caddr_t)start, firstaddr - start);
avail_start = MACH_CACHED_TO_PHYS(firstaddr);
avail_start = MIPS_KSEG0_TO_PHYS(firstaddr);
avail_end = mips_ptob(maxmem);
mem_size = avail_end - avail_start;
@ -278,7 +278,7 @@ pmap_bootstrap_alloc(size)
if (vm_page_startup_initialized)
panic("pmap_bootstrap_alloc: called after startup initialized");
val = MACH_PHYS_TO_CACHED(avail_start);
val = MIPS_PHYS_TO_KSEG0(avail_start);
size = round_page(size);
avail_start += size;
@ -375,7 +375,7 @@ pmap_pinit(pmap)
panic("pmap_pinit: segtab alloc failed");
pmap_zero_page(VM_PAGE_TO_PHYS(mem));
pmap->pm_segtab = stp = (struct segtab *)
MACH_PHYS_TO_CACHED(VM_PAGE_TO_PHYS(mem));
MIPS_PHYS_TO_KSEG0(VM_PAGE_TO_PHYS(mem));
i = mipspagesperpage * (NBPG / sizeof(struct segtab));
s = splimp();
while (--i != 0) {
@ -480,7 +480,7 @@ pmap_release(pmap)
(vm_offset_t)pte, PAGE_SIZE);
#endif
vm_page_free1(
PHYS_TO_VM_PAGE(MACH_CACHED_TO_PHYS(pte)));
PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS(pte)));
pmap->pm_segtab->seg_tab[i] = NULL;
}
@ -980,7 +980,7 @@ pmap_enter(pmap, va, pa, prot, wired)
*/
#ifdef MIPS1
if ((!CPUISMIPS3) && prot == (VM_PROT_READ | VM_PROT_EXECUTE)) {
MachFlushICache(MACH_PHYS_TO_CACHED(pa), PAGE_SIZE);
MachFlushICache(MIPS_PHYS_TO_KSEG0(pa), PAGE_SIZE);
}
#endif
@ -1030,7 +1030,7 @@ pmap_enter(pmap, va, pa, prot, wired)
panic("pmap_enter: segmap alloc failed");
pmap_zero_page(VM_PAGE_TO_PHYS(mem));
pmap_segmap(pmap, va) = pte = (pt_entry_t *)
MACH_PHYS_TO_CACHED(VM_PAGE_TO_PHYS(mem));
MIPS_PHYS_TO_KSEG0(VM_PAGE_TO_PHYS(mem));
#ifdef DIAGNOSTIC
for (i = 0; i < NPTEPG; i++) {
if ((pte+i)->pt_entry)
@ -1267,7 +1267,7 @@ pmap_zero_page(phys)
MachFlushDCache(phys, NBPG);
}
#endif
p = (int *)MACH_PHYS_TO_CACHED(phys);
p = (int *)MIPS_PHYS_TO_KSEG0(phys);
end = p + PAGE_SIZE / sizeof(int);
/* XXX blkclr()? */
do {
@ -1308,8 +1308,8 @@ pmap_copy_page(src, dst)
MachFlushDCache(src, NBPG);
}
#endif
s = (int *)MACH_PHYS_TO_CACHED(src);
d = (int *)MACH_PHYS_TO_CACHED(dst);
s = (int *)MIPS_PHYS_TO_KSEG0(src);
d = (int *)MIPS_PHYS_TO_KSEG0(dst);
end = s + PAGE_SIZE / sizeof(int);
do {
tmp0 = s[0];

50
sys/arch/mips/mips/trap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: trap.c,v 1.64 1997/06/22 03:17:45 jonathan Exp $ */
/* $NetBSD: trap.c,v 1.65 1997/06/22 07:43:04 jonathan Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -503,7 +503,7 @@ syscall(status, cause, opc, frame)
cnt.v_syscall++;
if (status & ((CPUISMIPS3) ? MIPS_SR_INT_IE : MIPS1_SR_INT_ENA_PREV))
splx(MIPS_SR_INT_IE | (status & MACH_HARD_INT_MASK));
splx(MIPS_SR_INT_IE | (status & MIPS_HARD_INT_MASK));
sticks = p->p_sticks;
if (DELAYBRANCH(cause))
@ -621,9 +621,9 @@ child_return(p)
}
#ifdef MIPS3
#define TRAPTYPE(x) (((x) & MIPS3_CR_EXC_CODE) >> MACH_CR_EXC_CODE_SHIFT)
#define TRAPTYPE(x) (((x) & MIPS3_CR_EXC_CODE) >> MIPS_CR_EXC_CODE_SHIFT)
#else
#define TRAPTYPE(x) (((x) & MIPS1_CR_EXC_CODE) >> MACH_CR_EXC_CODE_SHIFT)
#define TRAPTYPE(x) (((x) & MIPS1_CR_EXC_CODE) >> MIPS_CR_EXC_CODE_SHIFT)
#endif
#define KERNLAND(x) ((int)(x) < 0)
@ -666,7 +666,7 @@ trap(status, cause, vaddr, opc, frame)
}
if (status & ((CPUISMIPS3) ? MIPS_SR_INT_IE : MIPS1_SR_INT_ENA_PREV))
splx((status & MACH_HARD_INT_MASK) | MIPS_SR_INT_IE);
splx((status & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
switch (type) {
default:
@ -870,7 +870,7 @@ trap(status, cause, vaddr, opc, frame)
/* read break instruction */
instr = fuiword((caddr_t)va);
if (p->p_md.md_ss_addr != va || instr != MACH_BREAK_SSTEP) {
if (p->p_md.md_ss_addr != va || instr != MIPS_BREAK_SSTEP) {
sig = SIGTRAP;
break;
}
@ -886,7 +886,7 @@ trap(status, cause, vaddr, opc, frame)
rv = vm_map_protect(&p->p_vmspace->vm_map,
sa, ea, VM_PROT_DEFAULT, FALSE);
if (rv == KERN_SUCCESS) {
rv = suiword((caddr_t)va, MACH_BREAK_SSTEP);
rv = suiword((caddr_t)va, MIPS_BREAK_SSTEP);
(void)vm_map_protect(&p->p_vmspace->vm_map,
sa, ea, VM_PROT_READ|VM_PROT_EXECUTE, FALSE);
}
@ -919,13 +919,13 @@ trap(status, cause, vaddr, opc, frame)
sig = SIGILL;
break; /* SIGNAL */
case T_COP_UNUSABLE+T_USER:
if ((cause & MACH_CR_COP_ERR) != 0x10000000) {
if ((cause & MIPS_CR_COP_ERR) != 0x10000000) {
sig = SIGILL; /* only FPU instructions allowed */
break; /* SIGNAL */
}
switchfpregs(fpcurproc, p);
fpcurproc = p;
p->p_md.md_regs[PS] |= MACH_SR_COP_1_BIT;
p->p_md.md_regs[PS] |= MIPS_SR_COP_1_BIT;
p->p_md.md_flags |= MDP_FPUSED;
userret(p, opc, sticks);
return; /* GEN */
@ -980,7 +980,7 @@ interrupt(status, cause, pc, frame)
/* Device interrupt */
if (mips_hardware_intr)
splx((*mips_hardware_intr)(mask, pc, status, cause));
if (mask & MACH_INT_MASK_5) {
if (mask & MIPS_INT_MASK_5) {
intrcnt[FPU_INTR]++;
if (USERMODE(status))
MachFPInterrupt(status, cause, pc, frame->f_regs);
@ -991,8 +991,8 @@ interrupt(status, cause, pc, frame)
}
/* Network software interrupt */
if ((mask & MACH_SOFT_INT_MASK_1)
|| (netisr && (status & MACH_SOFT_INT_MASK_1))) {
if ((mask & MIPS_SOFT_INT_MASK_1)
|| (netisr && (status & MIPS_SOFT_INT_MASK_1))) {
register isr;
isr = netisr; netisr = 0; /* XXX need protect? */
clearsoftnet();
@ -1016,7 +1016,7 @@ interrupt(status, cause, pc, frame)
}
/* Software clock interrupt */
if (mask & MACH_SOFT_INT_MASK_0) {
if (mask & MIPS_SOFT_INT_MASK_0) {
clearsoftclock();
cnt.v_soft++;
intrcnt[SOFTCLOCK_INTR]++;
@ -1066,7 +1066,7 @@ trapDump(msg)
cause = (trp->cause & ((CPUISMIPS3) ?
MIPS3_CR_EXC_CODE : MIPS1_CR_EXC_CODE));
printf("%s: ADR %x PC %x CR %x SR %x\n",
trap_type[cause >> MACH_CR_EXC_CODE_SHIFT],
trap_type[cause >> MIPS_CR_EXC_CODE_SHIFT],
trp->vadr, trp->pc, trp->cause, trp->status);
printf(" RA %x SP %x code %d\n", trp->ra, trp->sp, trp->code);
}
@ -1108,7 +1108,7 @@ MachEmulateBranch(regsPtr, instPC, fpcCSR, allowNonBranch)
unsigned retAddr;
int condition;
inst.word = (instPC < MACH_CACHED_MEMORY_ADDR) ?
inst.word = (instPC < MIPS_KSEG0_START) ?
fuiword((caddr_t)instPC) : *(unsigned*)instPC;
#if 0
@ -1207,9 +1207,9 @@ MachEmulateBranch(regsPtr, instPC, fpcCSR, allowNonBranch)
case OP_BCx:
case OP_BCy:
if ((inst.RType.rt & COPz_BC_TF_MASK) == COPz_BC_TRUE)
condition = fpcCSR & MACH_FPC_COND_BIT;
condition = fpcCSR & MIPS_FPU_COND_BIT;
else
condition = !(fpcCSR & MACH_FPC_COND_BIT);
condition = !(fpcCSR & MIPS_FPU_COND_BIT);
if (condition)
retAddr = GetBranchDest((InstFmt *)instPC);
else
@ -1261,7 +1261,7 @@ mips_singlestep(p)
va = f->f_regs[PC] + sizeof(int);
p->p_md.md_ss_addr = va;
p->p_md.md_ss_instr = fuiword((caddr_t)va);
rv = suiword((caddr_t)va, MACH_BREAK_SSTEP);
rv = suiword((caddr_t)va, MIPS_BREAK_SSTEP);
if (rv < 0) {
vm_offset_t sa, ea;
sa = trunc_page((vm_offset_t)va);
@ -1269,7 +1269,7 @@ mips_singlestep(p)
rv = vm_map_protect(&p->p_vmspace->vm_map,
sa, ea, VM_PROT_DEFAULT, FALSE);
if (rv == KERN_SUCCESS) {
rv = suiword((caddr_t)va, MACH_BREAK_SSTEP);
rv = suiword((caddr_t)va, MIPS_BREAK_SSTEP);
(void)vm_map_protect(&p->p_vmspace->vm_map,
sa, ea, VM_PROT_READ|VM_PROT_EXECUTE, FALSE);
}
@ -1279,7 +1279,7 @@ mips_singlestep(p)
unsigned pc = f->f_regs[PC];
unsigned va = 0;
int rv;
int curinstr, bpinstr = MACH_BREAK_SSTEP;
int curinstr, bpinstr = MIPS_BREAK_SSTEP;
struct uio uio;
struct iovec iov;
@ -1931,7 +1931,7 @@ break_insert()
for (i = 0; i < MAXBRK; i++) {
if (brk_tab[i].addr != 0) {
brk_tab[i].inst = *(unsigned *)brk_tab[i].addr;
*(unsigned *)brk_tab[i].addr = MACH_BREAK_BRKPT;
*(unsigned *)brk_tab[i].addr = MIPS_BREAK_BRKPT;
MachFlushDCache(brk_tab[i].addr,4);
MachFlushICache(brk_tab[i].addr,4);
}
@ -2009,7 +2009,7 @@ mdbsetsstep(frame)
if ((int)va < 0) {
/* kernel address */
mdb_ss_instr = mdbpeek((caddr_t)va);
mdbpoke((caddr_t)va, MACH_BREAK_SSTEP);
mdbpoke((caddr_t)va, MIPS_BREAK_SSTEP);
MachFlushDCache(va, 4);
MachFlushICache(va, 4);
}
@ -2034,7 +2034,7 @@ mdbclrsstep(frame)
return(FALSE);
/* read break instruction */
if (mdbpeek((caddr_t)va) != MACH_BREAK_SSTEP)
if (mdbpeek((caddr_t)va) != MIPS_BREAK_SSTEP)
return(FALSE);
if ((int)va < 0) {
@ -2432,7 +2432,7 @@ static int ssandrun; /* Single step and run flag (when cont at brk) */
newaddr = frame->f_regs[PC];
switch (type) {
case T_BREAK:
if (*(int *)newaddr == MACH_BREAK_SOVER) {
if (*(int *)newaddr == MIPS_BREAK_SOVER) {
break_restore();
frame->f_regs[PC] += 4;
printf("\nStop break (panic)\n# ");
@ -2441,7 +2441,7 @@ static int ssandrun; /* Single step and run flag (when cont at brk) */
printf("\n# ");
break;
}
if (*(int *)newaddr == MACH_BREAK_BRKPT) {
if (*(int *)newaddr == MIPS_BREAK_BRKPT) {
break_restore();
printf("\rBRK %08x\t", newaddr);
if (mdbprintins(*(int *)newaddr, newaddr)) {

12
sys/arch/mips/mips/vm_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: vm_machdep.c,v 1.22 1997/06/21 04:24:45 mhitch Exp $ */
/* $NetBSD: vm_machdep.c,v 1.23 1997/06/22 07:43:06 jonathan Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -346,12 +346,12 @@ kvtophys(vm_offset_t kva)
pt_entry_t *pte;
vm_offset_t phys;
if (kva >= MACH_CACHED_MEMORY_ADDR && kva < MACH_UNCACHED_MEMORY_ADDR)
if (kva >= MIPS_KSEG0_START && kva < MIPS_KSEG1_START)
{
return (MACH_CACHED_TO_PHYS(kva));
return (MIPS_KSEG0_TO_PHYS(kva));
}
else if (kva >= MACH_UNCACHED_MEMORY_ADDR && kva < MACH_KSEG2_ADDR) {
return (MACH_UNCACHED_TO_PHYS(kva));
else if (kva >= MIPS_KSEG1_START && kva < MIPS_KSEG2_START) {
return (MIPS_KSEG1_TO_PHYS(kva));
}
else if (kva >= UADDR && kva < KERNELSTACK) {
int upage = (kva - UADDR) >> PGSHIFT;
@ -359,7 +359,7 @@ kvtophys(vm_offset_t kva)
pte = (pt_entry_t *)&curproc->p_md.md_upte[upage];
phys = pfn_to_vad(pte->pt_entry) | (kva & PGOFSET);
}
else if (kva >= MACH_KSEG2_ADDR /*&& kva < VM_MAX_KERNEL_ADDRESS*/) {
else if (kva >= MIPS_KSEG2_START /*&& kva < VM_MAX_KERNEL_ADDRESS*/) {
pte = kvtopte(kva);
if ((pte - Sysmap) > Sysmapsize) {

4
sys/arch/pmax/dev/bt478.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: bt478.c,v 1.8 1997/06/16 02:53:32 jonathan Exp $ */
/* $NetBSD: bt478.c,v 1.9 1997/06/22 07:42:25 jonathan Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -205,7 +205,7 @@ bt478InitColorMap (fi)
register VDACRegs *vdac = (VDACRegs *)(fi -> fi_vdac);
register int i;
*(volatile char *)MACH_PHYS_TO_UNCACHED
*(volatile char *)MIPS_PHYS_TO_KSEG1
(KN01_PHYS_COLMASK_START) = 0xff; /* XXX */
wbflush();

4
sys/arch/pmax/dev/cfb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cfb.c,v 1.24 1996/10/13 13:13:52 jonathan Exp $ */
/* $NetBSD: cfb.c,v 1.25 1997/06/22 07:42:26 jonathan Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -313,7 +313,7 @@ cfbinit(fi, cfbaddr, unit, silent)
* mapped into the user's address space uncached.
*/
fi->fi_fbu = (struct fbuaccess *)
MACH_PHYS_TO_UNCACHED(MACH_CACHED_TO_PHYS(&cfbu));
MIPS_PHYS_TO_KSEG1(MIPS_KSEG0_TO_PHYS(&cfbu));
/* This is glass-tty state but it's in the shared structure. Ick. */
fi->fi_fbu->scrInfo.max_row = 56;

8
sys/arch/pmax/dev/dc_ds.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: dc_ds.c,v 1.4 1996/10/14 17:28:46 jonathan Exp $ */
/* $NetBSD: dc_ds.c,v 1.5 1997/06/22 07:42:27 jonathan Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@ -49,11 +49,11 @@ dc_ds_consinit(dev)
#if defined(DEBUG) && 1 /* XXX untested */
printf("dc_ds(%d,%d): serial console at 0x%x\n",
minor(dev) >> 2, minor(dev) & 03,
MACH_PHYS_TO_UNCACHED(KN01_SYS_DZ));
MIPS_PHYS_TO_KSEG1(KN01_SYS_DZ));
#endif
/* let any pending PROM output from boot drain */
DELAY(100000);
dc_consinit(dev, (void *)MACH_PHYS_TO_UNCACHED(KN01_SYS_DZ));
dc_consinit(dev, (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_DZ));
return (1);
}
@ -93,7 +93,7 @@ dc_ds_attach(parent, self, aux)
dcaddr = (caddr_t)ca->ca_addr;
(void) dcattach(sc, (void*)MACH_PHYS_TO_UNCACHED(dcaddr),
(void) dcattach(sc, (void*)MIPS_PHYS_TO_KSEG1(dcaddr),
/* dtr/dsr mask: comm port only */
1 << DCCOMM_PORT,
/* rts/cts mask: none */

8
sys/arch/pmax/dev/dc_ioasic.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: dc_ioasic.c,v 1.4 1996/10/14 17:15:42 jonathan Exp $ */
/* $NetBSD: dc_ioasic.c,v 1.5 1997/06/22 07:42:28 jonathan Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@ -49,10 +49,10 @@ dc_ioasic_consinit(dev)
#if defined(DEBUG) && 0
printf("dc_ioasic(%d,%d): serial console at 0x%x\n",
minor(dev) >> 2, minor(dev) & 03,
MACH_PHYS_TO_UNCACHED(KN02_SYS_DZ));
MIPS_PHYS_TO_KSEG1(KN02_SYS_DZ));
DELAY(100000);
#endif
dc_consinit(dev, (void *)MACH_PHYS_TO_UNCACHED(KN02_SYS_DZ));
dc_consinit(dev, (void *)MIPS_PHYS_TO_KSEG1(KN02_SYS_DZ));
return(1);
}
@ -92,7 +92,7 @@ dc_ioasic_attach(parent, self, aux)
dcaddr = (caddr_t)d->iada_addr;
printf("address 0x%p\n", dcaddr);
(void) dcattach(sc, (void*)MACH_PHYS_TO_UNCACHED(dcaddr),
(void) dcattach(sc, (void*)MIPS_PHYS_TO_KSEG1(dcaddr),
/* dtr/dsr mask */ (1<< DCPRINTER_PORT) + (1 << DCCOMM_PORT),
#ifdef HW_FLOW_CONTROL
/* rts/cts mask */ (1<< DCPRINTER_PORT) + (1 << DCCOMM_PORT),

4
sys/arch/pmax/dev/dtop.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: dtop.c,v 1.23 1997/05/25 04:58:36 jonathan Exp $ */
/* $NetBSD: dtop.c,v 1.24 1997/06/22 07:42:29 jonathan Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -252,7 +252,7 @@ dtopattach(parent, self, aux)
int i;
sc->poll = (poll_reg_t)MACH_PHYS_TO_UNCACHED(XINE_REG_INTR);
sc->poll = (poll_reg_t)MIPS_PHYS_TO_KSEG1(XINE_REG_INTR);
sc->data = (data_reg_t)d->iada_addr;
for (i = 0; i < DTOP_MAX_DEVICES; i++)

4
sys/arch/pmax/dev/fb_usrreq.c
View File

@ -249,9 +249,9 @@ fbmmap(dev, off, prot)
len = mips_round_page(((vm_offset_t)fi->fi_fbu & PGOFSET)
+ sizeof(*fi->fi_fbu));
if (off < len)
return (int)mips_btop(MACH_CACHED_TO_PHYS(fi->fi_fbu) + off);
return (int)mips_btop(MIPS_KSEG0_TO_PHYS(fi->fi_fbu) + off);
off -= len;
if (off >= fi->fi_type.fb_size)
return (-1);
return (int)mips_btop(MACH_UNCACHED_TO_PHYS(fi->fi_pixels) + off);
return (int)mips_btop(MIPS_KSEG1_TO_PHYS(fi->fi_pixels) + off);
}

4
sys/arch/pmax/dev/mfb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mfb.c,v 1.25 1997/06/16 02:53:47 jonathan Exp $ */
/* $NetBSD: mfb.c,v 1.26 1997/06/22 07:42:31 jonathan Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -338,7 +338,7 @@ mfbinit(fi, mfbaddr, unit, silent)
* mapped into the user's address space uncached.
*/
fi->fi_fbu = (struct fbuaccess *)
MACH_PHYS_TO_UNCACHED(MACH_CACHED_TO_PHYS(&mfbu));
MIPS_PHYS_TO_KSEG1(MIPS_KSEG0_TO_PHYS(&mfbu));
/* This is glass-tty state but it's in the shared structure. Ick. */
fi->fi_fbu->scrInfo.max_row = 67;

12
sys/arch/pmax/dev/pm_ds.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pm_ds.c,v 1.4 1997/05/24 08:19:52 jonathan Exp $ */
/* $NetBSD: pm_ds.c,v 1.5 1997/06/22 07:42:32 jonathan Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@ -157,16 +157,16 @@ pminit(fi, unit, cold_console_flag)
/* Set address of frame buffer... */
fi->fi_unit = unit;
fi->fi_pixels = (caddr_t)MACH_PHYS_TO_UNCACHED(KN01_PHYS_FBUF_START);
fi->fi_base = (caddr_t)MACH_PHYS_TO_UNCACHED(KN01_SYS_PCC);
fi->fi_vdac = (caddr_t)MACH_PHYS_TO_UNCACHED(KN01_SYS_VDAC);
fi->fi_pixels = (caddr_t)MIPS_PHYS_TO_KSEG1(KN01_PHYS_FBUF_START);
fi->fi_base = (caddr_t)MIPS_PHYS_TO_KSEG1(KN01_SYS_PCC);
fi->fi_vdac = (caddr_t)MIPS_PHYS_TO_KSEG1(KN01_SYS_VDAC);
/* check for no frame buffer */
if (badaddr((char *)fi->fi_pixels, 4))
return (0);
/* Fill in the stuff that differs from monochrome to color. */
if (*(volatile u_short *)MACH_PHYS_TO_UNCACHED(KN01_SYS_CSR) &
if (*(volatile u_short *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR) &
KN01_CSR_MONO) {
fi->fi_type.fb_depth = 1;
}
@ -183,7 +183,7 @@ pminit(fi, unit, cold_console_flag)
* XXX can go away when MI support for d_mmap entrypoints added.
*/
fi->fi_fbu = (struct fbuaccess *)
MACH_PHYS_TO_UNCACHED(MACH_CACHED_TO_PHYS(&pmu));
MIPS_PHYS_TO_KSEG1(MIPS_KSEG0_TO_PHYS(&pmu));
fi->fi_glasstty = &pmfb;

4
sys/arch/pmax/dev/sfb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: sfb.c,v 1.19 1997/01/22 17:27:54 mhitch Exp $ */
/* $NetBSD: sfb.c,v 1.20 1997/06/22 07:42:32 jonathan Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -291,7 +291,7 @@ sfbinit(fi, base, unit, silent)
* mapped into the user's address space uncached.
*/
fi->fi_fbu = (struct fbuaccess *)
MACH_PHYS_TO_UNCACHED(MACH_CACHED_TO_PHYS(&sfbu));
MIPS_PHYS_TO_KSEG1(MIPS_KSEG0_TO_PHYS(&sfbu));
/* This is glass-tty state but it's in the shared structure. Ick. */
fi->fi_fbu->scrInfo.max_row = 67;

4
sys/arch/pmax/dev/sii.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: sii.c,v 1.25 1997/06/16 02:54:00 jonathan Exp $ */
/* $NetBSD: sii.c,v 1.26 1997/06/22 07:42:33 jonathan Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -240,7 +240,7 @@ old_siiattach(parent, self, aux)
register struct confargs *ca = aux;
register struct siisoftc *sc = (struct siisoftc *) self;
sc->sc_regs = (SIIRegs *)MACH_PHYS_TO_UNCACHED(ca->ca_addr);
sc->sc_regs = (SIIRegs *)MIPS_PHYS_TO_KSEG1(ca->ca_addr);
sc->sc_flags = sc->sc_dev.dv_cfdata->cf_flags;
siiattach(sc);

14
sys/arch/pmax/dev/sii_ds.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: sii_ds.c,v 1.2 1996/10/13 16:59:15 christos Exp $ */
/* $NetBSD: sii_ds.c,v 1.3 1997/06/22 07:42:34 jonathan Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@ -43,7 +43,7 @@ struct cfattach sii_ds_ca = {
/* define a safe address in the SCSI buffer for doing status & message DMA */
#define SII_BUF_ADDR (MACH_PHYS_TO_UNCACHED(KN01_SYS_SII_B_START) \
#define SII_BUF_ADDR (MIPS_PHYS_TO_KSEG1(KN01_SYS_SII_B_START) \
+ SII_MAX_DMA_XFER_LENGTH * 14)
/*
@ -64,10 +64,10 @@ sii_ds_match(parent, match, aux)
/* XXX check for bad address, untested */
siiaddr = (void *)ca->ca_addr;
if (siiaddr != (void *)MACH_PHYS_TO_UNCACHED(KN01_SYS_SII)) {
if (siiaddr != (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_SII)) {
printf("(siimatch: bad addr %x, substituting %x\n",
ca->ca_addr, MACH_PHYS_TO_UNCACHED(KN01_SYS_SII));
siiaddr = (void *)MACH_PHYS_TO_UNCACHED(KN01_SYS_SII);
ca->ca_addr, MIPS_PHYS_TO_KSEG1(KN01_SYS_SII));
siiaddr = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_SII);
}
if (badaddr(siiaddr, 4))
return (0);
@ -83,10 +83,10 @@ sii_ds_attach(parent, self, aux)
register struct confargs *ca = aux;
register struct siisoftc *sc = (struct siisoftc *) self;
sc->sc_regs = (SIIRegs *)MACH_PHYS_TO_UNCACHED(ca->ca_addr);
sc->sc_regs = (SIIRegs *)MIPS_PHYS_TO_KSEG1(ca->ca_addr);
/* set up scsi buffer. XXX Why statically allocated? */
sc->sc_buf = (void*)(MACH_PHYS_TO_UNCACHED(KN01_SYS_SII_B_START));
sc->sc_buf = (void*)(MIPS_PHYS_TO_KSEG1(KN01_SYS_SII_B_START));
siiattach(sc);

6
sys/arch/pmax/dev/xcfb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: xcfb.c,v 1.20 1996/10/14 01:39:57 mhitch Exp $ */
/* $NetBSD: xcfb.c,v 1.21 1997/06/22 07:42:35 jonathan Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -243,7 +243,7 @@ xcfbinit(fi, base, unit, silent)
* runs faster in cached address space, but the X server is going
* to blow away the data cache whenever it updates the screen, so..
*/
base = (char *) MACH_PHYS_TO_UNCACHED(XINE_PHYS_CFB_START);
base = (char *) MIPS_PHYS_TO_KSEG1(XINE_PHYS_CFB_START);
/* Fill in main frame buffer info struct. */
fi->fi_unit = unit;
@ -272,7 +272,7 @@ xcfbinit(fi, base, unit, silent)
* mapped into the user's address space uncached.
*/
fi->fi_fbu = (struct fbuaccess *)
MACH_PHYS_TO_UNCACHED(MACH_CACHED_TO_PHYS(&xcfbu));
MIPS_PHYS_TO_KSEG1(MIPS_KSEG0_TO_PHYS(&xcfbu));
/* This is glass-tty state but it's in the shared structure. Ick. */
fi->fi_fbu->scrInfo.max_row = 50;

6
sys/arch/pmax/include/tc_machdep.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: tc_machdep.h,v 1.6 1997/05/25 05:58:36 jonathan Exp $ */
/* $NetBSD: tc_machdep.h,v 1.7 1997/06/22 07:42:37 jonathan Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
@ -60,7 +60,7 @@
#ifndef __MACHINE_TC_MACHDEP_H__
#define __MACHINE_TC_MACHDEP_H__
#include <mips/cpuregs.h> /* defines MACH_PHYS_TO_UNCACHED */
#include <mips/cpuregs.h> /* defines MIPS_PHYS_TO_KSEG1 */
typedef int32_t tc_addr_t;
typedef int32_t tc_offset_t;
@ -78,7 +78,7 @@ typedef int32_t tc_offset_t;
#define TC_DENSE_TO_SPARSE(addr) (addr)
#define TC_PHYS_TO_UNCACHED(addr) MACH_PHYS_TO_UNCACHED(addr)
#define TC_PHYS_TO_UNCACHED(addr) MIPS_PHYS_TO_KSEG1(addr)
/*

6
sys/arch/pmax/pmax/clock.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: clock.c,v 1.18 1997/06/22 01:31:45 jonathan Exp $ */
/* $NetBSD: clock.c,v 1.19 1997/06/22 07:42:38 jonathan Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -229,11 +229,11 @@ clockattach(parent, self, aux)
#if NTC>0
if (parent->dv_cfdata->cf_driver != &mainbus_cd)
Mach_clock_addr = (struct chiptime *)
MACH_PHYS_TO_UNCACHED(d->iada_addr);
MIPS_PHYS_TO_KSEG1(d->iada_addr);
else
#endif
Mach_clock_addr = (struct chiptime *)
MACH_PHYS_TO_UNCACHED(ca->ca_addr);
MIPS_PHYS_TO_KSEG1(ca->ca_addr);
#ifdef pmax
printf("\n");

16
sys/arch/pmax/pmax/kadb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: kadb.c,v 1.4 1994/10/26 21:10:24 cgd Exp $ */
/* $NetBSD: kadb.c,v 1.5 1997/06/22 07:42:39 jonathan Exp $ */
/*-
* Copyright (c) 1991, 1993
@ -202,12 +202,12 @@ kdbprinttrap(causeReg, vadr)
int type, pc;
extern char *trap_type[];
type = (causeReg & MACH_CR_EXC_CODE) >> MACH_CR_EXC_CODE_SHIFT;
type = (causeReg & MIPS_CR_EXC_CODE) >> MIPS_CR_EXC_CODE_SHIFT;
/* check to see if we are entering kdb via kdbpanic() */
pc = kdbpcb.pcb_regs[PC];
if (type == T_BREAK && pc < 0) {
if (kdbpeek(pc) == MACH_BREAK_KDB)
if (kdbpeek(pc) == MIPS_BREAK_KDB)
kdbpcb.pcb_regs[PC] = pc + 4;
}
@ -236,12 +236,12 @@ kdbsetsstep()
if ((int)va < 0) {
/* kernel address */
kdb_ss_instr = kdbpeek(va);
kdbpoke((caddr_t)va, MACH_BREAK_SSTEP);
kdbpoke((caddr_t)va, MIPS_BREAK_SSTEP);
return;
}
kdb_ss_instr = fuiword(va);
i = suiword((caddr_t)va, MACH_BREAK_SSTEP);
i = suiword((caddr_t)va, MIPS_BREAK_SSTEP);
if (i < 0) {
register struct proc *p = curproc;
vm_offset_t sa, ea;
@ -252,7 +252,7 @@ kdbsetsstep()
rv = vm_map_protect(&p->p_vmspace->vm_map, sa, ea,
VM_PROT_DEFAULT, FALSE);
if (rv == KERN_SUCCESS) {
i = suiword((caddr_t)va, MACH_BREAK_SSTEP);
i = suiword((caddr_t)va, MIPS_BREAK_SSTEP);
(void) vm_map_protect(&p->p_vmspace->vm_map,
sa, ea, VM_PROT_READ|VM_PROT_EXECUTE, FALSE);
}
@ -270,7 +270,7 @@ kdbclrsstep()
/* ignore this trap if it is not a break trap */
cr = kdbvar[kdbvarchk('t')];
if ((cr & MACH_CR_EXC_CODE) != (T_BREAK << MACH_CR_EXC_CODE_SHIFT))
if ((cr & MIPS_CR_EXC_CODE) != (T_BREAK << MIPS_CR_EXC_CODE_SHIFT))
return;
/* fix pc if break instruction is in the delay slot */
@ -285,7 +285,7 @@ kdbclrsstep()
/* read break instruction */
instr = kdbpeek(va);
if (instr != MACH_BREAK_SSTEP)
if (instr != MIPS_BREAK_SSTEP)
return;
if ((int)va < 0) {

56
sys/arch/pmax/pmax/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.86 1997/06/22 03:17:37 jonathan Exp $ */
/* $NetBSD: machdep.c,v 1.87 1997/06/22 07:42:40 jonathan Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -377,7 +377,7 @@ mach_init(argc, argv, code, cv)
proc0.p_addr = proc0paddr = (struct user *)v;
curpcb = (struct pcb *)proc0.p_addr;
proc0.p_md.md_regs = proc0paddr->u_pcb.pcb_regs;
firstaddr = MACH_CACHED_TO_PHYS(v);
firstaddr = MIPS_KSEG0_TO_PHYS(v);
if (CPUISMIPS3) for (i = 0; i < UPAGES; i+=2) {
struct tlb tlb;
@ -436,7 +436,7 @@ mach_init(argc, argv, code, cv)
bzero(start, v - start);
if (CPUISMIPS3) {
mips3_FlushDCache(MACH_CACHED_TO_PHYS(start), v - start);
mips3_FlushDCache(MIPS_KSEG0_TO_PHYS(start), v - start);
mips3_HitFlushDCache(UADDR, UPAGES * NBPG);
}
@ -466,7 +466,7 @@ mach_init(argc, argv, code, cv)
* Initialize physmem_boardmax; assume no SIMM-bank limits.
* Adjst later in model-specific code if necessary.
*/
physmem_boardmax = MACH_MAX_MEM_ADDR;
physmem_boardmax = MIPS_MAX_MEM_ADDR;
/* check what model platform we are running on */
pmax_boardtype = ((i >> 16) & 0xff);
@ -488,7 +488,7 @@ mach_init(argc, argv, code, cv)
Mach_splstatclock = cpu_spl3;
Mach_clock_addr = (volatile struct chiptime *)
MACH_PHYS_TO_UNCACHED(KN01_SYS_CLOCK);
MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK);
strcpy(cpu_model, "3100");
break;
#endif /* DS3100 */
@ -509,7 +509,7 @@ mach_init(argc, argv, code, cv)
Mach_splclock = Mach_spl3;
Mach_splstatclock = Mach_spl3;
Mach_clock_addr = (volatile struct chiptime *)
MACH_PHYS_TO_UNCACHED(KN01_SYS_CLOCK);
MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK);
strcpy(cpu_model, "5100");
break;
#endif /* DS5100 */
@ -518,10 +518,10 @@ mach_init(argc, argv, code, cv)
case DS_3MAX: /* DS5000/200 3max */
{
volatile int *csr_addr =
(volatile int *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CSR);
(volatile int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
Mach_reset_addr =
(unsigned *)MACH_PHYS_TO_UNCACHED(KN02_SYS_ERRADR);
(unsigned *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR);
/* clear any memory errors from new-config probes */
*Mach_reset_addr = 0;
@ -541,7 +541,7 @@ mach_init(argc, argv, code, cv)
Mach_splclock = cpu_spl1;
Mach_splstatclock = cpu_spl1;
Mach_clock_addr = (volatile struct chiptime *)
MACH_PHYS_TO_UNCACHED(KN02_SYS_CLOCK);
MIPS_PHYS_TO_KSEG1(KN02_SYS_CLOCK);
}
strcpy(cpu_model, "5000/200");
@ -555,7 +555,7 @@ mach_init(argc, argv, code, cv)
tc_slot_phys_base[0] = KMIN_PHYS_TC_0_START;
tc_slot_phys_base[1] = KMIN_PHYS_TC_1_START;
tc_slot_phys_base[2] = KMIN_PHYS_TC_2_START;
ioasic_base = MACH_PHYS_TO_UNCACHED(KMIN_SYS_ASIC);
ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC);
mips_hardware_intr = kmin_intr;
tc_enable_interrupt = kmin_enable_intr;
kmin_tc3_imask = (KMIN_INTR_CLOCK | KMIN_INTR_PSWARN |
@ -574,7 +574,7 @@ mach_init(argc, argv, code, cv)
Mach_splclock = splhigh;
Mach_splstatclock = splhigh;
Mach_clock_addr = (volatile struct chiptime *)
MACH_PHYS_TO_UNCACHED(KMIN_SYS_CLOCK);
MIPS_PHYS_TO_KSEG1(KMIN_SYS_CLOCK);
/*
@ -585,7 +585,7 @@ mach_init(argc, argv, code, cv)
/* clear any memory errors from probes */
Mach_reset_addr =
(u_int*)MACH_PHYS_TO_UNCACHED(KMIN_REG_TIMEOUT);
(u_int*)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT);
(*Mach_reset_addr) = 0;
strcpy(cpu_model, (CPUISMIPS3)? "5000/150": "5000/1xx");
@ -598,10 +598,10 @@ mach_init(argc, argv, code, cv)
* XXX Do MAXINEs lose the same way?
*/
physmem_boardmax = KMIN_PHYS_MEMORY_END + 1;
if ((*(int*)(MACH_PHYS_TO_UNCACHED(KMIN_REG_MSR)) &
if ((*(int*)(MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) &
KMIN_MSR_SIZE_16Mb) == 0)
physmem_boardmax = physmem_boardmax >> 2;
physmem_boardmax = MACH_PHYS_TO_UNCACHED(physmem_boardmax);
physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax);
break;
#endif /* ds5000_100 */
@ -612,7 +612,7 @@ mach_init(argc, argv, code, cv)
tc_min_slot = XINE_TC_MIN;
tc_slot_phys_base[0] = XINE_PHYS_TC_0_START;
tc_slot_phys_base[1] = XINE_PHYS_TC_1_START;
ioasic_base = MACH_PHYS_TO_UNCACHED(XINE_SYS_ASIC);
ioasic_base = MIPS_PHYS_TO_KSEG1(XINE_SYS_ASIC);
mips_hardware_intr = xine_intr;
tc_enable_interrupt = xine_enable_intr;
@ -634,7 +634,7 @@ mach_init(argc, argv, code, cv)
Mach_splclock = cpu_spl3;
Mach_splstatclock = cpu_spl3;
Mach_clock_addr = (volatile struct chiptime *)
MACH_PHYS_TO_UNCACHED(XINE_SYS_CLOCK);
MIPS_PHYS_TO_KSEG1(XINE_SYS_CLOCK);
/*
* Initialize interrupts.
@ -643,7 +643,7 @@ mach_init(argc, argv, code, cv)
*(u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
/* clear any memory errors from probes */
Mach_reset_addr =
(u_int*)MACH_PHYS_TO_UNCACHED(XINE_REG_TIMEOUT);
(u_int*)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT);
(*Mach_reset_addr) = 0;
strcpy(cpu_model, (CPUISMIPS3) ? "5000/50": "5000/25");
@ -658,11 +658,11 @@ mach_init(argc, argv, code, cv)
tc_slot_phys_base[0] = KN03_PHYS_TC_0_START;
tc_slot_phys_base[1] = KN03_PHYS_TC_1_START;
tc_slot_phys_base[2] = KN03_PHYS_TC_2_START;
ioasic_base = MACH_PHYS_TO_UNCACHED(KN03_SYS_ASIC);
ioasic_base = MIPS_PHYS_TO_KSEG1(KN03_SYS_ASIC);
mips_hardware_intr = kn03_intr;
tc_enable_interrupt = kn03_enable_intr;
Mach_reset_addr =
(u_int *)MACH_PHYS_TO_UNCACHED(KN03_SYS_ERRADR);
(u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR);
*Mach_reset_addr = 0;
/*
@ -679,7 +679,7 @@ mach_init(argc, argv, code, cv)
Mach_splclock = cpu_spl1;
Mach_splstatclock = cpu_spl1;
Mach_clock_addr = (volatile struct chiptime *)
MACH_PHYS_TO_UNCACHED(KN03_SYS_CLOCK);
MIPS_PHYS_TO_KSEG1(KN03_SYS_CLOCK);
asic_init(0);
/*
@ -709,7 +709,7 @@ mach_init(argc, argv, code, cv)
* Be careful to save and restore the original contents for msgbuf.
*/
physmem = btoc((vm_offset_t)v - KERNBASE);
cp = (char *)MACH_PHYS_TO_UNCACHED(physmem << PGSHIFT);
cp = (char *)MIPS_PHYS_TO_KSEG1(physmem << PGSHIFT);
while (cp < (char *)physmem_boardmax) {
int j;
if (badaddr(cp, 4))
@ -764,7 +764,7 @@ mach_init(argc, argv, code, cv)
* Initialize error message buffer (at end of core).
*/
maxmem -= btoc(sizeof (struct msgbuf));
msgbufp = (struct msgbuf *)(MACH_PHYS_TO_CACHED(maxmem << PGSHIFT));
msgbufp = (struct msgbuf *)(MIPS_PHYS_TO_KSEG0(maxmem << PGSHIFT));
msgbufmapped = 1;
/*
@ -1497,7 +1497,7 @@ initcpu()
*(u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
break;
case DS_3MAX:
*(u_int *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CHKSYN) = 0;
*(u_int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CHKSYN) = 0;
wbflush();
break;
default:
@ -1624,7 +1624,7 @@ kn02_enable_intr(slotno, handler, sc, on)
int on;
{
register volatile int *p_csr =
(volatile int *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CSR);
(volatile int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
int csr;
int s;
@ -1685,11 +1685,11 @@ kmin_enable_intr(slotno, handler, sc, on)
switch (slotno) {
/* slots 0-2 don't interrupt through the IOASIC. */
case 0:
mask = MACH_INT_MASK_0; break;
mask = MIPS_INT_MASK_0; break;
case 1:
mask = MACH_INT_MASK_1; break;
mask = MIPS_INT_MASK_1; break;
case 2:
mask = MACH_INT_MASK_2; break;
mask = MIPS_INT_MASK_2; break;
case KMIN_SCSI_SLOT:
mask = (KMIN_INTR_SCSI | KMIN_INTR_SCSI_PTR_LOAD |
@ -1839,7 +1839,7 @@ kn03_tc_reset()
* Reset interrupts, clear any errors from newconf probes
*/
*(u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
*(unsigned *)MACH_PHYS_TO_UNCACHED(KN03_SYS_ERRADR) = 0;
*(unsigned *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
}

4
sys/arch/pmax/pmax/nameglue.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: nameglue.h,v 1.3 1996/10/13 03:39:52 christos Exp $ */
/* $NetBSD: nameglue.h,v 1.4 1997/06/22 07:42:41 jonathan Exp $ */
/*
* Use macros to glue names for "machine-independent" functions
@ -25,7 +25,7 @@
/*
* Map physical addresses to kernel-virtual addresses.
*/
#define KV(x) ((void *)MACH_PHYS_TO_UNCACHED(x))
#define KV(x) ((void *)MIPS_PHYS_TO_KSEG1(x))
/*
* Print debugging messages only if DEBUG defined on a pmax.

136
sys/arch/pmax/pmax/pmax_trap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmax_trap.c,v 1.46 1997/06/16 03:29:07 jonathan Exp $ */
/* $NetBSD: pmax_trap.c,v 1.47 1997/06/22 07:42:42 jonathan Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -203,7 +203,7 @@ kn01_intr(mask, pc, statusReg, causeReg)
extern struct cfdriver dc_cd;
/* handle clock interrupts ASAP */
if (mask & MACH_INT_MASK_3) {
if (mask & MIPS_INT_MASK_3) {
temp = c->regc; /* XXX clear interrupt bits */
cf.pc = pc;
cf.sr = statusReg;
@ -211,26 +211,26 @@ kn01_intr(mask, pc, statusReg, causeReg)
intrcnt[HARDCLOCK]++;
/* keep clock interrupts enabled when we return */
causeReg &= ~MACH_INT_MASK_3;
causeReg &= ~MIPS_INT_MASK_3;
}
/* If clock interrupts were enabled, re-enable them ASAP. */
splx(MACH_SR_INT_ENA_CUR | (statusReg & MACH_INT_MASK_3));
splx(MIPS_SR_INT_ENA_CUR | (statusReg & MIPS_INT_MASK_3));
#if NSII > 0
if (mask & MACH_INT_MASK_0) {
if (mask & MIPS_INT_MASK_0) {
intrcnt[SCSI_INTR]++;
siiintr(sii_cd.cd_devs[0]);
}
#endif /* NSII */
#if NLE_PMAX > 0
if (mask & MACH_INT_MASK_1) {
if (mask & MIPS_INT_MASK_1) {
/*
* tty interrupts were disabled by the splx() call
* that re-enables clock interrupts. A slip or ppp driver
* manipulating if queues should have called splimp(),
* which would mask out MACH_INT_MASK_1.
* which would mask out MIPS_INT_MASK_1.
*/
am7990_intr(tc_slot_info[1].sc);
intrcnt[LANCE_INTR]++;
@ -238,18 +238,18 @@ kn01_intr(mask, pc, statusReg, causeReg)
#endif /* NLE_PMAX */
#if NDC_DS > 0
if (mask & MACH_INT_MASK_2) {
if (mask & MIPS_INT_MASK_2) {
dcintr(dc_cd.cd_devs[0]);
intrcnt[SERIAL0_INTR]++;
}
#endif /* NDC_DS */
if (mask & MACH_INT_MASK_4) {
if (mask & MIPS_INT_MASK_4) {
pmax_errintr();
intrcnt[ERROR_INTR]++;
}
return ((statusReg & ~causeReg & MACH_HARD_INT_MASK) |
MACH_SR_INT_ENA_CUR);
return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
MIPS_SR_INT_ENA_CUR);
}
#endif /* DS3100 */
@ -273,8 +273,8 @@ kn02_intr(mask, pc, statusReg, causeReg)
static int warned = 0;
/* handle clock interrupts ASAP */
if (mask & MACH_INT_MASK_1) {
csr = *(unsigned *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CSR);
if (mask & MIPS_INT_MASK_1) {
csr = *(unsigned *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
if ((csr & KN02_CSR_PSWARN) && !warned) {
warned = 1;
printf("WARNING: power supply is overheating!\n");
@ -290,23 +290,23 @@ kn02_intr(mask, pc, statusReg, causeReg)
intrcnt[HARDCLOCK]++;
/* keep clock interrupts enabled when we return */
causeReg &= ~MACH_INT_MASK_1;
causeReg &= ~MIPS_INT_MASK_1;
}
/* If clock interrups were enabled, re-enable them ASAP. */
splx(MACH_SR_INT_ENA_CUR | (statusReg & MACH_INT_MASK_1));
splx(MIPS_SR_INT_ENA_CUR | (statusReg & MIPS_INT_MASK_1));
if (mask & MACH_INT_MASK_0) {
if (mask & MIPS_INT_MASK_0) {
static int intr_map[8] = { SLOT0_INTR, SLOT1_INTR, SLOT2_INTR,
/* these two bits reserved */
STRAY_INTR, STRAY_INTR,
SCSI_INTR, LANCE_INTR,
SERIAL0_INTR };
csr = *(unsigned *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CSR);
csr = *(unsigned *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
m = csr & (csr >> KN02_CSR_IOINTEN_SHIFT) & KN02_CSR_IOINT;
#if 0
*(unsigned *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CSR) =
*(unsigned *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) =
(csr & ~(KN02_CSR_WRESERVED | 0xFF)) |
(m << KN02_CSR_IOINTEN_SHIFT);
#endif
@ -320,17 +320,17 @@ kn02_intr(mask, pc, statusReg, causeReg)
printf("spurious interrupt %d\n", i);
}
#if 0
*(unsigned *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CSR) =
*(unsigned *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) =
csr & ~(KN02_CSR_WRESERVED | 0xFF);
#endif
}
if (mask & MACH_INT_MASK_3) {
if (mask & MIPS_INT_MASK_3) {
intrcnt[ERROR_INTR]++;
kn02_errintr();
}
return ((statusReg & ~causeReg & MACH_HARD_INT_MASK) |
MACH_SR_INT_ENA_CUR);
return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
MIPS_SR_INT_ENA_CUR);
}
/*
@ -346,9 +346,9 @@ kmin_intr(mask, pc, statusReg, causeReg)
register u_int intr;
register volatile struct chiptime *c = Mach_clock_addr;
volatile u_int *imaskp =
(volatile u_int *)MACH_PHYS_TO_UNCACHED(KMIN_REG_IMSK);
(volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK);
volatile u_int *intrp =
(volatile u_int *)MACH_PHYS_TO_UNCACHED(KMIN_REG_INTR);
(volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_INTR);
unsigned int old_mask;
struct clockframe cf;
int temp;
@ -358,9 +358,9 @@ kmin_intr(mask, pc, statusReg, causeReg)
*imaskp = kmin_tc3_imask |
(KMIN_IM0 & ~(KN03_INTR_TC_0|KN03_INTR_TC_1|KN03_INTR_TC_2));
if (mask & MACH_INT_MASK_4)
if (mask & MIPS_INT_MASK_4)
(*callv->_halt)((int *)0, 0);
if (mask & MACH_INT_MASK_3) {
if (mask & MIPS_INT_MASK_3) {
intr = *intrp;
/* masked interrupts are still observable */
@ -427,29 +427,29 @@ kmin_intr(mask, pc, statusReg, causeReg)
printf("%s\n", "Power supply overheating");
}
}
if ((mask & MACH_INT_MASK_0) && tc_slot_info[0].intr) {
if ((mask & MIPS_INT_MASK_0) && tc_slot_info[0].intr) {
(*tc_slot_info[0].intr)(tc_slot_info[0].sc);
intrcnt[SLOT0_INTR]++;
}
if ((mask & MACH_INT_MASK_1) && tc_slot_info[1].intr) {
if ((mask & MIPS_INT_MASK_1) && tc_slot_info[1].intr) {
(*tc_slot_info[1].intr)(tc_slot_info[1].sc);
intrcnt[SLOT1_INTR]++;
}
if ((mask & MACH_INT_MASK_2) && tc_slot_info[2].intr) {
if ((mask & MIPS_INT_MASK_2) && tc_slot_info[2].intr) {
(*tc_slot_info[2].intr)(tc_slot_info[2].sc);
intrcnt[SLOT2_INTR]++;
}
#if 0 /*XXX*/
if (mask & (MACH_INT_MASK_2|MACH_INT_MASK_1|MACH_INT_MASK_0))
if (mask & (MIPS_INT_MASK_2|MIPS_INT_MASK_1|MIPS_INT_MASK_0))
printf("kmin: slot intr, mask 0x%x\n",
mask &
(MACH_INT_MASK_2|MACH_INT_MASK_1|MACH_INT_MASK_0));
(MIPS_INT_MASK_2|MIPS_INT_MASK_1|MIPS_INT_MASK_0));
#endif
return ((statusReg & ~causeReg & MACH_HARD_INT_MASK) |
MACH_SR_INT_ENA_CUR);
return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
MIPS_SR_INT_ENA_CUR);
}
/*
@ -465,9 +465,9 @@ xine_intr(mask, pc, statusReg, causeReg)
register u_int intr;
register volatile struct chiptime *c = Mach_clock_addr;
volatile u_int *imaskp = (volatile u_int *)
MACH_PHYS_TO_UNCACHED(XINE_REG_IMSK);
MIPS_PHYS_TO_KSEG1(XINE_REG_IMSK);
volatile u_int *intrp = (volatile u_int *)
MACH_PHYS_TO_UNCACHED(XINE_REG_INTR);
MIPS_PHYS_TO_KSEG1(XINE_REG_INTR);
u_int old_mask;
struct clockframe cf;
int temp;
@ -475,24 +475,24 @@ xine_intr(mask, pc, statusReg, causeReg)
old_mask = *imaskp & xine_tc3_imask;
*imaskp = xine_tc3_imask;
if (mask & MACH_INT_MASK_4)
if (mask & MIPS_INT_MASK_4)
(*callv->_halt)((int *)0, 0);
/* handle clock interrupts ASAP */
if (mask & MACH_INT_MASK_1) {
if (mask & MIPS_INT_MASK_1) {
temp = c->regc; /* XXX clear interrupt bits */
cf.pc = pc;
cf.sr = statusReg;
hardclock(&cf);
intrcnt[HARDCLOCK]++;
/* keep clock interrupts enabled when we return */
causeReg &= ~MACH_INT_MASK_1;
causeReg &= ~MIPS_INT_MASK_1;
}
/* If clock interrups were enabled, re-enable them ASAP. */
splx(MACH_SR_INT_ENA_CUR | (statusReg & MACH_INT_MASK_1));
splx(MIPS_SR_INT_ENA_CUR | (statusReg & MIPS_INT_MASK_1));
if (mask & MACH_INT_MASK_3) {
if (mask & MIPS_INT_MASK_3) {
intr = *intrp;
/* masked interrupts are still observable */
intr &= old_mask;
@ -583,10 +583,10 @@ xine_intr(mask, pc, statusReg, causeReg)
intrcnt[LANCE_INTR]++;
}
}
if (mask & MACH_INT_MASK_2)
if (mask & MIPS_INT_MASK_2)
kn02ba_errintr();
return ((statusReg & ~causeReg & MACH_HARD_INT_MASK) |
MACH_SR_INT_ENA_CUR);
return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
MIPS_SR_INT_ENA_CUR);
}
#ifdef DS5000_240
@ -603,9 +603,9 @@ kn03_intr(mask, pc, statusReg, causeReg)
register u_int intr;
register volatile struct chiptime *c = Mach_clock_addr;
volatile u_int *imaskp = (volatile u_int *)
MACH_PHYS_TO_UNCACHED(KN03_REG_IMSK);
MIPS_PHYS_TO_KSEG1(KN03_REG_IMSK);
volatile u_int *intrp = (volatile u_int *)
MACH_PHYS_TO_UNCACHED(KN03_REG_INTR);
MIPS_PHYS_TO_KSEG1(KN03_REG_INTR);
u_int old_mask;
struct clockframe cf;
int temp;
@ -615,11 +615,11 @@ kn03_intr(mask, pc, statusReg, causeReg)
old_mask = *imaskp & kn03_tc3_imask;
*imaskp = kn03_tc3_imask;
if (mask & MACH_INT_MASK_4)
if (mask & MIPS_INT_MASK_4)
(*callv->_halt)((int *)0, 0);
/* handle clock interrupts ASAP */
if (mask & MACH_INT_MASK_1) {
if (mask & MIPS_INT_MASK_1) {
temp = c->regc; /* XXX clear interrupt bits */
cf.pc = pc;
cf.sr = statusReg;
@ -628,11 +628,11 @@ kn03_intr(mask, pc, statusReg, causeReg)
intrcnt[HARDCLOCK]++;
old_buscycle = latched_cycle_cnt - old_buscycle;
/* keep clock interrupts enabled when we return */
causeReg &= ~MACH_INT_MASK_1;
causeReg &= ~MIPS_INT_MASK_1;
}
/* If clock interrups were enabled, re-enable them ASAP. */
splx(MACH_SR_INT_ENA_CUR | (statusReg & MACH_INT_MASK_1));
splx(MIPS_SR_INT_ENA_CUR | (statusReg & MIPS_INT_MASK_1));
/*
* Check for late clock interrupts (allow 10% slop). Be careful
@ -641,7 +641,7 @@ kn03_intr(mask, pc, statusReg, causeReg)
* ticks to be missed.
*/
#ifdef notdef
if ((mask & MACH_INT_MASK_1) && old_buscycle > (tick+49) * 25) {
if ((mask & MIPS_INT_MASK_1) && old_buscycle > (tick+49) * 25) {
extern int msgbufmapped;
if(msgbufmapped && 0)
addlog("kn03: clock intr %d usec late\n",
@ -653,7 +653,7 @@ kn03_intr(mask, pc, statusReg, causeReg)
* and DMA pointers serviced as soon as possible.
*/
if (mask & MACH_INT_MASK_0) {
if (mask & MIPS_INT_MASK_0) {
intr = *intrp;
/* masked interrupts are still observable */
intr &= old_mask;
@ -753,10 +753,10 @@ kn03_intr(mask, pc, statusReg, causeReg)
printf("%s\n", "Power supply overheating");
}
}
if (mask & MACH_INT_MASK_3)
if (mask & MIPS_INT_MASK_3)
kn03_errintr();
return ((statusReg & ~causeReg & MACH_HARD_INT_MASK) |
MACH_SR_INT_ENA_CUR);
return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
MIPS_SR_INT_ENA_CUR);
}
#endif /* DS5000_240 */
@ -784,14 +784,14 @@ static void
pmax_errintr()
{
volatile u_short *sysCSRPtr =
(u_short *)MACH_PHYS_TO_UNCACHED(KN01_SYS_CSR);
(u_short *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR);
u_short csr;
csr = *sysCSRPtr;
if (csr & KN01_CSR_MERR) {
printf("Memory error at 0x%x\n",
*(unsigned *)MACH_PHYS_TO_UNCACHED(KN01_SYS_ERRADR));
*(unsigned *)MIPS_PHYS_TO_KSEG1(KN01_SYS_ERRADR));
panic("Mem error interrupt");
}
*sysCSRPtr = (csr & ~KN01_CSR_MBZ) | 0xff;
@ -803,9 +803,9 @@ kn02_errintr()
{
u_int erradr, chksyn, physadr;
erradr = *(u_int *)MACH_PHYS_TO_UNCACHED(KN02_SYS_ERRADR);
chksyn = *(u_int *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CHKSYN);
*(u_int *)MACH_PHYS_TO_UNCACHED(KN02_SYS_ERRADR) = 0;
erradr = *(u_int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR);
chksyn = *(u_int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CHKSYN);
*(u_int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0;
wbflush();
if (!(erradr & KN02_ERR_VALID))
@ -821,7 +821,7 @@ kn02_errintr()
(erradr & KN02_ERR_ECCERR) ? "ECC" : "timeout",
physadr);
if (erradr & KN02_ERR_ECCERR) {
*(u_int *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CHKSYN) = 0;
*(u_int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CHKSYN) = 0;
wbflush();
printf("ECC 0x%08x\n", chksyn);
@ -847,9 +847,9 @@ kn03_errintr()
{
u_int erradr, errsyn, physadr;
erradr = *(u_int *)MACH_PHYS_TO_UNCACHED(KN03_SYS_ERRADR);
errsyn = *(u_int *)MACH_PHYS_TO_UNCACHED(KN03_SYS_ERRSYN);
*(u_int *)MACH_PHYS_TO_UNCACHED(KN03_SYS_ERRADR) = 0;
erradr = *(u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR);
errsyn = *(u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRSYN);
*(u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
wbflush();
if (!(erradr & KN03_ERR_VALID))
@ -865,7 +865,7 @@ kn03_errintr()
(erradr & KN03_ERR_ECCERR) ? "ECC" : "timeout",
physadr);
if (erradr & KN03_ERR_ECCERR) {
*(u_int *)MACH_PHYS_TO_UNCACHED(KN03_SYS_ERRSYN) = 0;
*(u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRSYN) = 0;
wbflush();
printf(" ECC 0x%08x\n", errsyn);
@ -895,12 +895,12 @@ kn02ba_errintr()
register int mer, adr, siz;
static int errintr_cnt = 0;
siz = *(volatile int *)MACH_PHYS_TO_UNCACHED(KMIN_REG_MSR);
mer = *(volatile int *)MACH_PHYS_TO_UNCACHED(KMIN_REG_MER);
adr = *(volatile int *)MACH_PHYS_TO_UNCACHED(KMIN_REG_AER);
siz = *(volatile int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR);
mer = *(volatile int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MER);
adr = *(volatile int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_AER);
/* clear interrupt bit */
*(unsigned int *)MACH_PHYS_TO_UNCACHED(KMIN_REG_TIMEOUT) = 0;
*(unsigned int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
errintr_cnt++;
printf("(%d)%s%x [%x %x %x]\n", errintr_cnt,

4
sys/arch/pmax/tc/scc.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: scc.c,v 1.24 1997/06/16 04:30:15 jonathan Exp $ */
/* $NetBSD: scc.c,v 1.25 1997/06/22 07:42:44 jonathan Exp $ */
/*
* Copyright (c) 1991,1990,1989,1994,1995,1996 Carnegie Mellon University
@ -498,7 +498,7 @@ sccattach(parent, self, aux)
printf("\nattaching scc%d, currently PROM console\n", unit);
#endif /* defined(DEBUG) && defined(HAVE_RCONS)*/
sccaddr = (void*)MACH_PHYS_TO_UNCACHED(d->iada_addr);
sccaddr = (void*)MIPS_PHYS_TO_KSEG1(d->iada_addr);
#ifdef SPARSE
sccaddr = (void *)TC_DENSE_TO_SPARSE((tc_addr_t)sccaddr);
#endif

4
sys/arch/pmax/tc/tc.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: tc.c,v 1.13 1997/06/16 01:45:16 jonathan Exp $ */
/* $NetBSD: tc.c,v 1.14 1997/06/22 07:42:45 jonathan Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
@ -97,7 +97,7 @@ int consprobeslot __P((int slot));
#include <pmax/pmax/turbochannel.h>
/*#include <pmax/pmax/nameglue.h>*/
#define KV(x) ((tc_addr_t)MACH_PHYS_TO_UNCACHED(x))
#define KV(x) ((tc_addr_t)MIPS_PHYS_TO_KSEG1(x))

4
sys/arch/pmax/tc/tc_subr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: tc_subr.c,v 1.12 1997/06/16 01:45:19 jonathan Exp $ */
/* $NetBSD: tc_subr.c,v 1.13 1997/06/22 07:42:46 jonathan Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@ -73,7 +73,7 @@ static int tc_consprobeslot __P((tc_addr_t slotaddr));
/*#include <pmax/pmax/nameglue.h>*/
#define KV(x) ((tc_addr_t)MACH_PHYS_TO_UNCACHED(x))
#define KV(x) ((tc_addr_t)MIPS_PHYS_TO_KSEG1(x))

31
sys/dev/tc/asc_ioasic.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: asc_ioasic.c,v 1.8 1997/06/21 04:06:11 mhitch Exp $ */
/* $NetBSD: asc_ioasic.c,v 1.9 1997/06/22 07:44:04 jonathan Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@ -20,14 +20,14 @@
#include <dev/tc/ioasicvar.h>
#include <machine/autoconf.h>
#include <pmax/dev/device.h> /* XXX */
#include <pmax/dev/scsi.h> /* XXX */
#include <pmax/dev/device.h> /* XXX */
#include <pmax/dev/scsi.h> /* XXX */
#include <pmax/dev/ascreg.h> /* XXX */
#include <pmax/dev/ascreg.h> /* XXX */
#include <dev/tc/ascvar.h>
#include <mips/cpu.h> /* XXX CPUISMIPS3 */
#include <mips/locore.h> /* XXX XXX bus.h needs cache-consistency*/
#include <machine/cpu.h>
#include <machine/bus.h> /* bus, cache consistency, etc */
/*XXX*/
#include <pmax/pmax/asic.h> /* XXX ioasic register defs? */
@ -91,7 +91,7 @@ asc_ioasic_attach(parent, self, aux)
void *ascaddr;
int unit;
ascaddr = (void*)MACH_PHYS_TO_UNCACHED(d->iada_addr);
ascaddr = (void*)MIPS_PHYS_TO_KSEG1(d->iada_addr);
unit = asc->sc_dev.dv_unit;
/*
@ -105,7 +105,8 @@ asc_ioasic_attach(parent, self, aux)
* (2) timing based on turbochannel frequency
*/
asc->buff = (u_char *)MACH_PHYS_TO_CACHED(asc_iomem);
/* XXX why cached? Device registers must be uncached. */
asc->buff = (u_char *)MIPS_PHYS_TO_KSEG0(asc_iomem);
bufsiz = 8192;
*((volatile int *)IOASIC_REG_SCSI_DMAPTR(ioasic_base)) = -1;
*((volatile int *)IOASIC_REG_SCSI_DMANPTR(ioasic_base)) = -1;
@ -146,9 +147,9 @@ asic_dma_start(asc, state, cp, flag)
if (CPUISMIPS3)
mips3_HitFlushDCache((vm_offset_t)cp, state->dmalen);
#endif /* MIPS3 */
phys = MACH_CACHED_TO_PHYS(cp);
phys = MIPS_KSEG0_TO_PHYS(cp);
cp = (caddr_t)mips_trunc_page(cp + NBPG);
nphys = MACH_CACHED_TO_PHYS(cp);
nphys = MIPS_KSEG0_TO_PHYS(cp);
asc->dma_next = cp;
asc->dma_xfer = state->dmalen - (nphys - phys);
@ -179,7 +180,7 @@ asic_dma_end(asc, state, flag)
int nb;
*ssr &= ~IOASIC_CSR_DMAEN_SCSI;
to = (u_short *)MACH_PHYS_TO_CACHED(*dmap >> 3);
to = (u_short *)MIPS_PHYS_TO_KSEG0(*dmap >> 3);
*dmap = -1;
*((volatile int *)IOASIC_REG_SCSI_DMANPTR(ioasic_base)) = -1;
wbflush();
@ -187,12 +188,12 @@ asic_dma_end(asc, state, flag)
if (flag == ASCDMA_READ) {
#ifdef MIPS3
if (CPUISMIPS3)
MachFlushDCache(MACH_UNCACHED_TO_PHYS(state->dmaBufAddr),
MachFlushDCache(MIPS_KSEG1_TO_PHYS(state->dmaBufAddr),
state->dmalen);
else
#endif /* MIPS3 */
MachFlushDCache(MACH_PHYS_TO_CACHED(
MACH_UNCACHED_TO_PHYS(state->dmaBufAddr)),
MachFlushDCache(MIPS_PHYS_TO_KSEG0(
MIPS_KSEG1_TO_PHYS(state->dmaBufAddr)),
state->dmalen);
if ( (nb = *((int *)IOASIC_REG_SCSI_SCR(ioasic_base))) != 0) {
/* pick up last upto6 bytes, sigh. */
@ -229,7 +230,7 @@ asc_dma_intr()
*ssr &= ~IOASIC_CSR_DMAEN_SCSI;
} else {
asc->dma_next += NBPG;
next_phys = MACH_CACHED_TO_PHYS(asc->dma_next);
next_phys = MIPS_KSEG0_TO_PHYS(asc->dma_next);
}
*(volatile int *)IOASIC_REG_SCSI_DMANPTR(ioasic_base) =
IOASIC_DMA_ADDR(next_phys);

5
sys/dev/tc/asc_tc.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: asc_tc.c,v 1.4 1996/10/13 01:38:37 christos Exp $ */
/* $NetBSD: asc_tc.c,v 1.5 1997/06/22 07:44:05 jonathan Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@ -89,7 +89,8 @@ asc_tc_attach(parent, self, aux)
void *ascaddr;
int unit;
ascaddr = (void*)MACH_PHYS_TO_UNCACHED(t->ta_addr);
/* Use uncached address for chip registers. */
ascaddr = (void*)MIPS_PHYS_TO_KSEG1(t->ta_addr);
unit = asc->sc_dev.dv_unit;
/*