Include <machine/locore.h>, to force all MIPS cpu-model specific
locore calls to go via a locore-entry jumptable. Use mips_btop(), mips_round_page, mips_trunc_seg() instead of pmax_btop(), pmax_round_page, pmax_trunc_seg(). Add Per's software-readonly-bit mechanism, since the r2000 and r4000 hardware TLB entries are very different, and the r4k has no space for software bits in TLB entries. That is, this pmap code still won't work on r4000 machines. Some other solution, like another jump table for clients of the pmap code, is necessary.
This commit is contained in:
jonathan
parent
b4c4b28e43
commit
6bb09a3781
@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.9 1995/04/10 12:45:59 mycroft Exp $ */
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/* $NetBSD: pmap.c,v 1.10 1996/05/19 01:58:35 jonathan Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -79,7 +79,8 @@
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#include <vm/vm_page.h>
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#include <vm/vm_pageout.h>
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#include <machine/machConst.h>
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#include <mips/cpuregs.h>
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#include <machine/locore.h>
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#include <machine/pte.h>
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extern vm_page_t vm_page_alloc1 __P((void));
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@ -198,17 +199,17 @@ pmap_bootstrap(firstaddr)
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* phys_start and phys_end but its better to use kseg0 addresses
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* rather than kernel virtual addresses mapped through the TLB.
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*/
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i = maxmem - pmax_btop(MACH_CACHED_TO_PHYS(firstaddr));
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i = maxmem - mips_btop(MACH_CACHED_TO_PHYS(firstaddr));
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valloc(pv_table, struct pv_entry, i);
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/*
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* Clear allocated memory.
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*/
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firstaddr = pmax_round_page(firstaddr);
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firstaddr = mips_round_page(firstaddr);
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bzero((caddr_t)start, firstaddr - start);
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avail_start = MACH_CACHED_TO_PHYS(firstaddr);
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avail_end = pmax_ptob(maxmem);
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avail_end = mips_ptob(maxmem);
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mem_size = avail_end - avail_start;
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virtual_avail = VM_MIN_KERNEL_ADDRESS;
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@ -518,7 +519,7 @@ pmap_remove(pmap, sva, eva)
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panic("pmap_remove: uva not in range");
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#endif
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while (sva < eva) {
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nssva = pmax_trunc_seg(sva) + NBSEG;
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nssva = mips_trunc_seg(sva) + NBSEG;
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if (nssva == 0 || nssva > eva)
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nssva = eva;
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/*
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@ -686,7 +687,7 @@ pmap_protect(pmap, sva, eva, prot)
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panic("pmap_protect: uva not in range");
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#endif
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while (sva < eva) {
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nssva = pmax_trunc_seg(sva) + NBSEG;
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nssva = mips_trunc_seg(sva) + NBSEG;
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if (nssva == 0 || nssva > eva)
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nssva = eva;
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/*
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@ -717,6 +718,80 @@ pmap_protect(pmap, sva, eva, prot)
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}
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}
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#ifdef CPU_R4000
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/*
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* Return RO protection of page.
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*/
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int
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pmap_is_page_ro(pmap, va, entry)
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pmap_t pmap;
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vm_offset_t va;
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int entry;
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{
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return(entry & PG_RO);
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}
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/*
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* pmap_page_cache:
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*
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* Change all mappings of a page to cached/uncached.
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*/
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void
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pmap_page_cache(pa,mode)
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vm_offset_t pa;
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{
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register pv_entry_t pv;
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register pt_entry_t *pte;
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register vm_offset_t va;
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register unsigned entry;
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register unsigned newmode;
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int s;
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#ifdef DEBUG
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if (pmapdebug & (PDB_FOLLOW|PDB_ENTER))
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printf("pmap_page_uncache(%x)\n", pa);
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#endif
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if (!IS_VM_PHYSADDR(pa))
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return;
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newmode = mode & PV_UNCACHED ? PG_UNCACHED : PG_CACHED;
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pv = pa_to_pvh(pa);
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s = splimp();
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while (pv) {
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pv->pv_flags = (pv->pv_flags & ~PV_UNCACHED) | mode;
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if (!pv->pv_pmap->pm_segtab) {
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/*
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* Change entries in kernel pmap.
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*/
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pte = kvtopte(pv->pv_va);
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entry = pte->pt_entry;
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if (entry & PG_V) {
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entry = (entry & ~PG_CACHEMODE) | newmode;
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pte->pt_entry = entry;
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MachTLBUpdate(pv->pv_va, entry);
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}
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}
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else {
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if (pte = pmap_segmap(pv->pv_pmap, pv->pv_va)) {
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pte += (pv->pv_va >> PGSHIFT) & (NPTEPG - 1);
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entry = pte->pt_entry;
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if (entry & PG_V) {
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entry = (entry & ~PG_CACHEMODE) | newmode;
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pte->pt_entry = entry;
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if (pv->pv_pmap->pm_tlbgen == tlbpid_gen)
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MachTLBUpdate(pv->pv_va | (pv->pv_pmap->pm_tlbpid <<
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VMMACH_TLB_PID_SHIFT), entry);
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}
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}
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}
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pv = pv->pv_next;
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}
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splx(s);
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}
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#endif /* CPU_R4000 */
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/*
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* Insert the given physical page (p) at
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* the specified virtual address (v) in the
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@ -1288,7 +1363,7 @@ pmap_phys_address(ppn)
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if (pmapdebug & PDB_FOLLOW)
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printf("pmap_phys_address(%x)\n", ppn);
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#endif
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return (pmax_ptob(ppn));
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return (mips_ptob(ppn));
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}
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.9 1995/04/10 12:45:59 mycroft Exp $ */
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/* $NetBSD: pmap.c,v 1.10 1996/05/19 01:58:35 jonathan Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -79,7 +79,8 @@
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#include <vm/vm_page.h>
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#include <vm/vm_pageout.h>
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#include <machine/machConst.h>
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#include <mips/cpuregs.h>
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#include <machine/locore.h>
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#include <machine/pte.h>
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extern vm_page_t vm_page_alloc1 __P((void));
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@ -198,17 +199,17 @@ pmap_bootstrap(firstaddr)
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* phys_start and phys_end but its better to use kseg0 addresses
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* rather than kernel virtual addresses mapped through the TLB.
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*/
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i = maxmem - pmax_btop(MACH_CACHED_TO_PHYS(firstaddr));
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i = maxmem - mips_btop(MACH_CACHED_TO_PHYS(firstaddr));
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valloc(pv_table, struct pv_entry, i);
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/*
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* Clear allocated memory.
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*/
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firstaddr = pmax_round_page(firstaddr);
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firstaddr = mips_round_page(firstaddr);
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bzero((caddr_t)start, firstaddr - start);
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avail_start = MACH_CACHED_TO_PHYS(firstaddr);
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avail_end = pmax_ptob(maxmem);
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avail_end = mips_ptob(maxmem);
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mem_size = avail_end - avail_start;
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virtual_avail = VM_MIN_KERNEL_ADDRESS;
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@ -518,7 +519,7 @@ pmap_remove(pmap, sva, eva)
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panic("pmap_remove: uva not in range");
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#endif
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while (sva < eva) {
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nssva = pmax_trunc_seg(sva) + NBSEG;
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nssva = mips_trunc_seg(sva) + NBSEG;
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if (nssva == 0 || nssva > eva)
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nssva = eva;
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/*
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@ -686,7 +687,7 @@ pmap_protect(pmap, sva, eva, prot)
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panic("pmap_protect: uva not in range");
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#endif
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while (sva < eva) {
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nssva = pmax_trunc_seg(sva) + NBSEG;
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nssva = mips_trunc_seg(sva) + NBSEG;
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if (nssva == 0 || nssva > eva)
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nssva = eva;
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/*
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@ -717,6 +718,80 @@ pmap_protect(pmap, sva, eva, prot)
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}
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}
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#ifdef CPU_R4000
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/*
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* Return RO protection of page.
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*/
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int
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pmap_is_page_ro(pmap, va, entry)
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pmap_t pmap;
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vm_offset_t va;
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int entry;
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{
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return(entry & PG_RO);
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}
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/*
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* pmap_page_cache:
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*
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* Change all mappings of a page to cached/uncached.
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*/
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void
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pmap_page_cache(pa,mode)
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vm_offset_t pa;
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{
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register pv_entry_t pv;
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register pt_entry_t *pte;
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register vm_offset_t va;
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register unsigned entry;
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register unsigned newmode;
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int s;
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#ifdef DEBUG
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if (pmapdebug & (PDB_FOLLOW|PDB_ENTER))
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printf("pmap_page_uncache(%x)\n", pa);
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#endif
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if (!IS_VM_PHYSADDR(pa))
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return;
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newmode = mode & PV_UNCACHED ? PG_UNCACHED : PG_CACHED;
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pv = pa_to_pvh(pa);
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s = splimp();
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while (pv) {
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pv->pv_flags = (pv->pv_flags & ~PV_UNCACHED) | mode;
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if (!pv->pv_pmap->pm_segtab) {
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/*
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* Change entries in kernel pmap.
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*/
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pte = kvtopte(pv->pv_va);
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entry = pte->pt_entry;
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if (entry & PG_V) {
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entry = (entry & ~PG_CACHEMODE) | newmode;
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pte->pt_entry = entry;
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MachTLBUpdate(pv->pv_va, entry);
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}
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}
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else {
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if (pte = pmap_segmap(pv->pv_pmap, pv->pv_va)) {
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pte += (pv->pv_va >> PGSHIFT) & (NPTEPG - 1);
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entry = pte->pt_entry;
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if (entry & PG_V) {
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entry = (entry & ~PG_CACHEMODE) | newmode;
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pte->pt_entry = entry;
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if (pv->pv_pmap->pm_tlbgen == tlbpid_gen)
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MachTLBUpdate(pv->pv_va | (pv->pv_pmap->pm_tlbpid <<
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VMMACH_TLB_PID_SHIFT), entry);
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}
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}
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}
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pv = pv->pv_next;
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}
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splx(s);
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}
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#endif /* CPU_R4000 */
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/*
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* Insert the given physical page (p) at
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* the specified virtual address (v) in the
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@ -1288,7 +1363,7 @@ pmap_phys_address(ppn)
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if (pmapdebug & PDB_FOLLOW)
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printf("pmap_phys_address(%x)\n", ppn);
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#endif
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return (pmax_ptob(ppn));
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return (mips_ptob(ppn));
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}
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/*
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