mips pmap_activate:
* prototype and definition for pmap_activate(p). Updates the segtab, and changes the active ASID if p == curproc. * Make reserved fixed-address (UADDR) kernelstack PTEs global, so we still have a kernel stack after pmap_activate() on curproc. * make KSEG2 mappings for p_addr global (see above.) Seems to detune contextswitch and NTP resolution (by 60 ms), but thepmap_activate() interface is mandatory. Needs more thought.
This commit is contained in:
jonathan
parent
cbb2b5d0fb
commit
003ccf3b1c
@ -1,4 +1,4 @@
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/* $NetBSD: pmap.h,v 1.14 1997/07/29 01:43:26 mhitch Exp $ */
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/* $NetBSD: pmap.h,v 1.15 1997/08/09 03:41:02 jonathan Exp $ */
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/*
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* Copyright (c) 1987 Carnegie-Mellon University
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@ -122,6 +122,8 @@ void pmap_prefer __P((vm_offset_t, vm_offset_t *));
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#endif /* MIPS3 */
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void pmap_activate __P((register struct proc *p));
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/*
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* Kernel cache operations for the user-space API
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*/
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.S,v 1.44 1997/08/08 06:52:59 jonathan Exp $ */
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/* $NetBSD: locore.S,v 1.45 1997/08/09 03:41:03 jonathan Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -760,13 +760,13 @@ sw1:
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jal _C_LABEL(pmap_alloc_tlbpid) # v0 = TLB PID
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move s0, a0 # BDSLOT: save p
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sw s0, _C_LABEL(curproc) # set curproc
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lw t0, P_MD_UPTE+0(s0) # t0 = first u. pte
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lw t1, P_MD_UPTE+4(s0) # t1 = 2nd u. pte
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lw s0, P_ADDR(s0)
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lw a1, P_MD_UPTE+0(s0) # a1 = first u. pte
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lw a2, P_MD_UPTE+4(s0) # a2 = 2nd u. pte
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lw a0, P_ADDR(s0) # a0 = p_addr
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lw s1, _C_LABEL(mips_locore_jumpvec) + MIPSX_CPU_SWITCH_RESUME
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sw s0, _C_LABEL(curpcb) # set curpcb
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sw a0, _C_LABEL(curpcb) # set curpcb
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jr s1 # CPU-specific: resume process
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nop
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move a3, v0 # BDSLOT: a3 = TLB PID
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END(cpu_switch)
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/*
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@ -1492,17 +1492,18 @@ END(splx)
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*
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* Return the current value of the cause register.
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*
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* mips_read_causereg(void)
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* int mips_read_causereg(void)
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*
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* Results:
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* current value of Cause register.None.
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*
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* Side effects:
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* None.
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* Not profiled, skews CPU-clock measurement to uselessness.
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*
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*----------------------------------------------------------------------------
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*/
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LEAF(mips_read_causereg)
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NLEAF(mips_read_causereg)
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mfc0 v0, MIPS_COP_0_CAUSE_REG
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j ra
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nop
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@ -1,4 +1,4 @@
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/* $NetBSD: locore_r2000.S,v 1.39 1997/07/20 19:48:13 jonathan Exp $ */
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/* $NetBSD: locore_r2000.S,v 1.40 1997/08/09 03:41:05 jonathan Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -1645,9 +1645,10 @@ END(mips1_switch_exit)
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* Also, there should be no TLB faults at this point.
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*
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* Entered from CPU-common cpu_switch()
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* v0 = TLB Process ID for this process
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* t0 = First u.pte
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* t1 = Second u.pte
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* a0 = p_addr [curpcb]
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* a1 = First u.pte
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* a2 = Second u.pte
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* a3 = TLB Process ID for this process
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*/
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/*
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* XXXX - almost done with the UADDR mapping; only the kernel stack should
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@ -1656,27 +1657,29 @@ END(mips1_switch_exit)
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* map the current u-area. Also, any current mapping for the u-area
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* address space needs to be flushed as well.
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*
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* Both the UADDR and u-area are now mapped global.
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*
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* NB: cannot be profiled due to weird argument-assing convention.
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* mcount would trash v0, t0, t1.
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*/
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NLEAF(mips1_cpu_switch_resume)
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sll v0, v0, MIPS1_TLB_PID_SHIFT # v0 = aligned PID
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or v0, v0, UADDR # v0 = first HI entry
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sll a3, a3, MIPS1_TLB_PID_SHIFT # a3 = aligned PID
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li v0, UADDR # HI entry; PID = 0
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ori a1, MIPS1_PG_G # Global
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ori a2, MIPS1_PG_G # Global
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mtc0 zero, MIPS_COP_0_TLB_INDEX # set the index register
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mtc0 v0, MIPS_COP_0_TLB_HI # init high entry
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mtc0 t0, MIPS_COP_0_TLB_LOW # init low entry
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mtc0 a1, MIPS_COP_0_TLB_LOW # init low entry
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li s1, 1 << MIPS1_TLB_INDEX_SHIFT
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tlbwi # Write the TLB entry.
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addu v0, v0, NBPG # 2nd HI entry
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mtc0 s1, MIPS_COP_0_TLB_INDEX # set the index register
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mtc0 v0, MIPS_COP_0_TLB_HI # init high entry
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mtc0 t1, MIPS_COP_0_TLB_LOW # init low entry
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mtc0 a2, MIPS_COP_0_TLB_LOW # init low entry
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nop
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tlbwi # Write the TLB entry.
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# now map p_addr; may need to flush random TLB entries
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andi v0, MIPS1_TLB_PID # mask PID
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or v0, s0 # insert p_addr
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mtc0 v0, MIPS_COP_0_TLB_HI
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mtc0 a0, MIPS_COP_0_TLB_HI # PID = 0
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nop
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tlbp # probe for entry
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mfc0 s1, MIPS_COP_0_TLB_INDEX # see if we found it
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@ -1688,15 +1691,15 @@ NLEAF(mips1_cpu_switch_resume)
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nop
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tlbwi
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nop
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mtc0 v0, MIPS_COP_0_TLB_HI # restore High
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mtc0 a0, MIPS_COP_0_TLB_HI # restore High
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1:
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li s1, 2 << MIPS1_TLB_INDEX_SHIFT
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mtc0 s1, MIPS_COP_0_TLB_INDEX
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mtc0 t0, MIPS_COP_0_TLB_LOW
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mtc0 a1, MIPS_COP_0_TLB_LOW
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nop
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tlbwi
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addu v0, v0, NBPG
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mtc0 v0, MIPS_COP_0_TLB_HI
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addu a0, a0, NBPG
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mtc0 a0, MIPS_COP_0_TLB_HI # second page of p_addr
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nop
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tlbp # probe for entry
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mfc0 s1, MIPS_COP_0_TLB_INDEX # see if we found it
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@ -1708,13 +1711,14 @@ NLEAF(mips1_cpu_switch_resume)
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nop
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tlbwi
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nop
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mtc0 v0, MIPS_COP_0_TLB_HI # restore High
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mtc0 a0, MIPS_COP_0_TLB_HI # restore High
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1:
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li s1, 3 << MIPS1_TLB_INDEX_SHIFT
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mtc0 s1, MIPS_COP_0_TLB_INDEX
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mtc0 t1, MIPS_COP_0_TLB_LOW
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mtc0 a2, MIPS_COP_0_TLB_LOW
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nop
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tlbwi
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mtc0 a3, MIPS_COP_0_TLB_HI # set PID [UADDR/pcb GLOBAL]
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/*
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* Now running on new u struct.
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* Restore registers and return.
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@ -1,4 +1,4 @@
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/* $NetBSD: locore_r4000.S,v 1.40 1997/07/20 19:48:08 jonathan Exp $ */
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/* $NetBSD: locore_r4000.S,v 1.41 1997/08/09 03:41:07 jonathan Exp $ */
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/*
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* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
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@ -2155,9 +2155,10 @@ END(mips3_switch_exit)
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* Also, there should be no TLB faults at this point.
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*
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* Entered from CPU-common cpu_switch()
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* v0 = Address Space Identifier (TLB PID) for this process
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* t0 = First u.pte
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* t1 = Second u.pte
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* a0 = p_addr [curpcb]
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* a1 = First u.pte
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* a2 = Second u.pte
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* a3 = Address Space Identifier (TLB PID) for this process
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*/
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/*
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* XXXX - almost done with the UADDR mapping; only the kernel stack should
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@ -2168,15 +2169,19 @@ END(mips3_switch_exit)
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* begins on an even or odd page. Also, any current mapping for the u-area
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* address space needs to be flushed as well.
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*
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* Both UADDR and p_addr are mapped global.
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*
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* NB: cannot be profiled due to weird argument-assing convention.
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* mcount would trash v0, t0, t1.
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*/
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NLEAF(mips3_cpu_switch_resume)
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or v0, v0, UADDR # v0 = first HI entry
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li v0, UADDR # Hi entry = UADD, ASID = 0
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ori a1, MIPS3_PG_G # set PG_G
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ori a2, MIPS3_PG_G # set PG_G
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mtc0 zero, MIPS_COP_0_TLB_INDEX # set the index register
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mtc0 v0, MIPS_COP_0_TLB_HI # init high entry
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mtc0 t0, MIPS_COP_0_TLB_LO0 # init low entry 0
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mtc0 t1, MIPS_COP_0_TLB_LO1 # init low entry 1
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mtc0 a1, MIPS_COP_0_TLB_LO0 # init low entry 0
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mtc0 a2, MIPS_COP_0_TLB_LO1 # init low entry 1
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nop
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nop
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tlbwi # Write the TLB entry.
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@ -2185,17 +2190,13 @@ NLEAF(mips3_cpu_switch_resume)
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nop
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nop
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# now map the p_addr pages
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andi v0, PG_ASID
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or v0, s0
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ori t0, MIPS3_PG_G # XXX set PG_G
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ori t1, MIPS3_PG_G # XXX set PG_G
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li s1, MIPS3_PG_ODDPG
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and s1, v0 # does p_addr start on odd page
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and s1, a0 # does p_addr start on odd page
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beq s1, zero, 1f # no, only one TLB entry needed
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# p_addr starts on an odd page, need to set up 2 TLB entries
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addu v0, v0, MIPS3_PG_ODDPG # map second page
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addu a0, a0, MIPS3_PG_ODDPG # map second page
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# see if this address currently exists in TLB
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mtc0 v0, MIPS_COP_0_TLB_HI
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mtc0 a0, MIPS_COP_0_TLB_HI
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nop
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tlbp # probe for existing entry
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nop
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@ -2211,22 +2212,22 @@ NLEAF(mips3_cpu_switch_resume)
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nop
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tlbwi
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nop
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mtc0 v0, MIPS_COP_0_TLB_HI # restore high entry
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mtc0 a0, MIPS_COP_0_TLB_HI # restore high entry
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2:
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mtc0 t1, MIPS_COP_0_TLB_LO0 # even page to LO0
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li s1, MIPS3_PG_G # XXX set PG_G
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mtc0 a2, MIPS_COP_0_TLB_LO0 # even page to LO0
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li s1, MIPS3_PG_G # invalid page set PG_G
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mtc0 s1, MIPS_COP_0_TLB_LO1 # invalid page to LO1
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li s1, 2 # use TLB entry 2 for even page
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mtc0 s1, MIPS_COP_0_TLB_INDEX
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nop
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tlbwi # write odd page TLB entry
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move t1, t0 # odd page to LO1
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li t0, MIPS3_PG_G # XXX PG_G # clear LO0
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addi v0, v0, -NBPG * 2 # backup to odd page mapping
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move a2, a1 # odd page to LO1
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li a1, MIPS3_PG_G # LO0
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addi a0, a0, -NBPG * 2 # backup to odd page mapping
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# set up TLB entry 1
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1:
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# see if this address currently exists in TLB
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mtc0 v0, MIPS_COP_0_TLB_HI
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mtc0 a0, MIPS_COP_0_TLB_HI
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nop
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tlbp # probe for existing entry
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nop
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@ -2242,14 +2243,17 @@ NLEAF(mips3_cpu_switch_resume)
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nop
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tlbwi
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nop
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mtc0 v0, MIPS_COP_0_TLB_HI # restore high entry
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mtc0 a0, MIPS_COP_0_TLB_HI # restore high entry
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2:
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mtc0 t0, MIPS_COP_0_TLB_LO0 # first page
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mtc0 t1, MIPS_COP_0_TLB_LO1 # second page
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mtc0 a1, MIPS_COP_0_TLB_LO0 # first page
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mtc0 a2, MIPS_COP_0_TLB_LO1 # second page
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li s1, 1 # use TLB entry 1
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mtc0 s1, MIPS_COP_0_TLB_INDEX
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nop
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tlbwi # write TLB entry
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nop
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mtc0 a3, MIPS_COP_0_TLB_HI # set current ASID
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/*
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* Now running on new u struct.
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* Restore registers and return.
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.30 1997/07/29 01:41:46 mhitch Exp $ */
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/* $NetBSD: pmap.c,v 1.31 1997/08/09 03:41:08 jonathan Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -511,6 +511,21 @@ pmap_reference(pmap)
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}
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}
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/*
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* Make a new pmap (vmspace) active for the given process.
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*/
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void
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pmap_activate(register struct proc *p)
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{
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p->p_addr->u_pcb.pcb_segtab =
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p->p_vmspace->vm_map.pmap->pm_segtab;
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if (p == curproc) {
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register int tlbpid = pmap_alloc_tlbpid(p);
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MachSetPID(tlbpid);
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}
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}
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/*
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* Remove the given range of addresses from the specified map.
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*
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