- Withdraw a duplicated file. This has never been a part of distribution.
This commit is contained in:
nisimura
parent
5fedd08634
commit
8ed3c420dc
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@ -1,590 +0,0 @@
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/* $NetBSD: mips_cpu.h,v 1.4 1998/09/26 08:16:38 nisimura Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
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* This product includes software developed by the University of
|
||||
* California, Berkeley and its contributors.
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||||
* 4. Neither the name of the University nor the names of its contributors
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||||
* may be used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)machConst.h 8.1 (Berkeley) 6/10/93
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*
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* machConst.h --
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*
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* Machine dependent constants.
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*
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* Copyright (C) 1989 Digital Equipment Corporation.
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* Permission to use, copy, modify, and distribute this software and
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||||
* its documentation for any purpose and without fee is hereby granted,
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* provided that the above copyright notice appears in all copies.
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||||
* Digital Equipment Corporation makes no representations about the
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* suitability of this software for any purpose. It is provided "as is"
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* without express or implied warranty.
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*
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* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
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* v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
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* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
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* v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
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* from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
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* v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
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*/
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#ifndef _MIPS_CPU_H_
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#define _MIPS_CPU_H_
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/*
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* Address space.
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* 32-bit mips CPUS partition their 32-bit address space into four segments:
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*
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* kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
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* kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
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* kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
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* kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
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*
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* mips1 physical memory is limited to 512Mbytes, which is
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* doubly mapped in kseg0 (cached) and kseg1 (uncached.)
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* Caching of mapped addresses is controlled by bits in the TLB entry.
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*/
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#define MIPS_KUSEG_START 0x0
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#define MIPS_KSEG0_START 0x80000000
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#define MIPS_KSEG1_START 0xa0000000
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#define MIPS_KSEG2_START 0xc0000000
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#define MIPS_MAX_MEM_ADDR 0xbe000000
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#define MIPS_RESERVED_ADDR 0xbfc80000
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#define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
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#define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START)
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#define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
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#define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START)
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/* Map virtual address to index in mips3 r4k virtually-indexed cache */
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#define MIPS3_VA_TO_CINDEX(x) \
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((unsigned)(x) & 0xffffff | MIPS_KSEG0_START)
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/*
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* The bits in the cause register.
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*
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* Bits common to r3000 and r4000:
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*
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* MIPS_CR_BR_DELAY Exception happened in branch delay slot.
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* MIPS_CR_COP_ERR Coprocessor error.
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* MIPS_CR_IP Interrupt pending bits defined below.
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* (same meaning as in CAUSE register).
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* MIPS_CR_EXC_CODE The exception type (see exception codes below).
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*
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* Differences:
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* r3k has 4 bits of execption type, r4k has 5 bits.
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*/
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#define MIPS_CR_BR_DELAY 0x80000000
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#define MIPS_CR_COP_ERR 0x30000000
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#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */
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#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
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#define MIPS_CR_IP 0x0000FF00
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#define MIPS_CR_EXC_CODE_SHIFT 2
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/*
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* The bits in the status register. All bits are active when set to 1.
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*
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* R3000 status register fields:
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* MIPS_SR_CO_USABILITY Control the usability of the four coprocessors.
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* MIPS_SR_BOOT_EXC_VEC Use alternate exception vectors.
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* MIPS_SR_TLB_SHUTDOWN TLB disabled.
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*
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* MIPS_SR_INT_IE Master (current) interrupt enable bit.
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*
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* Differences:
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* r3k has cache control is via frobbing SR register bits, whereas the
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* r4k cache control is via explicit instructions.
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* r3k has a 3-entry stack of kernel/user bits, whereas the
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* r4k has kernel/supervisor/user.
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*/
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#define MIPS_SR_COP_USABILITY 0xf0000000
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#define MIPS_SR_COP_0_BIT 0x10000000
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#define MIPS_SR_COP_1_BIT 0x20000000
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/* r4k and r3k differences, see below */
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#define MIPS_SR_BOOT_EXC_VEC 0x00400000
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#define MIPS_SR_TLB_SHUTDOWN 0x00200000
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/* r4k and r3k differences, see below */
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#define MIPS_SR_INT_IE 0x00000001
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/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
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/*#define MIPS_SR_INT_MASK 0x0000ff00*/
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#define MIPS_SR_INT_ENAB MIPS_SR_INT_IE /* backwards compatibility */
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#define MIPS_SR_INT_ENA_CUR MIPS_SR_INT_IE /* backwards compatibility */
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/*
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* The R2000/R3000-specific status register bit definitions.
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* all bits are active when set to 1.
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*
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* MIPS_SR_PARITY_ERR Parity error.
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* MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss.
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* MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits.
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* MIPS_SR_SWAP_CACHES Swap I-cache and D-cache.
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* MIPS_SR_ISOL_CACHES Isolate D-cache from main memory.
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* Interrupt enable bits defined below.
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* MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode.
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* MIPS_SR_INT_ENA_OLD Old interrupt enable bit.
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* MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode.
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* MIPS_SR_INT_ENA_PREV Previous interrupt enable bit.
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* MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
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*/
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#define MIPS1_PARITY_ERR 0x00100000
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#define MIPS1_CACHE_MISS 0x00080000
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#define MIPS1_PARITY_ZERO 0x00040000
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#define MIPS1_SWAP_CACHES 0x00020000
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#define MIPS1_ISOL_CACHES 0x00010000
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#define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/
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#define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/
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#define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/
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#define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/
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#define MIPS1_SR_KU_CUR 0x00000002 /* current KU */
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/* backwards compatibility */
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#define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR
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#define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS
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#define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO
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#define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES
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#define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES
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#define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD
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#define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD
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#define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV
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#define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR
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#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
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/*
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* R4000 status register bit definitons,
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* where different from r2000/r3000.
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*/
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#define MIPS3_SR_RP 0x08000000
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#define MIPS3_SR_FR_32 0x04000000
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#define MIPS3_SR_RE 0x02000000
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#define MIPS3_SR_SOFT_RESET 0x00100000
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#define MIPS3_SR_DIAG_CH 0x00040000
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#define MIPS3_SR_DIAG_CE 0x00020000
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#define MIPS3_SR_DIAG_PE 0x00010000
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#define MIPS3_SR_KX 0x00000080
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#define MIPS3_SR_SX 0x00000040
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#define MIPS3_SR_UX 0x00000020
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#define MIPS3_SR_KSU_MASK 0x00000018
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#define MIPS3_SR_KSU_USER 0x00000010
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#define MIPS3_SR_KSU_SUPER 0x00000008
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#define MIPS3_SR_KSU_KERNEL 0x00000000
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#define MIPS3_SR_ERL 0x00000004
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#define MIPS3_SR_EXL 0x00000002
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#define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET
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#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH
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#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE
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#define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE
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#define MIPS_SR_KX MIPS3_SR_KX
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#define MIPS_SR_SX MIPS3_SR_SX
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#define MIPS_SR_UX MIPS3_SR_UX
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#define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK
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#define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER
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#define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER
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#define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL
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#define MIPS_SR_ERL MIPS3_SR_ERL
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#define MIPS_SR_EXL MIPS3_SR_EXL
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/*
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* The interrupt masks.
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* If a bit in the mask is 1 then the interrupt is enabled (or pending).
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*/
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#define MIPS_INT_MASK 0xff00
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#define MIPS_INT_MASK_5 0x8000
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#define MIPS_INT_MASK_4 0x4000
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#define MIPS_INT_MASK_3 0x2000
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#define MIPS_INT_MASK_2 0x1000
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#define MIPS_INT_MASK_1 0x0800
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#define MIPS_INT_MASK_0 0x0400
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#define MIPS_HARD_INT_MASK 0xfc00
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#define MIPS_SOFT_INT_MASK_1 0x0200
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#define MIPS_SOFT_INT_MASK_0 0x0100
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/*
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* nesting interrupt masks.
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*/
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#define MIPS_INT_MASK_SPL_SOFT0 MIPS_SOFT_INT_MASK_0
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#define MIPS_INT_MASK_SPL_SOFT1 (MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0)
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#define MIPS_INT_MASK_SPL0 (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1)
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#define MIPS_INT_MASK_SPL1 (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0)
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#define MIPS_INT_MASK_SPL2 (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1)
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#define MIPS_INT_MASK_SPL3 (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2)
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#define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3)
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#define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4)
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/*
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* mips3 CPUs have on-chip timer at INT_MASK_5. We don't support it yet.
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*/
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#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
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#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
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/*
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* The bits in the context register.
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*/
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#define MIPS1_CNTXT_PTE_BASE 0xFFE00000
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#define MIPS1_CNTXT_BAD_VPN 0x001FFFFC
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#define MIPS3_CNTXT_PTE_BASE 0xFF800000
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#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0
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/*
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* The bits in the MIPS3 config register.
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*
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* bit 0..5: R/W, Bit 6..31: R/O
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*/
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/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
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#define MIPS3_CONFIG_K0_MASK 0x00000007
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/*
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* R/W Update on Store Conditional
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* 0: Store Conditional uses coherency algorithm specified by TLB
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* 1: Store Conditional uses cacheable coherent update on write
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*/
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#define MIPS3_CONFIG_CU 0x00000008
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#define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */
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#define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */
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#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \
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(((config) & (bit)) ? 0x10 : 0x20)
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#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
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#define MIPS3_CONFIG_DC_SHIFT 6
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#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
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#define MIPS3_CONFIG_IC_SHIFT 9
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#define MIPS3_CONFIG_CACHE_SIZE(config, mask, shift) \
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(0x1000 << (((config) & (mask)) >> (shift)))
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/* Block ordering: 0: sequential, 1: sub-block */
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#define MIPS3_CONFIG_EB 0x00002000
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/* ECC mode - 0: ECC mode, 1: parity mode */
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#define MIPS3_CONFIG_EM 0x00004000
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/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
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#define MIPS3_CONFIG_BE 0x00008000
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/* Dirty Shared coherency state - 0: enabled, 1: disabled */
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#define MIPS3_CONFIG_SM 0x00010000
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/* Secondary Cache - 0: present, 1: not present */
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#define MIPS3_CONFIG_SC 0x00020000
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/* System Port width - 0: 64-bit, 1,2,3: reserved */
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#define MIPS3_CONFIG_EW_MASK 0x000c0000
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#define MIPS3_CONFIG_EW_SHIFT 18
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/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
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#define MIPS3_CONFIG_SW 0x00100000
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/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
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#define MIPS3_CONFIG_SS 0x00200000
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/* Secondary Cache line size */
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#define MIPS3_CONFIG_SB_MASK 0x00c00000
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#define MIPS3_CONFIG_SB_SHIFT 22
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#define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \
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(0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
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||||
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||||
/* write back data rate */
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#define MIPS3_CONFIG_EP_MASK 0x0f000000
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#define MIPS3_CONFIG_EP_SHIFT 24
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||||
/* System clock ratio - this value is CPU dependent */
|
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#define MIPS3_CONFIG_EC_MASK 0x70000000
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#define MIPS3_CONFIG_EC_SHIFT 28
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/* Master-Checker Mode - 1: enabled */
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#define MIPS3_CONFIG_CM 0x80000000
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/*
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* Location of exception vectors.
|
||||
*
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* Common vectors: reset and UTLB miss.
|
||||
*/
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#define MIPS_RESET_EXC_VEC 0xBFC00000
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#define MIPS_UTLB_MISS_EXC_VEC 0x80000000
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/*
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* R3000 general exception vector (everything else)
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*/
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#define MIPS1_GEN_EXC_VEC 0x80000080
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||||
/*
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||||
* R4000 MIPS-III exception vectors
|
||||
*/
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#define MIPS3_XTLB_MISS_EXC_VEC 0x80000080
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#define MIPS3_CACHE_ERR_EXC_VEC 0x80000100
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#define MIPS3_GEN_EXC_VEC 0x80000180
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/*
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* Values for the code field in a break instruction.
|
||||
*/
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#define MIPS_BREAK_INSTR 0x0000000d
|
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#define MIPS_BREAK_VAL_MASK 0x03ff0000
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#define MIPS_BREAK_VAL_SHIFT 16
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#define MIPS_BREAK_KDB_VAL 512
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#define MIPS_BREAK_SSTEP_VAL 513
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#define MIPS_BREAK_BRKPT_VAL 514
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#define MIPS_BREAK_SOVER_VAL 515
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#define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \
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(MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
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#define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \
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(MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
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#define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \
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(MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
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||||
#define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \
|
||||
(MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
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|
||||
/*
|
||||
* Mininum and maximum cache sizes.
|
||||
*/
|
||||
#define MIPS_MIN_CACHE_SIZE (16 * 1024)
|
||||
#define MIPS_MAX_CACHE_SIZE (256 * 1024)
|
||||
|
||||
/*
|
||||
* The floating point coprocessor status register bits.
|
||||
*/
|
||||
#define MIPS_FPU_ROUNDING_BITS 0x00000003
|
||||
#define MIPS_FPU_ROUND_RN 0x00000000
|
||||
#define MIPS_FPU_ROUND_RZ 0x00000001
|
||||
#define MIPS_FPU_ROUND_RP 0x00000002
|
||||
#define MIPS_FPU_ROUND_RM 0x00000003
|
||||
#define MIPS_FPU_STICKY_BITS 0x0000007c
|
||||
#define MIPS_FPU_STICKY_INEXACT 0x00000004
|
||||
#define MIPS_FPU_STICKY_UNDERFLOW 0x00000008
|
||||
#define MIPS_FPU_STICKY_OVERFLOW 0x00000010
|
||||
#define MIPS_FPU_STICKY_DIV0 0x00000020
|
||||
#define MIPS_FPU_STICKY_INVALID 0x00000040
|
||||
#define MIPS_FPU_ENABLE_BITS 0x00000f80
|
||||
#define MIPS_FPU_ENABLE_INEXACT 0x00000080
|
||||
#define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100
|
||||
#define MIPS_FPU_ENABLE_OVERFLOW 0x00000200
|
||||
#define MIPS_FPU_ENABLE_DIV0 0x00000400
|
||||
#define MIPS_FPU_ENABLE_INVALID 0x00000800
|
||||
#define MIPS_FPU_EXCEPTION_BITS 0x0003f000
|
||||
#define MIPS_FPU_EXCEPTION_INEXACT 0x00001000
|
||||
#define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000
|
||||
#define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000
|
||||
#define MIPS_FPU_EXCEPTION_DIV0 0x00008000
|
||||
#define MIPS_FPU_EXCEPTION_INVALID 0x00010000
|
||||
#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
|
||||
#define MIPS_FPU_COND_BIT 0x00800000
|
||||
#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
|
||||
#define MIPS1_FPC_MBZ_BITS 0xff7c0000
|
||||
#define MIPS3_FPC_MBZ_BITS 0xfe7c0000
|
||||
|
||||
|
||||
/*
|
||||
* Constants to determine if have a floating point instruction.
|
||||
*/
|
||||
#define MIPS_OPCODE_SHIFT 26
|
||||
#define MIPS_OPCODE_C1 0x11
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* The low part of the TLB entry.
|
||||
*/
|
||||
#define MIPS1_TLB_PHYS_PAGE_SHIFT 12
|
||||
#define MIPS1_TLB_PF_NUM 0xfffff000
|
||||
#define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800
|
||||
#define MIPS1_TLB_MOD_BIT 0x00000400
|
||||
#define MIPS1_TLB_VALID_BIT 0x00000200
|
||||
#define MIPS1_TLB_GLOBAL_BIT 0x00000100
|
||||
|
||||
#define MIPS3_TLB_PHYS_PAGE_SHIFT 6
|
||||
#define MIPS3_TLB_PF_NUM 0x3fffffc0
|
||||
|
||||
#define MIPS3_TLB_MOD_BIT 0x00000004
|
||||
#define MIPS3_TLB_VALID_BIT 0x00000002
|
||||
#define MIPS3_TLB_GLOBAL_BIT 0x00000001
|
||||
|
||||
/*
|
||||
* MIPS3_TLB_ATTR values - coherency algorithm:
|
||||
* 0: cacheable, noncoherent, write-through, no write allocate
|
||||
* 1: cacheable, noncoherent, write-through, write allocate
|
||||
* 2: uncached
|
||||
* 3: cacheable, noncoherent, write-back (noncoherent)
|
||||
* 4: cacheable, coherent, write-back, exclusive (exclusive)
|
||||
* 5: cacheable, coherent, write-back, exclusive on write (sharable)
|
||||
* 6: cacheable, coherent, write-back, update on write (update)
|
||||
* 7: cacheable, ?, ?, ?, ?
|
||||
*/
|
||||
#define MIPS3_TLB_ATTR_WT 0 /* IDT */
|
||||
#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
|
||||
#define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */
|
||||
#define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */
|
||||
#define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */
|
||||
#define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */
|
||||
#define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */
|
||||
|
||||
|
||||
/*
|
||||
* The high part of the TLB entry.
|
||||
*/
|
||||
#define MIPS_TLB_VIRT_PAGE_SHIFT 12
|
||||
|
||||
#define MIPS1_TLB_VIRT_PAGE_NUM 0xfffff000
|
||||
#define MIPS1_TLB_PID 0x00000fc0
|
||||
#define MIPS1_TLB_PID_SHIFT 6
|
||||
|
||||
#define MIPS3_TLB_VIRT_PAGE_NUM 0xffffe000
|
||||
#define MIPS3_TLB_PID 0x000000ff
|
||||
#define MIPS3_TLB_PID_SHIFT 0
|
||||
|
||||
|
||||
/*
|
||||
* r3000: shift count to put the index in the right spot.
|
||||
* (zero on r4000?)
|
||||
*/
|
||||
#define MIPS1_TLB_INDEX_SHIFT 8
|
||||
|
||||
|
||||
/*
|
||||
* The number of TLB entries and the first one that write random hits.
|
||||
*/
|
||||
#define MIPS1_TLB_NUM_TLB_ENTRIES 64
|
||||
#define MIPS1_TLB_FIRST_RAND_ENTRY 8
|
||||
|
||||
#define MIPS3_TLB_NUM_TLB_ENTRIES 48
|
||||
#define MIPS_R4300_TLB_NUM_TLB_ENTRIES 32
|
||||
#define MIPS3_TLB_WIRED_ENTRIES 8
|
||||
|
||||
|
||||
/*
|
||||
* The number of process id entries.
|
||||
*/
|
||||
#define MIPS1_TLB_NUM_PIDS 64
|
||||
#define MIPS3_TLB_NUM_PIDS 256
|
||||
|
||||
/*
|
||||
* backwards compatibility with existing locore and compile-time
|
||||
* mips1/mips3 binding.
|
||||
*
|
||||
* XXX INT_MASK and HARD_INT_MASK are here only because we dont
|
||||
* support the mips3 on-chip timer which is tied to INT_5.
|
||||
*/
|
||||
|
||||
#if defined(MIPS3) && !defined(MIPS1)
|
||||
#define MIPS_TLB_PID_SHIFT MIPS3_TLB_PID_SHIFT
|
||||
#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_PIDS
|
||||
#endif
|
||||
|
||||
#if !defined(MIPS3) && defined(MIPS1)
|
||||
#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
|
||||
#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(MIPS1) && defined(MIPS3)
|
||||
#define MIPS_TLB_PID_SHIFT \
|
||||
((CPUISMIPS3)? MIPS3_TLB_PID_SHIFT : MIPS1_TLB_PID_SHIFT)
|
||||
|
||||
#define MIPS_TLB_NUM_PIDS \
|
||||
((CPUISMIPS3)? MIPS3_TLB_NUM_PIDS : MIPS1_TLB_NUM_PIDS)
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* TLB probe return codes.
|
||||
*/
|
||||
#define MIPS_TLB_NOT_FOUND 0
|
||||
#define MIPS_TLB_FOUND 1
|
||||
#define MIPS_TLB_FOUND_WITH_PATCH 2
|
||||
#define MIPS_TLB_PROBE_ERROR 3
|
||||
|
||||
/*
|
||||
* CPU processor revision ID
|
||||
*/
|
||||
#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */
|
||||
#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */
|
||||
#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */
|
||||
#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */
|
||||
#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */
|
||||
#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */
|
||||
#define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 CPU ISA I */
|
||||
#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */
|
||||
#define MIPS_R4200 0x0a /* NEC VR4200 CPU ISA III */
|
||||
#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */
|
||||
#define MIPS_R4100 0x0c /* NEC VR4100 CPU ISA III */
|
||||
#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
|
||||
#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
|
||||
#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
|
||||
#define MIPS_R4650 0x22 /* ! QED R4650 ISA III */
|
||||
#define MIPS_TX3900 0x22 /* ! Toshiba R3000 based CPU ISA I */
|
||||
#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */
|
||||
#define MIPS_RC32364 0x26 /* IDT RC32364 CPU ISA II */
|
||||
#define MIPS_RM5230 0x28 /* QED RM5230 CPU ISA IV */
|
||||
#define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 CPU ISA III */
|
||||
#define MIPS_R3SONY 0x21 /* ? Sony R3000 based CPU ISA I */
|
||||
#define MIPS_R3NKK 0x23 /* ? NKK R3000 based CPU ISA I */
|
||||
|
||||
/*
|
||||
* FPU processor revision ID
|
||||
*/
|
||||
#define MIPS_SOFT 0x00 /* Software emulation ISA I */
|
||||
#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
|
||||
#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
|
||||
#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
|
||||
#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
|
||||
#define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */
|
||||
#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
|
||||
#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */
|
||||
#define MIPS_R4210 0x0a /* NEC VR4210 FPC ISA III */
|
||||
#define MIPS_R4300 0x0b /* NEC VR4300 FPC ISA III */
|
||||
#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
|
||||
#define MIPS_R4600 0x20 /* QED R4600 Orion FPU ISA III */
|
||||
#define MIPS_R5010 0x23 /* MIPS R5000 FPU ISA IV */
|
||||
#define MIPS_RC32364 0x26 /* IDT RC32364 FPU ISA II */
|
||||
#define MIPS_RM5230 0x28 /* QED RM5230 FPU ISA IV */
|
||||
#define MIPS_R3SONY 0x21 /* ? Sony R3000 based FPU ISA I */
|
||||
#define MIPS_R3TOSH 0x22 /* ? Toshiba R3000 based FPU ISA I */
|
||||
#define MIPS_R3NKK 0x23 /* ? NKK R3000 based FPU ISA I */
|
||||
|
||||
#endif /* _MIPS_CPU_H_ */
|
||||
Loading…
Reference in New Issue