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Kernel profiling. Don't profile the following: 

sigcode():
      executed from user-space stack.

  mips1_cpu_switch_resume, mips3_cpu_switch_resume:
      arguments passed in via v0, t0, t1 (outlined from cpu_switch())

  mips3_VCED(), mips3_VCEI():
      called from exception-vector code without any register save,
      $at, $ra are live.
This commit is contained in:
jonathan 1997-07-20 19:48:03 +00:00
parent 01794f87e3
commit 5ba85a4cf8
3 changed files with 28 additions and 8 deletions
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6
sys/arch/mips/mips/locore.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.40 1997/07/20 19:40:25 jonathan Exp $ */
/* $NetBSD: locore.S,v 1.41 1997/07/20 19:48:03 jonathan Exp $ */
/*
* Copyright (c) 1992, 1993
@ -205,8 +205,10 @@ _C_LABEL(kernel_text):
* This code is copied the user's stack for returning from signal handlers
* (see sendsig() and sigreturn()). We have to compute the address
* of the sigcontext struct for the sigreturn call.
*
* NB: we cannot profile sigcode(), it executes from userspace.
*/
LEAF(sigcode)
NLEAF(sigcode)
addu a0, sp, 16 # address of sigcontext
li v0, SYS_sigreturn # sigreturn(scp)
syscall

7
sys/arch/mips/mips/locore_r2000.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore_r2000.S,v 1.38 1997/07/07 03:54:33 jonathan Exp $ */
/* $NetBSD: locore_r2000.S,v 1.39 1997/07/20 19:48:13 jonathan Exp $ */
/*
* Copyright (c) 1992, 1993
@ -1655,8 +1655,11 @@ END(mips1_switch_exit)
* UADDR to the u-area. Then the following TLB entries are used to
* map the current u-area. Also, any current mapping for the u-area
* address space needs to be flushed as well.
*
* NB: cannot be profiled due to weird argument-assing convention.
* mcount would trash v0, t0, t1.
*/
LEAF(mips1_cpu_switch_resume)
NLEAF(mips1_cpu_switch_resume)
sll v0, v0, MIPS1_TLB_PID_SHIFT # v0 = aligned PID
or v0, v0, UADDR # v0 = first HI entry
mtc0 zero, MIPS_COP_0_TLB_INDEX # set the index register

23
sys/arch/mips/mips/locore_r4000.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore_r4000.S,v 1.39 1997/07/07 03:54:35 jonathan Exp $ */
/* $NetBSD: locore_r4000.S,v 1.40 1997/07/20 19:48:08 jonathan Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@ -1935,11 +1935,22 @@ END(mips3_InvalidateDCache)
*
* mips3_VCED --
*
* Handle virtual coherency exceptions
* Handle virtual coherency exceptions.
* Called directly from the mips3 execption-table code.
* only k0, k1 are avaiable on entry
*
* Results:
* None.
*
* Side effects:
* Remaps the conflicting address as uncached and returns
* from the execption.
*
* NB: cannot be profiled, all registers are user registers on entry.
*
*----------------------------------------------------------------------------
*/
LEAF(mips3_VCED)
NLEAF(mips3_VCED)
ALEAF(mips3_VCEI) /* XXXX */
.set noat
move k0, AT
@ -2135,6 +2146,7 @@ LEAF(mips3_switch_exit)
lw a0, kernel_map
la ra, sw1 # goto cpu_switch()
j kmem_free # free exiting USPACE
nop # XXX schedule better
END(mips3_switch_exit)
/*
@ -2155,8 +2167,11 @@ END(mips3_switch_exit)
* entries to map the u-area, depending upon whether the u-area
* begins on an even or odd page. Also, any current mapping for the u-area
* address space needs to be flushed as well.
*
* NB: cannot be profiled due to weird argument-assing convention.
* mcount would trash v0, t0, t1.
*/
LEAF(mips3_cpu_switch_resume)
NLEAF(mips3_cpu_switch_resume)
or v0, v0, UADDR # v0 = first HI entry
mtc0 zero, MIPS_COP_0_TLB_INDEX # set the index register
mtc0 v0, MIPS_COP_0_TLB_HI # init high entry