MIPS cpu-speed detection using mc146818 clock.
Compute CPU speed(MHz) and loop multiplier for DELAY() based on counting empty loop between mcclock ticks. New global: cpu_mhz. Change pmax/pmax/machdep.c to build baseboard model names from cpu_mhz. Set 'cpuspeed' for more realistic DELAY() on mips3 models. Mips CPU constants, testing, and calibration from D. Sean Davidson <davidson@zk3.dec.com> and Simon Burge <simonb@telstra.com.au>.
This commit is contained in:
jonathan
parent
003ccf3b1c
commit
95a12ee943
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@ -3,6 +3,7 @@ file arch/mips/mips/db_interface.c ddb
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file arch/mips/mips/db_trace.c ddb
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file arch/mips/mips/cpu_exec.c
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file arch/mips/mips/mem.c
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file arch/mips/mips/mips_mcclock.c clock # get CPU speed via mcclock
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file arch/mips/mips/pmap.c
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file arch/mips/mips/trap.c # interrupt, trap handlers
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file arch/mips/mips/vm_machdep.c
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@ -0,0 +1,275 @@
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/* $NetBSD: mips_mcclock.c,v 1.1 1997/08/09 05:51:57 jonathan Exp $ */
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/*
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* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Jonathan Stone for
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* the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: mips_mcclock.c,v 1.1 1997/08/09 05:51:57 jonathan Exp $");
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <dev/ic/mc146818reg.h> /* clock rates */
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#include <sys/param.h> /* guaranteed to get splXXX() */
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#include <machine/clock_machdep.h>
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#include <mips/cpu.h> /* CPUISMIPS3 */
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#include <mips/mips/mips_mcclock.h>
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#include <pmax/pmax/clockreg.h> /* XXX struct chiptime */
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extern u_int mips_read_causereg __P((void));
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unsigned mips_mc_cpuspeed __P((
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volatile struct chiptime *mcaddr, int clockmask,
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int (*tickpollfn) __P((volatile struct chiptime *mcclock_addr,
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int clockmask)) ));
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unsigned mips_mcclock_to_mhz __P((unsigned iters));
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int mips_mcclock_tickloop __P((volatile struct chiptime *mcclock_addr,
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int clockmask));
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/*
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* Estimate CPU cycle speed by counting cycles (acutally executions of a
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* one-line loop) between two adjacent ticks of an mc146818 clock.
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* Return loop iteration count so hand-calibrated MD code can
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* estimate clock speed from cycles.
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*
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* Runs before CPU is attached (so we can print CPU speed) which is
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* before the clock is attached, so we can't use the normal clock driver.
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*/
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unsigned
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mips_mc_cpuspeed(mcclock_addr, clockmask, tickpollfn)
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volatile struct chiptime *mcclock_addr;
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int clockmask;
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int (*tickpollfn) __P((volatile struct chiptime *mcclock_addr,
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int clockmask));
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{
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register int s;
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register int iters = 0;
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int saved_rega, saved_regb;
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/*
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* Block all interrupts, including clock ticks.
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*/
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s = splhigh();
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/*
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* Enable periodic interrupst on the mc146818,
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* and set it up for 256Hz (4ms) interrupts.
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* Save any state we change so we can restore it on exit.
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*/
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saved_rega = mcclock_addr->rega;
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saved_regb = mcclock_addr->regb;
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#if 0
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mcclock_addr->rega = (saved_rega & ~MC_BASE_RESET) | MC_RATE_256_Hz;
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mcclock_addr->regb = MC_REGB_BINARY|MC_REGB_24HR|MC_REGB_PIE;
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#else
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mcclock_addr->rega = MC_BASE_32_KHz | MC_RATE_256_Hz;
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mcclock_addr->regb = MC_REGB_BINARY|MC_REGB_24HR|MC_REGB_PIE| MC_REGB_SQWE;
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#endif
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/* count loop iterations between ticks */
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iters = (*tickpollfn)(mcclock_addr, clockmask);
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/* Restore mcclock registers */
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mcclock_addr->rega = saved_rega;
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mcclock_addr->regb = saved_regb;
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splx(s);
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/*
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* Compute approximate CPU speed in MHz, and an
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* appropriate base for DELAY() and delay(), from
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* the number of completed iterations.
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*/
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cpu_mhz = mips_mcclock_to_mhz(iters);
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#if defined(DEBUG) || defined(DIAGNOSTIC) || 1
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printf("mcclock: iters %d computed MHz %d, instrs per usec=%d\n",
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iters, cpu_mhz, cpuspeed);
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#endif
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return (iters);
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}
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/*
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* Poll mcclock chip for the next tick interrupt and count
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* instructions until the subsequent tick.
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*
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* XXX Assumes the mcclock chip has exclusive use of a CPU interrupt line.
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* XXX Assumes bus access to clock registers is cheap (not a function call).
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* MD alternatives must be used where this doesn't hold.
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*/
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int
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mips_mcclock_tickloop(mcclock_addr, clockmask)
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volatile struct chiptime *mcclock_addr;
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int clockmask;
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{
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register int iters = 0;
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register volatile int junk;
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/* clear any old pending interrupts */
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junk = mcclock_addr->regc;
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junk++; junk++; junk++; junk++;
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/* Poll clock interrupt, waiting for next tick to happen. */
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while ((mips_read_causereg() & clockmask) == 0)
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;
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/* Ack the mc146818 interrupt caused by starting tick. */
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junk = mcclock_addr->regc;
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junk++; junk++; junk++; junk++;
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/* Count loops until next tick-interrupt request occurs (4ms). */
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if (CPUISMIPS3) {
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while ((mips_read_causereg() & clockmask) == 0) {
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__asm __volatile ("nop; nop; nop; nop");
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iters++;
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}
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} else {
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while ((mips_read_causereg() & clockmask) == 0)
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iters++;
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}
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/* Ack the interrupt from the just-gone-off tick */
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junk = mcclock_addr->regc;
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return (iters);
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}
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/*
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* Compute MHz and DELAY() constants using the default
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* polling function.
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*/
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unsigned
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mc_cpuspeed(mcclock_addr, clockmask)
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volatile struct chiptime *mcclock_addr;
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int clockmask;
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{
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return mips_mc_cpuspeed(mcclock_addr, clockmask,
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mips_mcclock_tickloop);
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}
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/*
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* mips_mcclock_to_mhz(iters) -- convert an mcclock cycles-per-tick count
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* to a CPU speed in MHz.
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*
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* Side Effects:
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* set the global variables "cpuspeed", used by DELAY() and delay()
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* as an instructions-per-microsecond multiplier, to an value appropriate
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* for the estimated clock speed.
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*/
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unsigned
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mips_mcclock_to_mhz(unsigned iters)
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{
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register unsigned mhz = 0;
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/* XXX KN01? */
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/*
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* Measured thresholds for Digital systems from Sean Davidson.
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*
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* r3000-core DECstations values fit to:
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* iters per 4ms tick = 425 * MHz)
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* instructions per mhz = kHz * 575
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* with about 2 Mhz slop to allow for variation.
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*/
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#ifdef MIPS3
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if (CPUISMIPS3) {
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if (iters < 18100) {
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/* error */
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printf("mcclock loop count %d too low for r4000\n",
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iters);
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mhz = 45;
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cpuspeed = 90; /* XXX */
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} else if (iters < 20000) {
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mhz = 50;
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cpuspeed = 100; /* XXX */
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} else if (iters < 24110) {
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mhz = 60;
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cpuspeed = 110; /* XXX */
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} else if (iters < 27140) {
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mhz = 67;
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cpuspeed = 130; /* XXX */
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} else if (iters < 30000) {
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mhz = 75;
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cpuspeed = 150; /* XXX */
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}
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}
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#endif /* MIPS3 */
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#ifdef MIPS1
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if (!CPUISMIPS3) {
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if (iters < 8800) {
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mhz = 20;
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cpuspeed = 11;
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} else if (iters < 11300) {
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mhz = 25;
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cpuspeed = 13;
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} else if (iters < 14000) {
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mhz = 33;
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cpuspeed = 19;
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} else if (iters < 15000) {
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mhz = 36;
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cpuspeed = 21;
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} else if (iters < 16000) {
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mhz = 40;
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cpuspeed = 23;
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} else if (iters < 18800) {
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mhz = 45;
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cpuspeed = 25;
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} else if (iters < 21000) {
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mhz = 50;
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cpuspeed = 29;
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} else if (iters < 26000) {
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mhz = 60;
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cpuspeed = 35;
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} else {
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/* XXX */
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mhz = 70;
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cpuspeed = 40;
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}
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}
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#endif /* MIPS1 */
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return (mhz);
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}
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@ -0,0 +1,51 @@
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/* $NetBSD: mips_mcclock.h,v 1.1 1997/08/09 05:51:58 jonathan Exp $ */
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/*
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* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Jonathan Stone for
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* the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _MIPS_MCCLOCK_H_
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#define _MIPS_MCCLOCK_H_
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/*
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* Estimate CPU speed and multiplier for DELAY() by polling mcclock,
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* couting iterations of an loop between successive ticks.
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*/
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struct chiptime;
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unsigned mc_cpuspeed __P((volatile struct chiptime *mcaddr, int clockmask));
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/*
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* CPU speed in MHz, as estimated by mc_cpuspeed(). Read-only.
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*/
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extern int cpu_mhz;
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.93 1997/08/06 12:03:37 jonathan Exp $ */
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/* $NetBSD: machdep.c,v 1.94 1997/08/09 05:51:59 jonathan Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -85,6 +85,8 @@
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#include <machine/pte.h>
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#include <machine/autoconf.h>
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#include <mips/locore.h> /* wbflush() */
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#include <mips/mips/mips_mcclock.h> /* mclock CPU setimation */
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#ifdef DDB
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#include <mips/db_machdep.h>
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#endif
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@ -244,6 +246,8 @@ void kn02_enable_intr __P ((u_int slotno,
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#ifdef DS5000_100
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void kmin_enable_intr __P ((u_int slotno, int (*handler) (intr_arg_t sc),
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intr_arg_t sc, int onoff));
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void kmin_mcclock_cpuspeed __P((volatile struct chiptime *mcclock_addr,
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int clockmask));
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#endif /*DS5000_100*/
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#ifdef DS5000_25
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@ -286,7 +290,6 @@ struct proc nullproc; /* for use by switch_exit() */
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/* locore callback-vector setup */
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extern void mips_vector_init __P((void));
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/*
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* Do all the stuff that locore normally does before calling main().
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* Process arguments passed to us by the prom monitor.
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@ -508,6 +511,8 @@ mach_init(argc, argv, code, cv)
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mcclock_addr = (volatile struct chiptime *)
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MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK);
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mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_3);
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strcpy(cpu_model, "3100");
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break;
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#endif /* DS3100 */
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@ -563,6 +568,7 @@ mach_init(argc, argv, code, cv)
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MIPS_PHYS_TO_KSEG1(KN02_SYS_CLOCK);
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}
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mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_1);
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strcpy(cpu_model, "5000/200");
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break;
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#endif /* DS5000_200 */
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@ -594,7 +600,7 @@ mach_init(argc, argv, code, cv)
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Mach_splstatclock = splhigh;
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mcclock_addr = (volatile struct chiptime *)
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MIPS_PHYS_TO_KSEG1(KMIN_SYS_CLOCK);
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kmin_mcclock_cpuspeed(mcclock_addr, MIPS_INT_MASK_3);
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/*
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* Initialize interrupts.
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@ -607,7 +613,8 @@ mach_init(argc, argv, code, cv)
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(u_int*)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT);
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(*Mach_reset_addr) = 0;
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strcpy(cpu_model, (CPUISMIPS3)? "5000/150": "5000/1xx");
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sprintf(cpu_model, (CPUISMIPS3)? "5000/1%d": "5000/%d",
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cpu_mhz);
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/*
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* The kmin memory hardware seems to wrap memory addresses
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@ -654,6 +661,7 @@ mach_init(argc, argv, code, cv)
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Mach_splstatclock = cpu_spl3;
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mcclock_addr = (volatile struct chiptime *)
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MIPS_PHYS_TO_KSEG1(XINE_SYS_CLOCK);
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mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_1);
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/*
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* Initialize interrupts.
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@ -665,7 +673,7 @@ mach_init(argc, argv, code, cv)
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(u_int*)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT);
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(*Mach_reset_addr) = 0;
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strcpy(cpu_model, (CPUISMIPS3) ? "5000/50": "5000/25");
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sprintf(cpu_model, "5000/%d", cpu_mhz);
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break;
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#endif /*DS5000_25*/
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@ -699,6 +707,7 @@ mach_init(argc, argv, code, cv)
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Mach_splstatclock = cpu_spl1;
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mcclock_addr = (volatile struct chiptime *)
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MIPS_PHYS_TO_KSEG1(KN03_SYS_CLOCK);
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mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_1);
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asic_init(0);
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/*
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@ -714,7 +723,7 @@ mach_init(argc, argv, code, cv)
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/* clear any memory errors from probes */
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*Mach_reset_addr = 0;
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strcpy(cpu_model, (CPUISMIPS3) ? "5000/260" : "5000/240");
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sprintf(cpu_model, "5000/2%d", cpu_mhz);
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break;
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#endif /* DS5000_240 */
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@ -1564,6 +1573,35 @@ kmin_enable_intr(slotno, handler, sc, on)
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tc_slot_info[slotno].sc = 0;
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||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Count instructions between 4ms mcclock interrupt requests,
|
||||
* using the ioasic clock-interrupt-pending bit to determine
|
||||
* when clock ticks occur.
|
||||
* Set up iosiac to allow only clock interrupts, then
|
||||
* call
|
||||
*/
|
||||
void
|
||||
kmin_mcclock_cpuspeed(mcclock_addr, clockmask)
|
||||
volatile struct chiptime *mcclock_addr;
|
||||
int clockmask;
|
||||
{
|
||||
register volatile u_int * ioasic_intrmaskp =
|
||||
(volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK);
|
||||
|
||||
register int saved_imask = *ioasic_intrmaskp;
|
||||
|
||||
/* Allow only clock interrupts through ioasic. */
|
||||
*ioasic_intrmaskp = KMIN_INTR_CLOCK;
|
||||
wbflush();
|
||||
|
||||
mc_cpuspeed(mcclock_addr, clockmask);
|
||||
|
||||
*ioasic_intrmaskp = saved_imask;
|
||||
wbflush();
|
||||
}
|
||||
|
||||
|
||||
#endif /*DS5000_100*/
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue